2017-06-16 22:38:21 +02:00
|
|
|
/*
|
|
|
|
|
* Copyright 2017 Józef Kucia for CodeWeavers
|
|
|
|
|
*
|
|
|
|
|
* This library is free software; you can redistribute it and/or
|
|
|
|
|
* modify it under the terms of the GNU Lesser General Public
|
|
|
|
|
* License as published by the Free Software Foundation; either
|
|
|
|
|
* version 2.1 of the License, or (at your option) any later version.
|
|
|
|
|
*
|
|
|
|
|
* This library is distributed in the hope that it will be useful,
|
|
|
|
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
|
|
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
|
|
|
|
* Lesser General Public License for more details.
|
|
|
|
|
*
|
|
|
|
|
* You should have received a copy of the GNU Lesser General Public
|
|
|
|
|
* License along with this library; if not, write to the Free Software
|
|
|
|
|
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA
|
2017-06-16 22:38:21 +02:00
|
|
|
*
|
|
|
|
|
* This file incorporates work covered by the following copyright and
|
|
|
|
|
* permission notice:
|
|
|
|
|
*
|
|
|
|
|
* Copyright 2002-2003 The wine-d3d team
|
|
|
|
|
* Copyright 2002-2003 2004 Jason Edmeades
|
|
|
|
|
* Copyright 2002-2003 Raphael Junqueira
|
|
|
|
|
* Copyright 2005 Oliver Stieber
|
|
|
|
|
* Copyright 2006 Stefan Dösinger
|
|
|
|
|
* Copyright 2006-2011, 2013 Stefan Dösinger for CodeWeavers
|
|
|
|
|
* Copyright 2007 Henri Verbeet
|
2017-06-16 22:38:21 +02:00
|
|
|
* Copyright 2008-2009 Henri Verbeet for CodeWeavers
|
2017-06-16 22:38:21 +02:00
|
|
|
*
|
|
|
|
|
* This library is free software; you can redistribute it and/or
|
|
|
|
|
* modify it under the terms of the GNU Lesser General Public
|
|
|
|
|
* License as published by the Free Software Foundation; either
|
|
|
|
|
* version 2.1 of the License, or (at your option) any later version.
|
|
|
|
|
*
|
|
|
|
|
* This library is distributed in the hope that it will be useful,
|
|
|
|
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
|
|
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
|
|
|
|
* Lesser General Public License for more details.
|
|
|
|
|
*
|
|
|
|
|
* You should have received a copy of the GNU Lesser General Public
|
|
|
|
|
* License along with this library; if not, write to the Free Software
|
|
|
|
|
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA
|
2017-06-16 22:38:21 +02:00
|
|
|
*/
|
|
|
|
|
|
|
|
|
|
#ifndef __VKD3D_SHADER_PRIVATE_H
|
|
|
|
|
#define __VKD3D_SHADER_PRIVATE_H
|
|
|
|
|
|
2017-06-27 13:16:47 +02:00
|
|
|
#define NONAMELESSUNION
|
2017-06-16 22:38:21 +02:00
|
|
|
#include "vkd3d_common.h"
|
|
|
|
|
#include "vkd3d_memory.h"
|
|
|
|
|
#include "vkd3d_shader.h"
|
|
|
|
|
#include "list.h"
|
|
|
|
|
|
|
|
|
|
#include <inttypes.h>
|
|
|
|
|
#include <limits.h>
|
|
|
|
|
#include <stdbool.h>
|
2017-09-11 22:35:16 +02:00
|
|
|
#include <string.h>
|
2017-06-16 22:38:21 +02:00
|
|
|
|
|
|
|
|
#define VKD3D_VEC4_SIZE 4
|
2021-07-30 23:27:20 +10:00
|
|
|
#define VKD3D_DVEC2_SIZE 2
|
2017-06-16 22:38:21 +02:00
|
|
|
|
2025-02-05 17:54:39 +01:00
|
|
|
#define VKD3D_SHADER_COMPONENT_TYPE_COUNT (VKD3D_SHADER_COMPONENT_INT16 + 1)
|
2024-10-09 17:12:17 +02:00
|
|
|
#define VKD3D_SHADER_MINIMUM_PRECISION_COUNT (VKD3D_SHADER_MINIMUM_PRECISION_UINT_16 + 1)
|
2025-03-28 10:39:43 +01:00
|
|
|
#define VKD3D_SHADER_DESCRIPTOR_TYPE_COUNT (VKD3D_SHADER_DESCRIPTOR_TYPE_SAMPLER + 1)
|
2025-03-28 10:42:44 +01:00
|
|
|
#define VKD3D_SHADER_RESOURCE_TYPE_COUNT (VKD3D_SHADER_RESOURCE_TEXTURE_CUBEARRAY + 1)
|
vkd3d-shader/spirv: Cache numeric types without through the general declaration cache.
Numeric types are used very frequently, and doing a tree search
each time one is needed tends to waste a lot of time.
I ran the compilation of ~1000 DXBC-TPF shaders randomly taken from
my collection and measured the performance using callgrind and the
kcachegrind "cycle count" estimation.
BEFORE:
* 1,764,035,136 cycles
* 1,767,948,767 cycles
* 1,773,927,734 cycles
AFTER:
* 1,472,384,755 cycles
* 1,469,506,188 cycles
* 1,470,191,425 cycles
So callgrind would estimate a 16% improvement at least.
2024-09-19 15:00:28 +02:00
|
|
|
|
2024-12-09 10:39:43 +01:00
|
|
|
#define VKD3D_MAX_STREAM_COUNT 4
|
|
|
|
|
|
2020-07-23 13:41:25 +04:30
|
|
|
enum vkd3d_shader_error
|
|
|
|
|
{
|
2020-07-30 14:59:58 +04:30
|
|
|
VKD3D_SHADER_ERROR_DXBC_INVALID_SIZE = 1,
|
|
|
|
|
VKD3D_SHADER_ERROR_DXBC_INVALID_MAGIC = 2,
|
|
|
|
|
VKD3D_SHADER_ERROR_DXBC_INVALID_CHECKSUM = 3,
|
|
|
|
|
VKD3D_SHADER_ERROR_DXBC_INVALID_VERSION = 4,
|
|
|
|
|
VKD3D_SHADER_ERROR_DXBC_INVALID_CHUNK_OFFSET = 5,
|
|
|
|
|
VKD3D_SHADER_ERROR_DXBC_INVALID_CHUNK_SIZE = 6,
|
2023-02-20 17:11:18 +01:00
|
|
|
VKD3D_SHADER_ERROR_DXBC_OUT_OF_MEMORY = 7,
|
2023-03-07 14:04:44 +10:00
|
|
|
VKD3D_SHADER_ERROR_DXBC_INVALID_SIGNATURE = 8,
|
2025-02-05 16:34:14 +01:00
|
|
|
VKD3D_SHADER_ERROR_DXBC_INVALID_STRING_REFERENCE = 9,
|
2025-02-05 17:38:21 +01:00
|
|
|
VKD3D_SHADER_ERROR_DXBC_INVALID_COMPONENT_TYPE = 10,
|
2020-07-30 14:59:58 +04:30
|
|
|
|
|
|
|
|
VKD3D_SHADER_ERROR_TPF_MISMATCHED_CF = 1000,
|
2021-07-02 13:12:48 +10:00
|
|
|
VKD3D_SHADER_ERROR_TPF_INVALID_REGISTER_RANGE = 1001,
|
2023-01-20 11:35:38 +10:00
|
|
|
VKD3D_SHADER_ERROR_TPF_OUT_OF_MEMORY = 1002,
|
2023-05-03 17:10:37 +10:00
|
|
|
VKD3D_SHADER_ERROR_TPF_INVALID_REGISTER_INDEX_COUNT = 1003,
|
2023-05-03 17:17:24 +10:00
|
|
|
VKD3D_SHADER_ERROR_TPF_TOO_MANY_REGISTERS = 1004,
|
2023-05-03 17:24:24 +10:00
|
|
|
VKD3D_SHADER_ERROR_TPF_INVALID_IO_REGISTER = 1005,
|
2023-05-04 16:56:30 +10:00
|
|
|
VKD3D_SHADER_ERROR_TPF_INVALID_INDEX_RANGE_DCL = 1006,
|
2023-08-28 12:55:47 +10:00
|
|
|
VKD3D_SHADER_ERROR_TPF_INVALID_CASE_VALUE = 1007,
|
2023-08-08 11:38:26 +10:00
|
|
|
VKD3D_SHADER_ERROR_TPF_INVALID_REGISTER_DIMENSION = 1008,
|
|
|
|
|
VKD3D_SHADER_ERROR_TPF_INVALID_REGISTER_SWIZZLE = 1009,
|
2024-09-16 16:11:11 +02:00
|
|
|
VKD3D_SHADER_ERROR_TPF_INVALID_REGISTER_DCL = 1010,
|
2020-07-30 14:59:58 +04:30
|
|
|
|
2023-05-03 17:19:32 +10:00
|
|
|
VKD3D_SHADER_WARNING_TPF_MASK_NOT_CONTIGUOUS = 1300,
|
2023-05-04 16:56:30 +10:00
|
|
|
VKD3D_SHADER_WARNING_TPF_UNHANDLED_INDEX_RANGE_MASK = 1301,
|
2023-08-08 12:09:10 +10:00
|
|
|
VKD3D_SHADER_WARNING_TPF_UNHANDLED_REGISTER_MASK = 1302,
|
2023-08-08 12:29:20 +10:00
|
|
|
VKD3D_SHADER_WARNING_TPF_UNHANDLED_REGISTER_SWIZZLE = 1303,
|
2023-05-03 17:19:32 +10:00
|
|
|
|
2020-08-04 14:43:29 +04:30
|
|
|
VKD3D_SHADER_ERROR_SPV_DESCRIPTOR_BINDING_NOT_FOUND = 2000,
|
2020-08-04 14:43:30 +04:30
|
|
|
VKD3D_SHADER_ERROR_SPV_INVALID_REGISTER_TYPE = 2001,
|
2020-08-20 23:39:42 +04:30
|
|
|
VKD3D_SHADER_ERROR_SPV_INVALID_DESCRIPTOR_BINDING = 2002,
|
2021-07-23 23:01:37 +10:00
|
|
|
VKD3D_SHADER_ERROR_SPV_DESCRIPTOR_IDX_UNSUPPORTED = 2003,
|
2023-11-23 00:10:15 +10:00
|
|
|
VKD3D_SHADER_ERROR_SPV_UNSUPPORTED_FEATURE = 2004,
|
2023-05-18 15:51:53 +10:00
|
|
|
VKD3D_SHADER_ERROR_SPV_OUT_OF_MEMORY = 2005,
|
2023-11-04 00:16:44 +10:00
|
|
|
VKD3D_SHADER_ERROR_SPV_INVALID_TYPE = 2006,
|
2023-11-04 00:17:11 +10:00
|
|
|
VKD3D_SHADER_ERROR_SPV_INVALID_HANDLER = 2007,
|
2023-11-14 00:50:30 +10:00
|
|
|
VKD3D_SHADER_ERROR_SPV_NOT_IMPLEMENTED = 2008,
|
2023-09-25 15:00:12 +02:00
|
|
|
VKD3D_SHADER_ERROR_SPV_INVALID_SHADER = 2009,
|
2020-08-04 14:43:29 +04:30
|
|
|
|
2023-08-08 11:38:26 +10:00
|
|
|
VKD3D_SHADER_WARNING_SPV_INVALID_SWIZZLE = 2300,
|
2023-08-16 13:46:10 +10:00
|
|
|
VKD3D_SHADER_WARNING_SPV_INVALID_UAV_FLAGS = 2301,
|
2024-04-04 19:10:55 +10:00
|
|
|
VKD3D_SHADER_WARNING_SPV_IGNORING_FLAG = 2302,
|
2023-08-08 11:38:26 +10:00
|
|
|
|
2020-07-30 14:59:58 +04:30
|
|
|
VKD3D_SHADER_ERROR_RS_OUT_OF_MEMORY = 3000,
|
|
|
|
|
VKD3D_SHADER_ERROR_RS_INVALID_VERSION = 3001,
|
|
|
|
|
VKD3D_SHADER_ERROR_RS_INVALID_ROOT_PARAMETER_TYPE = 3002,
|
|
|
|
|
VKD3D_SHADER_ERROR_RS_INVALID_DESCRIPTOR_RANGE_TYPE = 3003,
|
|
|
|
|
VKD3D_SHADER_ERROR_RS_MIXED_DESCRIPTOR_RANGE_TYPES = 3004,
|
2020-12-15 17:13:20 -06:00
|
|
|
|
|
|
|
|
VKD3D_SHADER_ERROR_PP_INVALID_SYNTAX = 4000,
|
2021-01-14 14:47:50 -06:00
|
|
|
VKD3D_SHADER_ERROR_PP_ERROR_DIRECTIVE = 4001,
|
2021-01-07 11:48:09 -06:00
|
|
|
VKD3D_SHADER_ERROR_PP_INCLUDE_FAILED = 4002,
|
2020-12-21 14:37:06 -06:00
|
|
|
|
2021-01-07 11:48:06 -06:00
|
|
|
VKD3D_SHADER_WARNING_PP_ALREADY_DEFINED = 4300,
|
2020-12-21 14:37:06 -06:00
|
|
|
VKD3D_SHADER_WARNING_PP_INVALID_DIRECTIVE = 4301,
|
2021-01-12 16:14:19 -06:00
|
|
|
VKD3D_SHADER_WARNING_PP_ARGUMENT_COUNT_MISMATCH = 4302,
|
2020-12-21 14:37:06 -06:00
|
|
|
VKD3D_SHADER_WARNING_PP_UNKNOWN_DIRECTIVE = 4303,
|
2021-01-12 16:14:19 -06:00
|
|
|
VKD3D_SHADER_WARNING_PP_UNTERMINATED_MACRO = 4304,
|
2020-12-21 14:37:06 -06:00
|
|
|
VKD3D_SHADER_WARNING_PP_UNTERMINATED_IF = 4305,
|
2021-01-19 11:18:19 -06:00
|
|
|
VKD3D_SHADER_WARNING_PP_DIV_BY_ZERO = 4306,
|
2021-02-21 22:04:36 -06:00
|
|
|
|
|
|
|
|
VKD3D_SHADER_ERROR_HLSL_INVALID_SYNTAX = 5000,
|
|
|
|
|
VKD3D_SHADER_ERROR_HLSL_INVALID_MODIFIER = 5001,
|
|
|
|
|
VKD3D_SHADER_ERROR_HLSL_INVALID_TYPE = 5002,
|
|
|
|
|
VKD3D_SHADER_ERROR_HLSL_MODIFIES_CONST = 5003,
|
|
|
|
|
VKD3D_SHADER_ERROR_HLSL_MISSING_SEMANTIC = 5004,
|
|
|
|
|
VKD3D_SHADER_ERROR_HLSL_NOT_DEFINED = 5005,
|
|
|
|
|
VKD3D_SHADER_ERROR_HLSL_REDEFINED = 5006,
|
|
|
|
|
VKD3D_SHADER_ERROR_HLSL_WRONG_PARAMETER_COUNT = 5007,
|
|
|
|
|
VKD3D_SHADER_ERROR_HLSL_INVALID_SIZE = 5008,
|
|
|
|
|
VKD3D_SHADER_ERROR_HLSL_MISSING_INITIALIZER = 5009,
|
|
|
|
|
VKD3D_SHADER_ERROR_HLSL_INVALID_LVALUE = 5010,
|
|
|
|
|
VKD3D_SHADER_ERROR_HLSL_INVALID_WRITEMASK = 5011,
|
|
|
|
|
VKD3D_SHADER_ERROR_HLSL_INVALID_INDEX = 5012,
|
|
|
|
|
VKD3D_SHADER_ERROR_HLSL_INVALID_SEMANTIC = 5013,
|
|
|
|
|
VKD3D_SHADER_ERROR_HLSL_INVALID_RETURN = 5014,
|
2021-06-23 23:57:35 -05:00
|
|
|
VKD3D_SHADER_ERROR_HLSL_OVERLAPPING_RESERVATIONS = 5015,
|
|
|
|
|
VKD3D_SHADER_ERROR_HLSL_INVALID_RESERVATION = 5016,
|
2021-08-13 16:03:24 +02:00
|
|
|
VKD3D_SHADER_ERROR_HLSL_NOT_IMPLEMENTED = 5017,
|
2022-01-26 15:35:30 +01:00
|
|
|
VKD3D_SHADER_ERROR_HLSL_INVALID_TEXEL_OFFSET = 5018,
|
2022-02-24 15:06:15 +01:00
|
|
|
VKD3D_SHADER_ERROR_HLSL_OFFSET_OUT_OF_BOUNDS = 5019,
|
2022-02-28 12:23:43 +01:00
|
|
|
VKD3D_SHADER_ERROR_HLSL_INCOMPATIBLE_PROFILE = 5020,
|
2022-04-14 12:52:39 +02:00
|
|
|
VKD3D_SHADER_ERROR_HLSL_DIVISION_BY_ZERO = 5021,
|
2022-07-22 11:40:24 -04:00
|
|
|
VKD3D_SHADER_ERROR_HLSL_NON_STATIC_OBJECT_REF = 5022,
|
2021-08-16 17:29:34 -05:00
|
|
|
VKD3D_SHADER_ERROR_HLSL_INVALID_THREAD_COUNT = 5023,
|
|
|
|
|
VKD3D_SHADER_ERROR_HLSL_MISSING_ATTRIBUTE = 5024,
|
2021-09-11 11:20:32 -05:00
|
|
|
VKD3D_SHADER_ERROR_HLSL_RECURSIVE_CALL = 5025,
|
2022-11-25 20:38:33 -03:00
|
|
|
VKD3D_SHADER_ERROR_HLSL_INCONSISTENT_SAMPLER = 5026,
|
2023-07-05 10:39:04 +02:00
|
|
|
VKD3D_SHADER_ERROR_HLSL_NON_FINITE_RESULT = 5027,
|
2023-10-11 13:55:32 +02:00
|
|
|
VKD3D_SHADER_ERROR_HLSL_DUPLICATE_SWITCH_CASE = 5028,
|
2024-02-23 02:11:38 +01:00
|
|
|
VKD3D_SHADER_ERROR_HLSL_MISSING_TECHNIQUE = 5029,
|
2024-02-25 02:42:54 +01:00
|
|
|
VKD3D_SHADER_ERROR_HLSL_UNKNOWN_MODIFIER = 5030,
|
2024-06-06 17:50:05 -04:00
|
|
|
VKD3D_SHADER_ERROR_HLSL_INVALID_STATE_BLOCK_ENTRY = 5031,
|
2024-04-11 11:11:14 -03:00
|
|
|
VKD3D_SHADER_ERROR_HLSL_FAILED_FORCED_UNROLL = 5032,
|
2024-06-24 17:30:46 -04:00
|
|
|
VKD3D_SHADER_ERROR_HLSL_INVALID_PROFILE = 5033,
|
|
|
|
|
VKD3D_SHADER_ERROR_HLSL_MISPLACED_COMPILE = 5034,
|
2024-08-24 10:08:53 -04:00
|
|
|
VKD3D_SHADER_ERROR_HLSL_INVALID_DOMAIN = 5035,
|
2024-09-03 15:30:40 -04:00
|
|
|
VKD3D_SHADER_ERROR_HLSL_INVALID_CONTROL_POINT_COUNT = 5036,
|
2024-08-24 10:12:34 -04:00
|
|
|
VKD3D_SHADER_ERROR_HLSL_INVALID_OUTPUT_PRIMITIVE = 5037,
|
2024-09-03 15:09:24 -04:00
|
|
|
VKD3D_SHADER_ERROR_HLSL_INVALID_PARTITIONING = 5038,
|
2024-08-26 16:43:20 -04:00
|
|
|
VKD3D_SHADER_ERROR_HLSL_MISPLACED_SAMPLER_STATE = 5039,
|
2024-12-02 15:18:15 +01:00
|
|
|
VKD3D_SHADER_ERROR_HLSL_AMBIGUOUS_CALL = 5040,
|
2025-01-20 15:39:31 -05:00
|
|
|
VKD3D_SHADER_ERROR_HLSL_DUPLICATE_PATCH = 5041,
|
2025-03-10 16:32:42 -04:00
|
|
|
VKD3D_SHADER_ERROR_HLSL_INVALID_MAX_VERTEX_COUNT = 5042,
|
2025-03-10 16:21:08 -04:00
|
|
|
VKD3D_SHADER_ERROR_HLSL_MISSING_PRIMITIVE_TYPE = 5043,
|
2025-03-06 11:17:29 -05:00
|
|
|
VKD3D_SHADER_ERROR_HLSL_MISPLACED_STREAM_OUTPUT = 5044,
|
2025-05-15 16:23:15 -04:00
|
|
|
VKD3D_SHADER_ERROR_HLSL_MISSING_INPUT_PATCH = 5045,
|
2021-02-21 22:04:36 -06:00
|
|
|
|
|
|
|
|
VKD3D_SHADER_WARNING_HLSL_IMPLICIT_TRUNCATION = 5300,
|
2022-04-14 12:52:39 +02:00
|
|
|
VKD3D_SHADER_WARNING_HLSL_DIVISION_BY_ZERO = 5301,
|
2021-08-16 14:52:10 -05:00
|
|
|
VKD3D_SHADER_WARNING_HLSL_UNKNOWN_ATTRIBUTE = 5302,
|
2023-07-05 10:39:04 +02:00
|
|
|
VKD3D_SHADER_WARNING_HLSL_IMAGINARY_NUMERIC_RESULT = 5303,
|
2023-07-05 11:09:21 +02:00
|
|
|
VKD3D_SHADER_WARNING_HLSL_NON_FINITE_RESULT = 5304,
|
2023-08-10 10:03:49 +02:00
|
|
|
VKD3D_SHADER_WARNING_HLSL_IGNORED_ATTRIBUTE = 5305,
|
2024-06-25 18:36:32 -04:00
|
|
|
VKD3D_SHADER_WARNING_HLSL_IGNORED_DEFAULT_VALUE = 5306,
|
2025-05-13 18:17:26 -04:00
|
|
|
VKD3D_SHADER_WARNING_HLSL_IGNORED_MODIFIER = 5307,
|
2025-06-17 18:17:28 -04:00
|
|
|
VKD3D_SHADER_WARNING_HLSL_OVERRIDDEN_SEMANTIC = 5308,
|
2021-08-18 09:49:14 +05:30
|
|
|
|
|
|
|
|
VKD3D_SHADER_ERROR_GLSL_INTERNAL = 6000,
|
2024-02-25 00:35:48 +01:00
|
|
|
VKD3D_SHADER_ERROR_GLSL_BINDING_NOT_FOUND = 6001,
|
2024-05-06 14:00:58 +02:00
|
|
|
VKD3D_SHADER_ERROR_GLSL_UNSUPPORTED = 6002,
|
2021-10-06 17:11:48 +02:00
|
|
|
|
|
|
|
|
VKD3D_SHADER_ERROR_D3DBC_UNEXPECTED_EOF = 7000,
|
|
|
|
|
VKD3D_SHADER_ERROR_D3DBC_INVALID_VERSION_TOKEN = 7001,
|
|
|
|
|
VKD3D_SHADER_ERROR_D3DBC_INVALID_OPCODE = 7002,
|
|
|
|
|
VKD3D_SHADER_ERROR_D3DBC_INVALID_RESOURCE_TYPE = 7003,
|
2023-01-20 11:13:01 +10:00
|
|
|
VKD3D_SHADER_ERROR_D3DBC_OUT_OF_MEMORY = 7004,
|
2023-02-24 13:12:30 -06:00
|
|
|
VKD3D_SHADER_ERROR_D3DBC_INVALID_REGISTER_INDEX = 7005,
|
|
|
|
|
VKD3D_SHADER_ERROR_D3DBC_UNDECLARED_SEMANTIC = 7006,
|
2024-05-23 21:22:04 -04:00
|
|
|
VKD3D_SHADER_ERROR_D3DBC_INVALID_REGISTER_TYPE = 7007,
|
2024-05-27 19:58:05 -04:00
|
|
|
VKD3D_SHADER_ERROR_D3DBC_INVALID_REGISTER_COUNT = 7008,
|
|
|
|
|
VKD3D_SHADER_ERROR_D3DBC_NOT_IMPLEMENTED = 7009,
|
|
|
|
|
VKD3D_SHADER_ERROR_D3DBC_INVALID_PROFILE = 7010,
|
2024-05-31 02:20:36 -04:00
|
|
|
VKD3D_SHADER_ERROR_D3DBC_INVALID_WRITEMASK = 7011,
|
2021-10-06 17:11:48 +02:00
|
|
|
|
|
|
|
|
VKD3D_SHADER_WARNING_D3DBC_IGNORED_INSTRUCTION_FLAGS= 7300,
|
2022-11-15 15:16:41 +10:00
|
|
|
|
|
|
|
|
VKD3D_SHADER_ERROR_DXIL_OUT_OF_MEMORY = 8000,
|
|
|
|
|
VKD3D_SHADER_ERROR_DXIL_INVALID_SIZE = 8001,
|
|
|
|
|
VKD3D_SHADER_ERROR_DXIL_INVALID_CHUNK_OFFSET = 8002,
|
|
|
|
|
VKD3D_SHADER_ERROR_DXIL_INVALID_CHUNK_SIZE = 8003,
|
|
|
|
|
VKD3D_SHADER_ERROR_DXIL_INVALID_BITCODE = 8004,
|
2023-05-12 15:59:42 +10:00
|
|
|
VKD3D_SHADER_ERROR_DXIL_INVALID_OPERAND_COUNT = 8005,
|
|
|
|
|
VKD3D_SHADER_ERROR_DXIL_INVALID_TYPE_TABLE = 8006,
|
2023-07-10 13:46:45 +10:00
|
|
|
VKD3D_SHADER_ERROR_DXIL_INVALID_VALUE_SYMTAB = 8007,
|
2025-09-01 19:56:42 +02:00
|
|
|
VKD3D_SHADER_ERROR_DXIL_UNSUPPORTED = 8008,
|
2023-05-15 12:45:09 +10:00
|
|
|
VKD3D_SHADER_ERROR_DXIL_INVALID_FUNCTION_DCL = 8009,
|
|
|
|
|
VKD3D_SHADER_ERROR_DXIL_INVALID_TYPE_ID = 8010,
|
2023-05-15 13:52:00 +10:00
|
|
|
VKD3D_SHADER_ERROR_DXIL_INVALID_MODULE = 8011,
|
2023-07-31 16:23:08 +10:00
|
|
|
VKD3D_SHADER_ERROR_DXIL_INVALID_OPERAND = 8012,
|
2023-09-25 12:12:29 +10:00
|
|
|
VKD3D_SHADER_ERROR_DXIL_UNHANDLED_INTRINSIC = 8013,
|
2023-09-29 11:16:08 +10:00
|
|
|
VKD3D_SHADER_ERROR_DXIL_INVALID_METADATA = 8014,
|
2023-09-28 16:25:39 +10:00
|
|
|
VKD3D_SHADER_ERROR_DXIL_INVALID_ENTRY_POINT = 8015,
|
2023-09-28 16:33:11 +10:00
|
|
|
VKD3D_SHADER_ERROR_DXIL_INVALID_SIGNATURE = 8016,
|
2023-10-03 15:06:29 +10:00
|
|
|
VKD3D_SHADER_ERROR_DXIL_INVALID_PROPERTIES = 8017,
|
2023-10-15 13:38:11 +10:00
|
|
|
VKD3D_SHADER_ERROR_DXIL_INVALID_RESOURCES = 8018,
|
2023-10-05 15:38:09 +10:00
|
|
|
VKD3D_SHADER_ERROR_DXIL_INVALID_RESOURCE_HANDLE = 8019,
|
2025-05-13 11:30:41 +02:00
|
|
|
VKD3D_SHADER_ERROR_DXIL_INVALID_CONSTANT = 8020,
|
2025-10-01 16:36:51 -03:00
|
|
|
VKD3D_SHADER_ERROR_DXIL_NOT_IMPLEMENTED = 8021,
|
2022-11-15 15:16:41 +10:00
|
|
|
|
|
|
|
|
VKD3D_SHADER_WARNING_DXIL_UNKNOWN_MAGIC_NUMBER = 8300,
|
|
|
|
|
VKD3D_SHADER_WARNING_DXIL_UNKNOWN_SHADER_TYPE = 8301,
|
|
|
|
|
VKD3D_SHADER_WARNING_DXIL_INVALID_BLOCK_LENGTH = 8302,
|
|
|
|
|
VKD3D_SHADER_WARNING_DXIL_INVALID_MODULE_LENGTH = 8303,
|
2023-05-12 15:59:42 +10:00
|
|
|
VKD3D_SHADER_WARNING_DXIL_IGNORING_OPERANDS = 8304,
|
2023-09-29 11:45:44 +10:00
|
|
|
VKD3D_SHADER_WARNING_DXIL_TYPE_MISMATCH = 8305,
|
2023-09-28 16:25:39 +10:00
|
|
|
VKD3D_SHADER_WARNING_DXIL_ENTRY_POINT_MISMATCH = 8306,
|
2023-10-02 12:24:04 +10:00
|
|
|
VKD3D_SHADER_WARNING_DXIL_INVALID_MASK = 8307,
|
2023-10-16 15:41:17 +10:00
|
|
|
VKD3D_SHADER_WARNING_DXIL_INVALID_OPERATION = 8308,
|
2023-11-27 16:55:29 +10:00
|
|
|
VKD3D_SHADER_WARNING_DXIL_IGNORING_ATTACHMENT = 8309,
|
2023-06-15 14:47:37 +10:00
|
|
|
VKD3D_SHADER_WARNING_DXIL_UNDEFINED_OPERAND = 8310,
|
2023-07-20 21:52:25 -05:00
|
|
|
|
|
|
|
|
VKD3D_SHADER_ERROR_VSIR_NOT_IMPLEMENTED = 9000,
|
2025-05-29 20:54:35 +02:00
|
|
|
VKD3D_SHADER_ERROR_VSIR_INVALID_OPCODE = 9001,
|
2023-08-29 21:58:31 +02:00
|
|
|
VKD3D_SHADER_ERROR_VSIR_INVALID_REGISTER_TYPE = 9002,
|
2023-08-29 22:17:28 +02:00
|
|
|
VKD3D_SHADER_ERROR_VSIR_INVALID_WRITE_MASK = 9003,
|
|
|
|
|
VKD3D_SHADER_ERROR_VSIR_INVALID_MODIFIERS = 9004,
|
|
|
|
|
VKD3D_SHADER_ERROR_VSIR_INVALID_SHIFT = 9005,
|
2023-08-29 22:23:02 +02:00
|
|
|
VKD3D_SHADER_ERROR_VSIR_INVALID_SWIZZLE = 9006,
|
2023-10-24 19:37:40 -05:00
|
|
|
VKD3D_SHADER_ERROR_VSIR_INVALID_PRECISION = 9007,
|
2023-10-24 19:41:09 -05:00
|
|
|
VKD3D_SHADER_ERROR_VSIR_INVALID_DATA_TYPE = 9008,
|
2023-10-24 19:43:31 -05:00
|
|
|
VKD3D_SHADER_ERROR_VSIR_INVALID_DIMENSION = 9009,
|
2023-10-24 19:46:07 -05:00
|
|
|
VKD3D_SHADER_ERROR_VSIR_INVALID_INDEX_COUNT = 9010,
|
2023-10-24 20:08:00 -05:00
|
|
|
VKD3D_SHADER_ERROR_VSIR_INVALID_DEST_COUNT = 9011,
|
|
|
|
|
VKD3D_SHADER_ERROR_VSIR_INVALID_SOURCE_COUNT = 9012,
|
2023-10-24 19:55:37 -05:00
|
|
|
VKD3D_SHADER_ERROR_VSIR_DUPLICATE_DCL_TEMPS = 9013,
|
|
|
|
|
VKD3D_SHADER_ERROR_VSIR_INVALID_DCL_TEMPS = 9014,
|
|
|
|
|
VKD3D_SHADER_ERROR_VSIR_INVALID_INDEX = 9015,
|
2024-01-12 09:28:14 +01:00
|
|
|
VKD3D_SHADER_ERROR_VSIR_INVALID_CONTROL_FLOW = 9016,
|
2024-01-10 11:58:44 +01:00
|
|
|
VKD3D_SHADER_ERROR_VSIR_INVALID_SSA_USAGE = 9017,
|
2024-04-05 13:54:25 +10:00
|
|
|
VKD3D_SHADER_ERROR_VSIR_INVALID_TESSELLATION = 9018,
|
2024-04-19 12:45:09 +10:00
|
|
|
VKD3D_SHADER_ERROR_VSIR_INVALID_GS = 9019,
|
2024-07-16 19:48:48 -05:00
|
|
|
VKD3D_SHADER_ERROR_VSIR_INVALID_PARAMETER = 9020,
|
|
|
|
|
VKD3D_SHADER_ERROR_VSIR_MISSING_SEMANTIC = 9021,
|
2024-10-08 15:01:12 +02:00
|
|
|
VKD3D_SHADER_ERROR_VSIR_INVALID_SIGNATURE = 9022,
|
2024-11-11 10:57:42 +01:00
|
|
|
VKD3D_SHADER_ERROR_VSIR_INVALID_RANGE = 9023,
|
2025-03-28 10:39:43 +01:00
|
|
|
VKD3D_SHADER_ERROR_VSIR_INVALID_DESCRIPTOR_TYPE = 9024,
|
2025-03-28 10:42:44 +01:00
|
|
|
VKD3D_SHADER_ERROR_VSIR_INVALID_RESOURCE_TYPE = 9025,
|
2025-03-28 10:58:16 +01:00
|
|
|
VKD3D_SHADER_ERROR_VSIR_INVALID_DESCRIPTOR_COUNT = 9026,
|
2025-03-28 15:19:31 +01:00
|
|
|
VKD3D_SHADER_ERROR_VSIR_INVALID_FLAGS = 9027,
|
2023-11-20 14:58:40 +01:00
|
|
|
|
|
|
|
|
VKD3D_SHADER_WARNING_VSIR_DYNAMIC_DESCRIPTOR_ARRAY = 9300,
|
2024-08-27 10:34:57 +08:00
|
|
|
|
|
|
|
|
VKD3D_SHADER_ERROR_MSL_INTERNAL = 10000,
|
2024-10-09 16:36:06 +08:00
|
|
|
VKD3D_SHADER_ERROR_MSL_BINDING_NOT_FOUND = 10001,
|
2024-12-12 15:02:51 +08:00
|
|
|
VKD3D_SHADER_ERROR_MSL_UNSUPPORTED = 10002,
|
2024-10-04 23:36:28 +02:00
|
|
|
|
|
|
|
|
VKD3D_SHADER_ERROR_FX_NOT_IMPLEMENTED = 11000,
|
|
|
|
|
VKD3D_SHADER_ERROR_FX_INVALID_VERSION = 11001,
|
2024-10-17 11:36:34 +02:00
|
|
|
VKD3D_SHADER_ERROR_FX_INVALID_DATA = 11002,
|
2025-03-05 16:40:17 +01:00
|
|
|
VKD3D_SHADER_ERROR_FX_INVALID_SIZE = 11003,
|
2025-03-07 13:50:03 +01:00
|
|
|
VKD3D_SHADER_ERROR_FX_OUT_OF_MEMORY = 11004,
|
2020-07-23 13:41:25 +04:30
|
|
|
};
|
|
|
|
|
|
2021-02-16 14:58:23 +01:00
|
|
|
enum vkd3d_shader_opcode
|
2017-06-16 22:38:21 +02:00
|
|
|
{
|
2025-06-24 13:11:57 +02:00
|
|
|
VSIR_OP_ABS,
|
|
|
|
|
VSIR_OP_ACOS,
|
|
|
|
|
VSIR_OP_ADD,
|
|
|
|
|
VSIR_OP_AND,
|
|
|
|
|
VSIR_OP_ASIN,
|
|
|
|
|
VSIR_OP_ATAN,
|
|
|
|
|
VSIR_OP_ATOMIC_AND,
|
|
|
|
|
VSIR_OP_ATOMIC_CMP_STORE,
|
|
|
|
|
VSIR_OP_ATOMIC_IADD,
|
|
|
|
|
VSIR_OP_ATOMIC_IMAX,
|
|
|
|
|
VSIR_OP_ATOMIC_IMIN,
|
|
|
|
|
VSIR_OP_ATOMIC_OR,
|
|
|
|
|
VSIR_OP_ATOMIC_UMAX,
|
|
|
|
|
VSIR_OP_ATOMIC_UMIN,
|
|
|
|
|
VSIR_OP_ATOMIC_XOR,
|
|
|
|
|
VSIR_OP_BEM,
|
|
|
|
|
VSIR_OP_BFI,
|
|
|
|
|
VSIR_OP_BFREV,
|
|
|
|
|
VSIR_OP_BRANCH,
|
|
|
|
|
VSIR_OP_BREAK,
|
|
|
|
|
VSIR_OP_BREAKC,
|
|
|
|
|
VSIR_OP_BREAKP,
|
|
|
|
|
VSIR_OP_BUFINFO,
|
|
|
|
|
VSIR_OP_CALL,
|
|
|
|
|
VSIR_OP_CALLNZ,
|
|
|
|
|
VSIR_OP_CASE,
|
|
|
|
|
VSIR_OP_CHECK_ACCESS_FULLY_MAPPED,
|
|
|
|
|
VSIR_OP_CMP,
|
|
|
|
|
VSIR_OP_CND,
|
|
|
|
|
VSIR_OP_CONTINUE,
|
|
|
|
|
VSIR_OP_CONTINUEP,
|
|
|
|
|
VSIR_OP_COS,
|
|
|
|
|
VSIR_OP_COUNTBITS,
|
|
|
|
|
VSIR_OP_CRS,
|
|
|
|
|
VSIR_OP_CUT,
|
|
|
|
|
VSIR_OP_CUT_STREAM,
|
|
|
|
|
VSIR_OP_DADD,
|
|
|
|
|
VSIR_OP_DCL,
|
|
|
|
|
VSIR_OP_DCL_CONSTANT_BUFFER,
|
|
|
|
|
VSIR_OP_DCL_FUNCTION_BODY,
|
|
|
|
|
VSIR_OP_DCL_FUNCTION_TABLE,
|
|
|
|
|
VSIR_OP_DCL_GLOBAL_FLAGS,
|
|
|
|
|
VSIR_OP_DCL_GS_INSTANCES,
|
|
|
|
|
VSIR_OP_DCL_HS_FORK_PHASE_INSTANCE_COUNT,
|
|
|
|
|
VSIR_OP_DCL_HS_JOIN_PHASE_INSTANCE_COUNT,
|
|
|
|
|
VSIR_OP_DCL_HS_MAX_TESSFACTOR,
|
|
|
|
|
VSIR_OP_DCL_IMMEDIATE_CONSTANT_BUFFER,
|
|
|
|
|
VSIR_OP_DCL_INDEX_RANGE,
|
|
|
|
|
VSIR_OP_DCL_INDEXABLE_TEMP,
|
|
|
|
|
VSIR_OP_DCL_INPUT,
|
|
|
|
|
VSIR_OP_DCL_INPUT_CONTROL_POINT_COUNT,
|
|
|
|
|
VSIR_OP_DCL_INPUT_PRIMITIVE,
|
|
|
|
|
VSIR_OP_DCL_INPUT_PS,
|
|
|
|
|
VSIR_OP_DCL_INPUT_PS_SGV,
|
|
|
|
|
VSIR_OP_DCL_INPUT_PS_SIV,
|
|
|
|
|
VSIR_OP_DCL_INPUT_SGV,
|
|
|
|
|
VSIR_OP_DCL_INPUT_SIV,
|
|
|
|
|
VSIR_OP_DCL_INTERFACE,
|
|
|
|
|
VSIR_OP_DCL_OUTPUT,
|
|
|
|
|
VSIR_OP_DCL_OUTPUT_CONTROL_POINT_COUNT,
|
|
|
|
|
VSIR_OP_DCL_OUTPUT_SGV,
|
|
|
|
|
VSIR_OP_DCL_OUTPUT_SIV,
|
|
|
|
|
VSIR_OP_DCL_OUTPUT_TOPOLOGY,
|
|
|
|
|
VSIR_OP_DCL_RESOURCE_RAW,
|
|
|
|
|
VSIR_OP_DCL_RESOURCE_STRUCTURED,
|
|
|
|
|
VSIR_OP_DCL_SAMPLER,
|
|
|
|
|
VSIR_OP_DCL_STREAM,
|
|
|
|
|
VSIR_OP_DCL_TEMPS,
|
|
|
|
|
VSIR_OP_DCL_TESSELLATOR_DOMAIN,
|
|
|
|
|
VSIR_OP_DCL_TESSELLATOR_OUTPUT_PRIMITIVE,
|
|
|
|
|
VSIR_OP_DCL_TESSELLATOR_PARTITIONING,
|
|
|
|
|
VSIR_OP_DCL_TGSM_RAW,
|
|
|
|
|
VSIR_OP_DCL_TGSM_STRUCTURED,
|
|
|
|
|
VSIR_OP_DCL_THREAD_GROUP,
|
|
|
|
|
VSIR_OP_DCL_UAV_RAW,
|
|
|
|
|
VSIR_OP_DCL_UAV_STRUCTURED,
|
|
|
|
|
VSIR_OP_DCL_UAV_TYPED,
|
|
|
|
|
VSIR_OP_DCL_VERTICES_OUT,
|
|
|
|
|
VSIR_OP_DDIV,
|
|
|
|
|
VSIR_OP_DEF,
|
|
|
|
|
VSIR_OP_DEFAULT,
|
|
|
|
|
VSIR_OP_DEFB,
|
|
|
|
|
VSIR_OP_DEFI,
|
|
|
|
|
VSIR_OP_DEQO,
|
|
|
|
|
VSIR_OP_DFMA,
|
|
|
|
|
VSIR_OP_DGEO,
|
|
|
|
|
VSIR_OP_DISCARD,
|
|
|
|
|
VSIR_OP_DIV,
|
|
|
|
|
VSIR_OP_DLT,
|
|
|
|
|
VSIR_OP_DMAX,
|
|
|
|
|
VSIR_OP_DMIN,
|
|
|
|
|
VSIR_OP_DMOV,
|
|
|
|
|
VSIR_OP_DMOVC,
|
|
|
|
|
VSIR_OP_DMUL,
|
|
|
|
|
VSIR_OP_DNE,
|
|
|
|
|
VSIR_OP_DP2,
|
|
|
|
|
VSIR_OP_DP2ADD,
|
|
|
|
|
VSIR_OP_DP3,
|
|
|
|
|
VSIR_OP_DP4,
|
|
|
|
|
VSIR_OP_DRCP,
|
|
|
|
|
VSIR_OP_DST,
|
|
|
|
|
VSIR_OP_DSX,
|
|
|
|
|
VSIR_OP_DSX_COARSE,
|
|
|
|
|
VSIR_OP_DSX_FINE,
|
|
|
|
|
VSIR_OP_DSY,
|
|
|
|
|
VSIR_OP_DSY_COARSE,
|
|
|
|
|
VSIR_OP_DSY_FINE,
|
|
|
|
|
VSIR_OP_DTOF,
|
|
|
|
|
VSIR_OP_DTOI,
|
|
|
|
|
VSIR_OP_DTOU,
|
|
|
|
|
VSIR_OP_ELSE,
|
|
|
|
|
VSIR_OP_EMIT,
|
|
|
|
|
VSIR_OP_EMIT_STREAM,
|
|
|
|
|
VSIR_OP_ENDIF,
|
|
|
|
|
VSIR_OP_ENDLOOP,
|
|
|
|
|
VSIR_OP_ENDREP,
|
|
|
|
|
VSIR_OP_ENDSWITCH,
|
|
|
|
|
VSIR_OP_EQO,
|
|
|
|
|
VSIR_OP_EQU,
|
|
|
|
|
VSIR_OP_EVAL_CENTROID,
|
|
|
|
|
VSIR_OP_EVAL_SAMPLE_INDEX,
|
|
|
|
|
VSIR_OP_EXP,
|
|
|
|
|
VSIR_OP_EXPP,
|
|
|
|
|
VSIR_OP_F16TOF32,
|
|
|
|
|
VSIR_OP_F32TOF16,
|
|
|
|
|
VSIR_OP_FCALL,
|
|
|
|
|
VSIR_OP_FIRSTBIT_HI,
|
|
|
|
|
VSIR_OP_FIRSTBIT_LO,
|
|
|
|
|
VSIR_OP_FIRSTBIT_SHI,
|
|
|
|
|
VSIR_OP_FRC,
|
|
|
|
|
VSIR_OP_FREM,
|
|
|
|
|
VSIR_OP_FTOD,
|
|
|
|
|
VSIR_OP_FTOI,
|
|
|
|
|
VSIR_OP_FTOU,
|
|
|
|
|
VSIR_OP_GATHER4,
|
|
|
|
|
VSIR_OP_GATHER4_C,
|
|
|
|
|
VSIR_OP_GATHER4_C_S,
|
|
|
|
|
VSIR_OP_GATHER4_PO,
|
|
|
|
|
VSIR_OP_GATHER4_PO_C,
|
|
|
|
|
VSIR_OP_GATHER4_PO_C_S,
|
|
|
|
|
VSIR_OP_GATHER4_PO_S,
|
|
|
|
|
VSIR_OP_GATHER4_S,
|
|
|
|
|
VSIR_OP_GEO,
|
|
|
|
|
VSIR_OP_GEU,
|
|
|
|
|
VSIR_OP_HCOS,
|
|
|
|
|
VSIR_OP_HS_CONTROL_POINT_PHASE,
|
|
|
|
|
VSIR_OP_HS_DECLS,
|
|
|
|
|
VSIR_OP_HS_FORK_PHASE,
|
|
|
|
|
VSIR_OP_HS_JOIN_PHASE,
|
|
|
|
|
VSIR_OP_HSIN,
|
|
|
|
|
VSIR_OP_HTAN,
|
|
|
|
|
VSIR_OP_IADD,
|
|
|
|
|
VSIR_OP_IBFE,
|
|
|
|
|
VSIR_OP_IDIV,
|
|
|
|
|
VSIR_OP_IEQ,
|
|
|
|
|
VSIR_OP_IF,
|
|
|
|
|
VSIR_OP_IFC,
|
|
|
|
|
VSIR_OP_IGE,
|
|
|
|
|
VSIR_OP_ILT,
|
|
|
|
|
VSIR_OP_IMAD,
|
|
|
|
|
VSIR_OP_IMAX,
|
|
|
|
|
VSIR_OP_IMIN,
|
|
|
|
|
VSIR_OP_IMM_ATOMIC_ALLOC,
|
|
|
|
|
VSIR_OP_IMM_ATOMIC_AND,
|
|
|
|
|
VSIR_OP_IMM_ATOMIC_CMP_EXCH,
|
|
|
|
|
VSIR_OP_IMM_ATOMIC_CONSUME,
|
|
|
|
|
VSIR_OP_IMM_ATOMIC_EXCH,
|
|
|
|
|
VSIR_OP_IMM_ATOMIC_IADD,
|
|
|
|
|
VSIR_OP_IMM_ATOMIC_IMAX,
|
|
|
|
|
VSIR_OP_IMM_ATOMIC_IMIN,
|
|
|
|
|
VSIR_OP_IMM_ATOMIC_OR,
|
|
|
|
|
VSIR_OP_IMM_ATOMIC_UMAX,
|
|
|
|
|
VSIR_OP_IMM_ATOMIC_UMIN,
|
|
|
|
|
VSIR_OP_IMM_ATOMIC_XOR,
|
|
|
|
|
VSIR_OP_IMUL,
|
|
|
|
|
VSIR_OP_IMUL_LOW,
|
|
|
|
|
VSIR_OP_INE,
|
|
|
|
|
VSIR_OP_INEG,
|
2025-06-10 19:20:12 +02:00
|
|
|
VSIR_OP_IREM,
|
2025-06-24 13:11:57 +02:00
|
|
|
VSIR_OP_ISFINITE,
|
|
|
|
|
VSIR_OP_ISHL,
|
|
|
|
|
VSIR_OP_ISHR,
|
|
|
|
|
VSIR_OP_ISINF,
|
|
|
|
|
VSIR_OP_ISNAN,
|
|
|
|
|
VSIR_OP_ITOD,
|
|
|
|
|
VSIR_OP_ITOF,
|
|
|
|
|
VSIR_OP_ITOI,
|
|
|
|
|
VSIR_OP_LABEL,
|
|
|
|
|
VSIR_OP_LD,
|
|
|
|
|
VSIR_OP_LD2DMS,
|
|
|
|
|
VSIR_OP_LD2DMS_S,
|
|
|
|
|
VSIR_OP_LD_RAW,
|
|
|
|
|
VSIR_OP_LD_RAW_S,
|
|
|
|
|
VSIR_OP_LD_S,
|
|
|
|
|
VSIR_OP_LD_STRUCTURED,
|
|
|
|
|
VSIR_OP_LD_STRUCTURED_S,
|
|
|
|
|
VSIR_OP_LD_UAV_TYPED,
|
|
|
|
|
VSIR_OP_LD_UAV_TYPED_S,
|
|
|
|
|
VSIR_OP_LIT,
|
|
|
|
|
VSIR_OP_LOD,
|
|
|
|
|
VSIR_OP_LOG,
|
|
|
|
|
VSIR_OP_LOGP,
|
|
|
|
|
VSIR_OP_LOOP,
|
|
|
|
|
VSIR_OP_LRP,
|
|
|
|
|
VSIR_OP_LTO,
|
|
|
|
|
VSIR_OP_LTU,
|
|
|
|
|
VSIR_OP_M3x2,
|
|
|
|
|
VSIR_OP_M3x3,
|
|
|
|
|
VSIR_OP_M3x4,
|
|
|
|
|
VSIR_OP_M4x3,
|
|
|
|
|
VSIR_OP_M4x4,
|
|
|
|
|
VSIR_OP_MAD,
|
|
|
|
|
VSIR_OP_MAX,
|
|
|
|
|
VSIR_OP_MIN,
|
|
|
|
|
VSIR_OP_MOV,
|
|
|
|
|
VSIR_OP_MOVA,
|
|
|
|
|
VSIR_OP_MOVC,
|
|
|
|
|
VSIR_OP_MSAD,
|
|
|
|
|
VSIR_OP_MUL,
|
|
|
|
|
VSIR_OP_NEO,
|
|
|
|
|
VSIR_OP_NEU,
|
|
|
|
|
VSIR_OP_NOP,
|
|
|
|
|
VSIR_OP_NOT,
|
|
|
|
|
VSIR_OP_NRM,
|
|
|
|
|
VSIR_OP_OR,
|
|
|
|
|
VSIR_OP_ORD,
|
|
|
|
|
VSIR_OP_PHASE,
|
|
|
|
|
VSIR_OP_PHI,
|
|
|
|
|
VSIR_OP_POW,
|
|
|
|
|
VSIR_OP_QUAD_READ_ACROSS_D,
|
|
|
|
|
VSIR_OP_QUAD_READ_ACROSS_X,
|
|
|
|
|
VSIR_OP_QUAD_READ_ACROSS_Y,
|
|
|
|
|
VSIR_OP_QUAD_READ_LANE_AT,
|
|
|
|
|
VSIR_OP_RCP,
|
|
|
|
|
VSIR_OP_REP,
|
|
|
|
|
VSIR_OP_RESINFO,
|
|
|
|
|
VSIR_OP_RET,
|
|
|
|
|
VSIR_OP_RETP,
|
|
|
|
|
VSIR_OP_ROUND_NE,
|
|
|
|
|
VSIR_OP_ROUND_NI,
|
|
|
|
|
VSIR_OP_ROUND_PI,
|
|
|
|
|
VSIR_OP_ROUND_Z,
|
|
|
|
|
VSIR_OP_RSQ,
|
|
|
|
|
VSIR_OP_SAMPLE,
|
|
|
|
|
VSIR_OP_SAMPLE_B,
|
|
|
|
|
VSIR_OP_SAMPLE_B_CL_S,
|
|
|
|
|
VSIR_OP_SAMPLE_C,
|
|
|
|
|
VSIR_OP_SAMPLE_C_CL_S,
|
|
|
|
|
VSIR_OP_SAMPLE_C_LZ,
|
|
|
|
|
VSIR_OP_SAMPLE_C_LZ_S,
|
|
|
|
|
VSIR_OP_SAMPLE_CL_S,
|
|
|
|
|
VSIR_OP_SAMPLE_GRAD,
|
|
|
|
|
VSIR_OP_SAMPLE_GRAD_CL_S,
|
|
|
|
|
VSIR_OP_SAMPLE_INFO,
|
|
|
|
|
VSIR_OP_SAMPLE_LOD,
|
|
|
|
|
VSIR_OP_SAMPLE_LOD_S,
|
|
|
|
|
VSIR_OP_SAMPLE_POS,
|
|
|
|
|
VSIR_OP_SETP,
|
|
|
|
|
VSIR_OP_SGE,
|
|
|
|
|
VSIR_OP_SGN,
|
|
|
|
|
VSIR_OP_SIN,
|
|
|
|
|
VSIR_OP_SINCOS,
|
|
|
|
|
VSIR_OP_SLT,
|
|
|
|
|
VSIR_OP_SQRT,
|
|
|
|
|
VSIR_OP_STORE_RAW,
|
|
|
|
|
VSIR_OP_STORE_STRUCTURED,
|
|
|
|
|
VSIR_OP_STORE_UAV_TYPED,
|
|
|
|
|
VSIR_OP_SUB,
|
|
|
|
|
VSIR_OP_SWAPC,
|
|
|
|
|
VSIR_OP_SWITCH,
|
|
|
|
|
VSIR_OP_SWITCH_MONOLITHIC,
|
|
|
|
|
VSIR_OP_SYNC,
|
|
|
|
|
VSIR_OP_TAN,
|
|
|
|
|
VSIR_OP_TEX,
|
|
|
|
|
VSIR_OP_TEXBEM,
|
|
|
|
|
VSIR_OP_TEXBEML,
|
|
|
|
|
VSIR_OP_TEXCOORD,
|
|
|
|
|
VSIR_OP_TEXCRD,
|
|
|
|
|
VSIR_OP_TEXDEPTH,
|
|
|
|
|
VSIR_OP_TEXDP3,
|
|
|
|
|
VSIR_OP_TEXDP3TEX,
|
|
|
|
|
VSIR_OP_TEXKILL,
|
|
|
|
|
VSIR_OP_TEXLD,
|
|
|
|
|
VSIR_OP_TEXLDD,
|
|
|
|
|
VSIR_OP_TEXLDL,
|
|
|
|
|
VSIR_OP_TEXM3x2DEPTH,
|
|
|
|
|
VSIR_OP_TEXM3x2PAD,
|
|
|
|
|
VSIR_OP_TEXM3x2TEX,
|
|
|
|
|
VSIR_OP_TEXM3x3,
|
|
|
|
|
VSIR_OP_TEXM3x3DIFF,
|
|
|
|
|
VSIR_OP_TEXM3x3PAD,
|
|
|
|
|
VSIR_OP_TEXM3x3SPEC,
|
|
|
|
|
VSIR_OP_TEXM3x3TEX,
|
|
|
|
|
VSIR_OP_TEXM3x3VSPEC,
|
|
|
|
|
VSIR_OP_TEXREG2AR,
|
|
|
|
|
VSIR_OP_TEXREG2GB,
|
|
|
|
|
VSIR_OP_TEXREG2RGB,
|
|
|
|
|
VSIR_OP_UBFE,
|
|
|
|
|
VSIR_OP_UDIV,
|
2025-06-20 18:39:07 +02:00
|
|
|
VSIR_OP_UDIV_SIMPLE,
|
2025-06-24 13:11:57 +02:00
|
|
|
VSIR_OP_UGE,
|
|
|
|
|
VSIR_OP_ULT,
|
|
|
|
|
VSIR_OP_UMAX,
|
|
|
|
|
VSIR_OP_UMIN,
|
|
|
|
|
VSIR_OP_UMUL,
|
|
|
|
|
VSIR_OP_UNO,
|
2025-06-20 18:44:45 +02:00
|
|
|
VSIR_OP_UREM,
|
2025-06-24 13:11:57 +02:00
|
|
|
VSIR_OP_USHR,
|
|
|
|
|
VSIR_OP_UTOD,
|
|
|
|
|
VSIR_OP_UTOF,
|
|
|
|
|
VSIR_OP_UTOU,
|
|
|
|
|
VSIR_OP_WAVE_ACTIVE_ALL_EQUAL,
|
|
|
|
|
VSIR_OP_WAVE_ACTIVE_BALLOT,
|
|
|
|
|
VSIR_OP_WAVE_ACTIVE_BIT_AND,
|
|
|
|
|
VSIR_OP_WAVE_ACTIVE_BIT_OR,
|
|
|
|
|
VSIR_OP_WAVE_ACTIVE_BIT_XOR,
|
|
|
|
|
VSIR_OP_WAVE_ALL_BIT_COUNT,
|
|
|
|
|
VSIR_OP_WAVE_ALL_TRUE,
|
|
|
|
|
VSIR_OP_WAVE_ANY_TRUE,
|
|
|
|
|
VSIR_OP_WAVE_IS_FIRST_LANE,
|
|
|
|
|
VSIR_OP_WAVE_OP_ADD,
|
|
|
|
|
VSIR_OP_WAVE_OP_IMAX,
|
|
|
|
|
VSIR_OP_WAVE_OP_IMIN,
|
|
|
|
|
VSIR_OP_WAVE_OP_MAX,
|
|
|
|
|
VSIR_OP_WAVE_OP_MIN,
|
|
|
|
|
VSIR_OP_WAVE_OP_MUL,
|
|
|
|
|
VSIR_OP_WAVE_OP_UMAX,
|
|
|
|
|
VSIR_OP_WAVE_OP_UMIN,
|
|
|
|
|
VSIR_OP_WAVE_PREFIX_BIT_COUNT,
|
|
|
|
|
VSIR_OP_WAVE_READ_LANE_AT,
|
|
|
|
|
VSIR_OP_WAVE_READ_LANE_FIRST,
|
|
|
|
|
VSIR_OP_XOR,
|
2019-02-20 13:42:48 +01:00
|
|
|
|
2025-06-24 13:11:57 +02:00
|
|
|
VSIR_OP_INVALID,
|
2024-10-25 15:38:50 -03:00
|
|
|
|
2025-06-24 13:11:57 +02:00
|
|
|
VSIR_OP_COUNT,
|
2017-06-16 22:38:21 +02:00
|
|
|
};
|
|
|
|
|
|
2025-06-03 13:46:04 +02:00
|
|
|
const char *vsir_opcode_get_name(enum vkd3d_shader_opcode op, const char *error);
|
|
|
|
|
|
2017-06-16 22:38:21 +02:00
|
|
|
enum vkd3d_shader_register_type
|
|
|
|
|
{
|
2024-07-20 12:26:56 -05:00
|
|
|
VKD3DSPR_TEMP,
|
|
|
|
|
VKD3DSPR_INPUT,
|
|
|
|
|
VKD3DSPR_CONST,
|
|
|
|
|
VKD3DSPR_ADDR,
|
2024-07-20 12:26:56 -05:00
|
|
|
VKD3DSPR_TEXTURE,
|
2024-07-20 12:26:56 -05:00
|
|
|
VKD3DSPR_RASTOUT,
|
|
|
|
|
VKD3DSPR_ATTROUT,
|
|
|
|
|
VKD3DSPR_TEXCRDOUT,
|
2024-07-20 12:26:56 -05:00
|
|
|
VKD3DSPR_OUTPUT,
|
2024-07-20 12:26:56 -05:00
|
|
|
VKD3DSPR_CONSTINT,
|
|
|
|
|
VKD3DSPR_COLOROUT,
|
|
|
|
|
VKD3DSPR_DEPTHOUT,
|
|
|
|
|
VKD3DSPR_COMBINED_SAMPLER,
|
|
|
|
|
VKD3DSPR_CONSTBOOL,
|
|
|
|
|
VKD3DSPR_LOOP,
|
|
|
|
|
VKD3DSPR_TEMPFLOAT16,
|
|
|
|
|
VKD3DSPR_MISCTYPE,
|
|
|
|
|
VKD3DSPR_LABEL,
|
|
|
|
|
VKD3DSPR_PREDICATE,
|
2017-06-16 22:38:21 +02:00
|
|
|
VKD3DSPR_IMMCONST,
|
2021-07-30 23:27:20 +10:00
|
|
|
VKD3DSPR_IMMCONST64,
|
2017-06-16 22:38:21 +02:00
|
|
|
VKD3DSPR_CONSTBUFFER,
|
|
|
|
|
VKD3DSPR_IMMCONSTBUFFER,
|
|
|
|
|
VKD3DSPR_PRIMID,
|
|
|
|
|
VKD3DSPR_NULL,
|
2023-03-07 16:45:18 -06:00
|
|
|
VKD3DSPR_SAMPLER,
|
2017-06-16 22:38:21 +02:00
|
|
|
VKD3DSPR_RESOURCE,
|
|
|
|
|
VKD3DSPR_UAV,
|
|
|
|
|
VKD3DSPR_OUTPOINTID,
|
|
|
|
|
VKD3DSPR_FORKINSTID,
|
|
|
|
|
VKD3DSPR_JOININSTID,
|
|
|
|
|
VKD3DSPR_INCONTROLPOINT,
|
|
|
|
|
VKD3DSPR_OUTCONTROLPOINT,
|
|
|
|
|
VKD3DSPR_PATCHCONST,
|
|
|
|
|
VKD3DSPR_TESSCOORD,
|
|
|
|
|
VKD3DSPR_GROUPSHAREDMEM,
|
|
|
|
|
VKD3DSPR_THREADID,
|
|
|
|
|
VKD3DSPR_THREADGROUPID,
|
|
|
|
|
VKD3DSPR_LOCALTHREADID,
|
|
|
|
|
VKD3DSPR_LOCALTHREADINDEX,
|
|
|
|
|
VKD3DSPR_IDXTEMP,
|
|
|
|
|
VKD3DSPR_STREAM,
|
|
|
|
|
VKD3DSPR_FUNCTIONBODY,
|
|
|
|
|
VKD3DSPR_FUNCTIONPOINTER,
|
|
|
|
|
VKD3DSPR_COVERAGE,
|
|
|
|
|
VKD3DSPR_SAMPLEMASK,
|
|
|
|
|
VKD3DSPR_GSINSTID,
|
2018-05-29 12:50:31 +02:00
|
|
|
VKD3DSPR_DEPTHOUTGE,
|
|
|
|
|
VKD3DSPR_DEPTHOUTLE,
|
|
|
|
|
VKD3DSPR_RASTERIZER,
|
2021-10-18 18:28:12 +02:00
|
|
|
VKD3DSPR_OUTSTENCILREF,
|
2023-05-22 23:40:39 +10:00
|
|
|
VKD3DSPR_UNDEF,
|
2023-05-18 15:51:53 +10:00
|
|
|
VKD3DSPR_SSA,
|
2024-04-18 10:35:07 +10:00
|
|
|
VKD3DSPR_WAVELANECOUNT,
|
|
|
|
|
VKD3DSPR_WAVELANEINDEX,
|
2024-06-10 19:25:18 -05:00
|
|
|
VKD3DSPR_PARAMETER,
|
2024-10-15 19:04:19 -05:00
|
|
|
VKD3DSPR_POINT_COORD,
|
2018-04-13 12:37:37 +02:00
|
|
|
|
2023-07-19 12:19:02 -04:00
|
|
|
VKD3DSPR_COUNT,
|
|
|
|
|
|
2018-04-13 12:37:37 +02:00
|
|
|
VKD3DSPR_INVALID = ~0u,
|
2017-06-16 22:38:21 +02:00
|
|
|
};
|
|
|
|
|
|
2024-10-03 13:10:10 -05:00
|
|
|
enum vsir_rastout_register
|
|
|
|
|
{
|
|
|
|
|
VSIR_RASTOUT_POSITION = 0x0,
|
|
|
|
|
VSIR_RASTOUT_FOG = 0x1,
|
|
|
|
|
VSIR_RASTOUT_POINT_SIZE = 0x2,
|
|
|
|
|
};
|
|
|
|
|
|
2021-09-28 16:07:22 +02:00
|
|
|
enum vkd3d_shader_register_precision
|
|
|
|
|
{
|
|
|
|
|
VKD3D_SHADER_REGISTER_PRECISION_DEFAULT,
|
|
|
|
|
VKD3D_SHADER_REGISTER_PRECISION_MIN_FLOAT_16,
|
|
|
|
|
VKD3D_SHADER_REGISTER_PRECISION_MIN_FLOAT_10,
|
|
|
|
|
VKD3D_SHADER_REGISTER_PRECISION_MIN_INT_16,
|
|
|
|
|
VKD3D_SHADER_REGISTER_PRECISION_MIN_UINT_16,
|
|
|
|
|
|
2023-10-24 19:37:40 -05:00
|
|
|
VKD3D_SHADER_REGISTER_PRECISION_COUNT,
|
|
|
|
|
|
2021-09-28 16:07:22 +02:00
|
|
|
VKD3D_SHADER_REGISTER_PRECISION_INVALID = ~0u,
|
|
|
|
|
};
|
|
|
|
|
|
2025-07-17 15:22:54 +02:00
|
|
|
enum vsir_data_type
|
2017-06-16 22:38:21 +02:00
|
|
|
{
|
2025-07-21 15:39:16 +02:00
|
|
|
VSIR_DATA_BOOL,
|
2025-07-17 15:37:58 +02:00
|
|
|
|
|
|
|
|
VSIR_DATA_F16,
|
2025-07-17 15:55:17 +02:00
|
|
|
VSIR_DATA_F32,
|
2025-07-17 16:03:55 +02:00
|
|
|
VSIR_DATA_F64,
|
2023-10-24 19:41:09 -05:00
|
|
|
|
vkd3d-shader/dxil: Allow returning signed types from vsir_data_type_from_dxil().
We have a number of vsir operations which should take a signed type, but
which the DXIL parser currently emits unsigned types for. For example,
ISHR.
In the SPIR-V backend, we translate ISHR to OpShiftRightArithmetic,
which is specified as filling the most-significant bits of the result
with the sign bit of the "Base" operand. For an unsigned type, that
would technically be 0. In practice, implementations like radv/Mesa seem
to fill with the most-significant bit of the "Base" operand for unsigned
types, but arguably that could be considered a bug. Alternatively, the
wording in the specification is just unfortunate; SPIR-V does generally
take the position that signedness of operands should be irrelevant for
almost all operations. Either way, it seems best to avoid using
OpShiftRightArithmetic with unsigned types.
For a target like MSL, allowing ISHR to take an unsigned source operand
is just inconvenient; we'd have to introduce bitcasts to achieve the
desired behaviour, instead of simply using msl_binop().
2025-09-01 20:14:32 +02:00
|
|
|
VSIR_DATA_I8,
|
2025-08-31 19:50:16 +02:00
|
|
|
VSIR_DATA_I16,
|
2025-07-17 16:29:38 +02:00
|
|
|
VSIR_DATA_I32,
|
2025-08-31 19:50:16 +02:00
|
|
|
VSIR_DATA_I64,
|
2025-07-17 16:29:38 +02:00
|
|
|
|
2025-07-17 16:34:07 +02:00
|
|
|
VSIR_DATA_U8,
|
2025-07-17 16:37:23 +02:00
|
|
|
VSIR_DATA_U16,
|
2025-07-17 16:47:43 +02:00
|
|
|
VSIR_DATA_U32,
|
2025-07-17 16:51:18 +02:00
|
|
|
VSIR_DATA_U64,
|
2025-07-17 16:34:07 +02:00
|
|
|
|
2025-07-21 15:09:30 +02:00
|
|
|
VSIR_DATA_SNORM,
|
2025-07-21 15:05:46 +02:00
|
|
|
VSIR_DATA_UNORM,
|
|
|
|
|
|
2025-07-21 15:12:49 +02:00
|
|
|
VSIR_DATA_OPAQUE,
|
2025-07-21 15:15:35 +02:00
|
|
|
VSIR_DATA_MIXED,
|
2025-07-21 15:17:51 +02:00
|
|
|
VSIR_DATA_CONTINUED,
|
2025-07-21 15:31:59 +02:00
|
|
|
VSIR_DATA_UNUSED,
|
2025-07-21 15:12:49 +02:00
|
|
|
|
2025-07-17 15:22:54 +02:00
|
|
|
VSIR_DATA_TYPE_COUNT,
|
2017-06-16 22:38:21 +02:00
|
|
|
};
|
|
|
|
|
|
2025-08-25 16:53:24 +02:00
|
|
|
const char *vsir_data_type_get_name(enum vsir_data_type t, const char *error);
|
|
|
|
|
|
2025-07-17 15:22:54 +02:00
|
|
|
static inline bool data_type_is_integer(enum vsir_data_type data_type)
|
2023-05-17 00:09:19 +10:00
|
|
|
{
|
vkd3d-shader/dxil: Allow returning signed types from vsir_data_type_from_dxil().
We have a number of vsir operations which should take a signed type, but
which the DXIL parser currently emits unsigned types for. For example,
ISHR.
In the SPIR-V backend, we translate ISHR to OpShiftRightArithmetic,
which is specified as filling the most-significant bits of the result
with the sign bit of the "Base" operand. For an unsigned type, that
would technically be 0. In practice, implementations like radv/Mesa seem
to fill with the most-significant bit of the "Base" operand for unsigned
types, but arguably that could be considered a bug. Alternatively, the
wording in the specification is just unfortunate; SPIR-V does generally
take the position that signedness of operands should be irrelevant for
almost all operations. Either way, it seems best to avoid using
OpShiftRightArithmetic with unsigned types.
For a target like MSL, allowing ISHR to take an unsigned source operand
is just inconvenient; we'd have to introduce bitcasts to achieve the
desired behaviour, instead of simply using msl_binop().
2025-09-01 20:14:32 +02:00
|
|
|
return data_type == VSIR_DATA_I8
|
|
|
|
|
|| data_type == VSIR_DATA_I16
|
|
|
|
|
|| data_type == VSIR_DATA_I32
|
|
|
|
|
|| data_type == VSIR_DATA_I64
|
|
|
|
|
|| data_type == VSIR_DATA_U8
|
|
|
|
|
|| data_type == VSIR_DATA_U16
|
|
|
|
|
|| data_type == VSIR_DATA_U32
|
2025-08-31 19:50:16 +02:00
|
|
|
|| data_type == VSIR_DATA_U64;
|
2023-05-17 00:09:19 +10:00
|
|
|
}
|
|
|
|
|
|
2025-07-17 15:22:54 +02:00
|
|
|
static inline bool data_type_is_bool(enum vsir_data_type data_type)
|
2023-10-05 15:38:09 +10:00
|
|
|
{
|
2025-07-21 15:39:16 +02:00
|
|
|
return data_type == VSIR_DATA_BOOL;
|
2023-10-05 15:38:09 +10:00
|
|
|
}
|
|
|
|
|
|
2025-07-17 15:22:54 +02:00
|
|
|
static inline bool data_type_is_floating_point(enum vsir_data_type data_type)
|
2023-12-06 16:49:17 +10:00
|
|
|
{
|
2025-07-17 16:03:55 +02:00
|
|
|
return data_type == VSIR_DATA_F16 || data_type == VSIR_DATA_F32 || data_type == VSIR_DATA_F64;
|
2023-12-06 16:49:17 +10:00
|
|
|
}
|
|
|
|
|
|
2025-07-17 15:22:54 +02:00
|
|
|
static inline bool data_type_is_64_bit(enum vsir_data_type data_type)
|
2023-11-21 16:32:35 +10:00
|
|
|
{
|
2025-08-31 19:50:16 +02:00
|
|
|
return data_type == VSIR_DATA_F64 || data_type == VSIR_DATA_I64 || data_type == VSIR_DATA_U64;
|
2023-11-21 16:32:35 +10:00
|
|
|
}
|
|
|
|
|
|
2023-08-14 13:21:41 -04:00
|
|
|
enum vsir_dimension
|
2017-06-16 22:38:21 +02:00
|
|
|
{
|
2023-08-14 13:21:41 -04:00
|
|
|
VSIR_DIMENSION_NONE,
|
|
|
|
|
VSIR_DIMENSION_SCALAR,
|
|
|
|
|
VSIR_DIMENSION_VEC4,
|
2023-10-24 19:43:31 -05:00
|
|
|
|
|
|
|
|
VSIR_DIMENSION_COUNT,
|
2017-06-16 22:38:21 +02:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
enum vkd3d_shader_src_modifier
|
|
|
|
|
{
|
|
|
|
|
VKD3DSPSM_NONE = 0,
|
|
|
|
|
VKD3DSPSM_NEG = 1,
|
|
|
|
|
VKD3DSPSM_BIAS = 2,
|
|
|
|
|
VKD3DSPSM_BIASNEG = 3,
|
|
|
|
|
VKD3DSPSM_SIGN = 4,
|
|
|
|
|
VKD3DSPSM_SIGNNEG = 5,
|
|
|
|
|
VKD3DSPSM_COMP = 6,
|
|
|
|
|
VKD3DSPSM_X2 = 7,
|
|
|
|
|
VKD3DSPSM_X2NEG = 8,
|
|
|
|
|
VKD3DSPSM_DZ = 9,
|
|
|
|
|
VKD3DSPSM_DW = 10,
|
|
|
|
|
VKD3DSPSM_ABS = 11,
|
|
|
|
|
VKD3DSPSM_ABSNEG = 12,
|
|
|
|
|
VKD3DSPSM_NOT = 13,
|
2023-08-29 22:23:02 +02:00
|
|
|
VKD3DSPSM_COUNT,
|
2017-06-16 22:38:21 +02:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
#define VKD3DSP_WRITEMASK_0 0x1u /* .x r */
|
|
|
|
|
#define VKD3DSP_WRITEMASK_1 0x2u /* .y g */
|
|
|
|
|
#define VKD3DSP_WRITEMASK_2 0x4u /* .z b */
|
|
|
|
|
#define VKD3DSP_WRITEMASK_3 0x8u /* .w a */
|
|
|
|
|
#define VKD3DSP_WRITEMASK_ALL 0xfu /* all */
|
|
|
|
|
|
|
|
|
|
enum vkd3d_shader_dst_modifier
|
|
|
|
|
{
|
|
|
|
|
VKD3DSPDM_NONE = 0,
|
|
|
|
|
VKD3DSPDM_SATURATE = 1,
|
|
|
|
|
VKD3DSPDM_PARTIALPRECISION = 2,
|
|
|
|
|
VKD3DSPDM_MSAMPCENTROID = 4,
|
2023-08-29 22:17:28 +02:00
|
|
|
VKD3DSPDM_MASK = 7,
|
2017-06-16 22:38:21 +02:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
enum vkd3d_shader_interpolation_mode
|
|
|
|
|
{
|
2019-05-14 13:27:41 +02:00
|
|
|
VKD3DSIM_NONE = 0,
|
2017-06-16 22:38:21 +02:00
|
|
|
VKD3DSIM_CONSTANT = 1,
|
|
|
|
|
VKD3DSIM_LINEAR = 2,
|
|
|
|
|
VKD3DSIM_LINEAR_CENTROID = 3,
|
|
|
|
|
VKD3DSIM_LINEAR_NOPERSPECTIVE = 4,
|
|
|
|
|
VKD3DSIM_LINEAR_NOPERSPECTIVE_CENTROID = 5,
|
|
|
|
|
VKD3DSIM_LINEAR_SAMPLE = 6,
|
|
|
|
|
VKD3DSIM_LINEAR_NOPERSPECTIVE_SAMPLE = 7,
|
2023-09-28 16:33:11 +10:00
|
|
|
|
|
|
|
|
VKD3DSIM_COUNT = 8,
|
2017-06-16 22:38:21 +02:00
|
|
|
};
|
|
|
|
|
|
2024-10-18 22:38:45 +02:00
|
|
|
enum vsir_global_flags
|
2017-06-16 22:38:21 +02:00
|
|
|
{
|
2018-10-11 15:33:33 +02:00
|
|
|
VKD3DSGF_REFACTORING_ALLOWED = 0x01,
|
2021-07-10 01:31:35 +10:00
|
|
|
VKD3DSGF_ENABLE_DOUBLE_PRECISION_FLOAT_OPS = 0x02,
|
2018-10-11 15:33:33 +02:00
|
|
|
VKD3DSGF_FORCE_EARLY_DEPTH_STENCIL = 0x04,
|
|
|
|
|
VKD3DSGF_ENABLE_RAW_AND_STRUCTURED_BUFFERS = 0x08,
|
2020-09-15 18:05:11 +01:00
|
|
|
VKD3DSGF_SKIP_OPTIMIZATION = 0x10,
|
2021-07-10 01:31:35 +10:00
|
|
|
VKD3DSGF_ENABLE_MINIMUM_PRECISION = 0x20,
|
|
|
|
|
VKD3DSGF_ENABLE_11_1_DOUBLE_EXTENSIONS = 0x40,
|
2023-10-03 14:50:09 +10:00
|
|
|
VKD3DSGF_ENABLE_SHADER_EXTENSIONS = 0x80, /* never emitted? */
|
|
|
|
|
VKD3DSGF_BIND_FOR_DURATION = 0x100,
|
|
|
|
|
VKD3DSGF_ENABLE_VP_AND_RT_ARRAY_INDEX = 0x200,
|
|
|
|
|
VKD3DSGF_ENABLE_INNER_COVERAGE = 0x400,
|
|
|
|
|
VKD3DSGF_ENABLE_STENCIL_REF = 0x800,
|
|
|
|
|
VKD3DSGF_ENABLE_TILED_RESOURCE_INTRINSICS = 0x1000,
|
|
|
|
|
VKD3DSGF_ENABLE_RELAXED_TYPED_UAV_FORMATS = 0x2000,
|
|
|
|
|
VKD3DSGF_ENABLE_LVL_9_COMPARISON_FILTERING = 0x4000,
|
|
|
|
|
VKD3DSGF_ENABLE_UP_TO_64_UAVS = 0x8000,
|
|
|
|
|
VKD3DSGF_ENABLE_UAVS_AT_EVERY_STAGE = 0x10000,
|
|
|
|
|
VKD3DSGF_ENABLE_CS4_RAW_STRUCTURED_BUFFERS = 0x20000,
|
|
|
|
|
VKD3DSGF_ENABLE_RASTERIZER_ORDERED_VIEWS = 0x40000,
|
|
|
|
|
VKD3DSGF_ENABLE_WAVE_INTRINSICS = 0x80000,
|
|
|
|
|
VKD3DSGF_ENABLE_INT64 = 0x100000,
|
|
|
|
|
VKD3DSGF_ENABLE_VIEWID = 0x200000,
|
|
|
|
|
VKD3DSGF_ENABLE_BARYCENTRICS = 0x400000,
|
|
|
|
|
VKD3DSGF_FORCE_NATIVE_LOW_PRECISION = 0x800000,
|
|
|
|
|
VKD3DSGF_ENABLE_SHADINGRATE = 0x1000000,
|
|
|
|
|
VKD3DSGF_ENABLE_RAYTRACING_TIER_1_1 = 0x2000000,
|
|
|
|
|
VKD3DSGF_ENABLE_SAMPLER_FEEDBACK = 0x4000000,
|
|
|
|
|
VKD3DSGF_ENABLE_ATOMIC_INT64_ON_TYPED_RESOURCE = 0x8000000,
|
|
|
|
|
VKD3DSGF_ENABLE_ATOMIC_INT64_ON_GROUP_SHARED = 0x10000000,
|
|
|
|
|
VKD3DSGF_ENABLE_DERIVATIVES_IN_MESH_AND_AMPLIFICATION_SHADERS = 0x20000000,
|
|
|
|
|
VKD3DSGF_ENABLE_RESOURCE_DESCRIPTOR_HEAP_INDEXING = 0x40000000,
|
|
|
|
|
VKD3DSGF_ENABLE_SAMPLER_DESCRIPTOR_HEAP_INDEXING = 0x80000000,
|
|
|
|
|
VKD3DSGF_ENABLE_ATOMIC_INT64_ON_DESCRIPTOR_HEAP_RESOURCE = 0x100000000ull,
|
2017-06-16 22:38:21 +02:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
enum vkd3d_shader_sync_flags
|
|
|
|
|
{
|
|
|
|
|
VKD3DSSF_THREAD_GROUP = 0x1,
|
|
|
|
|
VKD3DSSF_GROUP_SHARED_MEMORY = 0x2,
|
2023-08-16 13:46:10 +10:00
|
|
|
VKD3DSSF_THREAD_GROUP_UAV = 0x4,
|
2021-02-03 21:09:17 -06:00
|
|
|
VKD3DSSF_GLOBAL_UAV = 0x8,
|
2017-06-16 22:38:21 +02:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
enum vkd3d_shader_uav_flags
|
|
|
|
|
{
|
2023-08-28 14:17:17 +10:00
|
|
|
VKD3DSUF_GLOBALLY_COHERENT = 0x002,
|
|
|
|
|
VKD3DSUF_RASTERISER_ORDERED_VIEW = 0x004,
|
2017-06-16 22:38:21 +02:00
|
|
|
VKD3DSUF_ORDER_PRESERVING_COUNTER = 0x100,
|
|
|
|
|
};
|
|
|
|
|
|
2024-03-01 16:03:47 +10:00
|
|
|
enum vkd3d_shader_atomic_rmw_flags
|
|
|
|
|
{
|
vkd3d-shader/dxil: Ignore ORDERING_SEQCST.
More recent versions of the Vulkan/SPIR-V validation layers have started
to complain about our usage of "SequentiallyConsistent" in our SPIR-V
output. Specifically, VUID-StandaloneSpirv-MemorySemantics-10866 "Memory
Semantics with SequentiallyConsistent memory order must not be used in
the Vulkan API".
The SPIR-V specification says: "If the declared memory model is Vulkan,
SequentiallyConsistent must not be used." However, we're using the
GLSL450 memory model with SPIR-V 1.3, and "Vulkan" is not available
before SPIR-V 1.5.
The Vulkan specification says "Sequentially consistent atomics and
barriers are not supported and SequentiallyConsistent is treated as
AcquireRelease. SequentiallyConsistent should not be used." in the
"Shader Memory Access Ordering" section.
Those don't quite add up to the "... must not be used in the Vulkan
API", from the validation layers, but it does seem clear that
SequentiallyConsistent isn't actually supported. On the DXIL side, when
targetting SPIR-V with dxc, the generated SPIR-V uses the
"None"/"Relaxed" memory semantics. I wasn't immediately able to find a
reference for what seq_cst is supposed to mean in the context of DXIL,
but "None"/"Relaxed" does seem consistent with how the HLSL
atomic/interlocked intrinsics are expected to behave, as well as with
our behaviour for tpf shaders.
2025-10-08 16:24:44 +02:00
|
|
|
VKD3DARF_VOLATILE = 0x1,
|
2024-03-01 16:03:47 +10:00
|
|
|
};
|
|
|
|
|
|
2017-06-16 22:38:21 +02:00
|
|
|
enum vkd3d_tessellator_domain
|
|
|
|
|
{
|
2023-12-06 16:39:51 +10:00
|
|
|
VKD3D_TESSELLATOR_DOMAIN_INVALID = 0,
|
|
|
|
|
|
2017-06-16 22:38:21 +02:00
|
|
|
VKD3D_TESSELLATOR_DOMAIN_LINE = 1,
|
|
|
|
|
VKD3D_TESSELLATOR_DOMAIN_TRIANGLE = 2,
|
|
|
|
|
VKD3D_TESSELLATOR_DOMAIN_QUAD = 3,
|
2023-12-06 16:39:51 +10:00
|
|
|
|
|
|
|
|
VKD3D_TESSELLATOR_DOMAIN_COUNT = 4,
|
2017-06-16 22:38:21 +02:00
|
|
|
};
|
|
|
|
|
|
2018-06-05 13:52:57 +02:00
|
|
|
#define VKD3DSI_NONE 0x0
|
|
|
|
|
#define VKD3DSI_TEXLD_PROJECT 0x1
|
2024-05-21 21:38:44 +02:00
|
|
|
#define VKD3DSI_TEXLD_BIAS 0x2
|
2018-06-05 13:52:57 +02:00
|
|
|
#define VKD3DSI_INDEXED_DYNAMIC 0x4
|
|
|
|
|
#define VKD3DSI_RESINFO_RCP_FLOAT 0x1
|
|
|
|
|
#define VKD3DSI_RESINFO_UINT 0x2
|
|
|
|
|
#define VKD3DSI_SAMPLE_INFO_UINT 0x1
|
2017-06-16 22:38:21 +02:00
|
|
|
#define VKD3DSI_SAMPLER_COMPARISON_MODE 0x1
|
2023-11-22 23:58:44 +10:00
|
|
|
#define VKD3DSI_SHIFT_UNMASKED 0x1
|
2024-04-23 21:28:21 +10:00
|
|
|
#define VKD3DSI_WAVE_PREFIX 0x1
|
2017-06-16 22:38:21 +02:00
|
|
|
|
2018-05-29 12:50:30 +02:00
|
|
|
#define VKD3DSI_PRECISE_X 0x100
|
|
|
|
|
#define VKD3DSI_PRECISE_Y 0x200
|
|
|
|
|
#define VKD3DSI_PRECISE_Z 0x400
|
|
|
|
|
#define VKD3DSI_PRECISE_W 0x800
|
|
|
|
|
#define VKD3DSI_PRECISE_XYZW (VKD3DSI_PRECISE_X | VKD3DSI_PRECISE_Y \
|
|
|
|
|
| VKD3DSI_PRECISE_Z | VKD3DSI_PRECISE_W)
|
|
|
|
|
#define VKD3DSI_PRECISE_SHIFT 8
|
|
|
|
|
|
2017-06-16 22:38:21 +02:00
|
|
|
enum vkd3d_shader_rel_op
|
|
|
|
|
{
|
|
|
|
|
VKD3D_SHADER_REL_OP_GT = 1,
|
|
|
|
|
VKD3D_SHADER_REL_OP_EQ = 2,
|
|
|
|
|
VKD3D_SHADER_REL_OP_GE = 3,
|
|
|
|
|
VKD3D_SHADER_REL_OP_LT = 4,
|
|
|
|
|
VKD3D_SHADER_REL_OP_NE = 5,
|
|
|
|
|
VKD3D_SHADER_REL_OP_LE = 6,
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
enum vkd3d_shader_conditional_op
|
|
|
|
|
{
|
|
|
|
|
VKD3D_SHADER_CONDITIONAL_OP_NZ = 0,
|
|
|
|
|
VKD3D_SHADER_CONDITIONAL_OP_Z = 1
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
#define MAX_REG_OUTPUT 32
|
|
|
|
|
|
|
|
|
|
enum vkd3d_shader_type
|
|
|
|
|
{
|
|
|
|
|
VKD3D_SHADER_TYPE_PIXEL,
|
|
|
|
|
VKD3D_SHADER_TYPE_VERTEX,
|
|
|
|
|
VKD3D_SHADER_TYPE_GEOMETRY,
|
|
|
|
|
VKD3D_SHADER_TYPE_HULL,
|
|
|
|
|
VKD3D_SHADER_TYPE_DOMAIN,
|
|
|
|
|
VKD3D_SHADER_TYPE_GRAPHICS_COUNT,
|
|
|
|
|
|
|
|
|
|
VKD3D_SHADER_TYPE_COMPUTE = VKD3D_SHADER_TYPE_GRAPHICS_COUNT,
|
2021-01-27 10:29:44 -06:00
|
|
|
|
|
|
|
|
VKD3D_SHADER_TYPE_EFFECT,
|
|
|
|
|
VKD3D_SHADER_TYPE_TEXTURE,
|
|
|
|
|
VKD3D_SHADER_TYPE_LIBRARY,
|
2017-06-16 22:38:21 +02:00
|
|
|
VKD3D_SHADER_TYPE_COUNT,
|
|
|
|
|
};
|
|
|
|
|
|
2024-03-13 14:37:45 +01:00
|
|
|
struct vkd3d_shader_message_context;
|
|
|
|
|
|
2025-08-05 21:17:28 +02:00
|
|
|
struct vkd3d_shader_source_list
|
|
|
|
|
{
|
|
|
|
|
const char **sources;
|
|
|
|
|
size_t capacity, count;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
bool vkd3d_shader_source_list_append(struct vkd3d_shader_source_list *l, const char *source);
|
|
|
|
|
void vkd3d_shader_source_list_cleanup(struct vkd3d_shader_source_list *l);
|
|
|
|
|
void vkd3d_shader_source_list_init(struct vkd3d_shader_source_list *l);
|
|
|
|
|
|
2017-06-16 22:38:21 +02:00
|
|
|
struct vkd3d_shader_version
|
|
|
|
|
{
|
|
|
|
|
enum vkd3d_shader_type type;
|
2018-12-11 15:48:05 +01:00
|
|
|
uint8_t major;
|
|
|
|
|
uint8_t minor;
|
2017-06-16 22:38:21 +02:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
struct vkd3d_shader_immediate_constant_buffer
|
|
|
|
|
{
|
2023-11-15 16:27:41 +10:00
|
|
|
unsigned int register_idx;
|
2025-07-17 15:22:54 +02:00
|
|
|
enum vsir_data_type data_type;
|
2023-09-29 10:17:51 +10:00
|
|
|
/* total count is element_count * component_count */
|
|
|
|
|
unsigned int element_count;
|
|
|
|
|
unsigned int component_count;
|
2023-11-14 16:17:47 +10:00
|
|
|
bool is_null;
|
2023-01-20 11:35:38 +10:00
|
|
|
uint32_t data[];
|
2017-06-16 22:38:21 +02:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
struct vkd3d_shader_indexable_temp
|
|
|
|
|
{
|
|
|
|
|
unsigned int register_idx;
|
|
|
|
|
unsigned int register_size;
|
2023-11-13 16:09:58 +10:00
|
|
|
unsigned int alignment;
|
2025-07-17 15:22:54 +02:00
|
|
|
enum vsir_data_type data_type;
|
2017-06-16 22:38:21 +02:00
|
|
|
unsigned int component_count;
|
2024-01-12 12:47:19 +10:00
|
|
|
bool has_function_scope;
|
2023-11-14 00:50:30 +10:00
|
|
|
const struct vkd3d_shader_immediate_constant_buffer *initialiser;
|
2017-06-16 22:38:21 +02:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
struct vkd3d_shader_register_index
|
|
|
|
|
{
|
2024-01-17 16:10:17 +01:00
|
|
|
struct vkd3d_shader_src_param *rel_addr;
|
2017-06-16 22:38:21 +02:00
|
|
|
unsigned int offset;
|
2023-11-13 16:52:45 +10:00
|
|
|
/* address is known to fall within the object (for optimisation) */
|
|
|
|
|
bool is_in_bounds;
|
2017-06-16 22:38:21 +02:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
struct vkd3d_shader_register
|
|
|
|
|
{
|
|
|
|
|
enum vkd3d_shader_register_type type;
|
2021-09-28 16:07:22 +02:00
|
|
|
enum vkd3d_shader_register_precision precision;
|
2021-09-28 16:07:23 +02:00
|
|
|
bool non_uniform;
|
2025-07-17 15:22:54 +02:00
|
|
|
enum vsir_data_type data_type;
|
2019-04-29 11:38:15 +02:00
|
|
|
struct vkd3d_shader_register_index idx[3];
|
2023-05-03 17:10:37 +10:00
|
|
|
unsigned int idx_count;
|
2023-08-14 13:21:41 -04:00
|
|
|
enum vsir_dimension dimension;
|
2023-11-22 12:42:23 +10:00
|
|
|
/* known address alignment for optimisation, or zero */
|
|
|
|
|
unsigned int alignment;
|
2025-05-05 18:18:11 +02:00
|
|
|
union vsir_immediate_constant
|
2017-06-16 22:38:21 +02:00
|
|
|
{
|
2023-12-05 23:24:36 +01:00
|
|
|
uint32_t immconst_u32[VKD3D_VEC4_SIZE];
|
2023-12-05 23:29:04 +01:00
|
|
|
float immconst_f32[VKD3D_VEC4_SIZE];
|
2023-12-05 23:31:18 +01:00
|
|
|
uint64_t immconst_u64[VKD3D_DVEC2_SIZE];
|
2023-12-05 23:33:16 +01:00
|
|
|
double immconst_f64[VKD3D_DVEC2_SIZE];
|
2017-06-16 22:38:21 +02:00
|
|
|
unsigned fp_body_idx;
|
|
|
|
|
} u;
|
|
|
|
|
};
|
|
|
|
|
|
2023-08-29 13:20:44 -04:00
|
|
|
void vsir_register_init(struct vkd3d_shader_register *reg, enum vkd3d_shader_register_type reg_type,
|
2025-07-17 15:22:54 +02:00
|
|
|
enum vsir_data_type data_type, unsigned int idx_count);
|
2023-05-17 00:09:19 +10:00
|
|
|
|
2023-11-11 18:48:12 +01:00
|
|
|
static inline bool vsir_register_is_descriptor(const struct vkd3d_shader_register *reg)
|
|
|
|
|
{
|
|
|
|
|
switch (reg->type)
|
|
|
|
|
{
|
|
|
|
|
case VKD3DSPR_SAMPLER:
|
|
|
|
|
case VKD3DSPR_RESOURCE:
|
|
|
|
|
case VKD3DSPR_CONSTBUFFER:
|
|
|
|
|
case VKD3DSPR_UAV:
|
|
|
|
|
return true;
|
|
|
|
|
|
|
|
|
|
default:
|
|
|
|
|
return false;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
2025-08-10 19:58:02 +02:00
|
|
|
static inline enum vkd3d_shader_register_type vsir_register_type_from_sysval_input(
|
|
|
|
|
enum vkd3d_shader_sysval_semantic sysval)
|
|
|
|
|
{
|
|
|
|
|
switch (sysval)
|
|
|
|
|
{
|
|
|
|
|
case VKD3D_SHADER_SV_PRIMITIVE_ID:
|
|
|
|
|
return VKD3DSPR_PRIMID;
|
|
|
|
|
case VKD3D_SHADER_SV_COVERAGE:
|
|
|
|
|
return VKD3DSPR_COVERAGE;
|
|
|
|
|
default:
|
|
|
|
|
return VKD3DSPR_INPUT;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
2017-06-16 22:38:21 +02:00
|
|
|
struct vkd3d_shader_dst_param
|
|
|
|
|
{
|
|
|
|
|
struct vkd3d_shader_register reg;
|
2023-09-29 16:51:52 +10:00
|
|
|
uint32_t write_mask;
|
2023-12-06 00:16:06 +01:00
|
|
|
uint32_t modifiers;
|
2023-12-06 00:22:37 +01:00
|
|
|
unsigned int shift;
|
2017-06-16 22:38:21 +02:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
struct vkd3d_shader_src_param
|
|
|
|
|
{
|
|
|
|
|
struct vkd3d_shader_register reg;
|
2023-12-06 00:08:25 +01:00
|
|
|
uint32_t swizzle;
|
2017-06-16 22:38:21 +02:00
|
|
|
enum vkd3d_shader_src_modifier modifiers;
|
|
|
|
|
};
|
|
|
|
|
|
2023-11-24 13:14:44 +10:00
|
|
|
void vsir_src_param_init(struct vkd3d_shader_src_param *param, enum vkd3d_shader_register_type reg_type,
|
2025-07-17 15:22:54 +02:00
|
|
|
enum vsir_data_type data_type, unsigned int idx_count);
|
2024-01-03 16:18:50 +01:00
|
|
|
void vsir_dst_param_init(struct vkd3d_shader_dst_param *param, enum vkd3d_shader_register_type reg_type,
|
2025-07-17 15:22:54 +02:00
|
|
|
enum vsir_data_type data_type, unsigned int idx_count);
|
2025-03-07 17:22:55 -06:00
|
|
|
void vsir_dst_param_init_null(struct vkd3d_shader_dst_param *dst);
|
2024-01-12 13:20:32 +10:00
|
|
|
void vsir_src_param_init_label(struct vkd3d_shader_src_param *param, unsigned int label_id);
|
|
|
|
|
|
2017-06-16 22:38:21 +02:00
|
|
|
struct vkd3d_shader_index_range
|
|
|
|
|
{
|
2019-02-20 13:42:53 +01:00
|
|
|
struct vkd3d_shader_dst_param dst;
|
|
|
|
|
unsigned int register_count;
|
2017-06-16 22:38:21 +02:00
|
|
|
};
|
|
|
|
|
|
2021-06-24 14:03:46 +10:00
|
|
|
struct vkd3d_shader_register_range
|
|
|
|
|
{
|
|
|
|
|
unsigned int space;
|
|
|
|
|
unsigned int first, last;
|
|
|
|
|
};
|
|
|
|
|
|
2020-06-30 15:02:03 +04:30
|
|
|
struct vkd3d_shader_resource
|
|
|
|
|
{
|
|
|
|
|
struct vkd3d_shader_dst_param reg;
|
2021-06-24 14:03:46 +10:00
|
|
|
struct vkd3d_shader_register_range range;
|
2020-06-30 15:02:03 +04:30
|
|
|
};
|
|
|
|
|
|
2017-06-16 22:38:21 +02:00
|
|
|
enum vkd3d_decl_usage
|
|
|
|
|
{
|
|
|
|
|
VKD3D_DECL_USAGE_POSITION = 0,
|
|
|
|
|
VKD3D_DECL_USAGE_BLEND_WEIGHT = 1,
|
|
|
|
|
VKD3D_DECL_USAGE_BLEND_INDICES = 2,
|
|
|
|
|
VKD3D_DECL_USAGE_NORMAL = 3,
|
|
|
|
|
VKD3D_DECL_USAGE_PSIZE = 4,
|
|
|
|
|
VKD3D_DECL_USAGE_TEXCOORD = 5,
|
|
|
|
|
VKD3D_DECL_USAGE_TANGENT = 6,
|
|
|
|
|
VKD3D_DECL_USAGE_BINORMAL = 7,
|
|
|
|
|
VKD3D_DECL_USAGE_TESS_FACTOR = 8,
|
|
|
|
|
VKD3D_DECL_USAGE_POSITIONT = 9,
|
|
|
|
|
VKD3D_DECL_USAGE_COLOR = 10,
|
|
|
|
|
VKD3D_DECL_USAGE_FOG = 11,
|
|
|
|
|
VKD3D_DECL_USAGE_DEPTH = 12,
|
|
|
|
|
VKD3D_DECL_USAGE_SAMPLE = 13
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
struct vkd3d_shader_semantic
|
|
|
|
|
{
|
|
|
|
|
enum vkd3d_decl_usage usage;
|
2018-02-15 15:43:53 +01:00
|
|
|
unsigned int usage_idx;
|
2017-06-16 22:38:21 +02:00
|
|
|
enum vkd3d_shader_resource_type resource_type;
|
2023-03-04 09:58:46 +01:00
|
|
|
unsigned int sample_count;
|
2025-07-17 15:22:54 +02:00
|
|
|
enum vsir_data_type resource_data_type[VKD3D_VEC4_SIZE];
|
2020-06-30 15:02:03 +04:30
|
|
|
struct vkd3d_shader_resource resource;
|
2017-06-16 22:38:21 +02:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
enum vkd3d_shader_input_sysval_semantic
|
|
|
|
|
{
|
|
|
|
|
VKD3D_SIV_NONE = 0,
|
|
|
|
|
VKD3D_SIV_POSITION = 1,
|
|
|
|
|
VKD3D_SIV_CLIP_DISTANCE = 2,
|
|
|
|
|
VKD3D_SIV_CULL_DISTANCE = 3,
|
|
|
|
|
VKD3D_SIV_RENDER_TARGET_ARRAY_INDEX = 4,
|
|
|
|
|
VKD3D_SIV_VIEWPORT_ARRAY_INDEX = 5,
|
|
|
|
|
VKD3D_SIV_VERTEX_ID = 6,
|
|
|
|
|
VKD3D_SIV_PRIMITIVE_ID = 7,
|
|
|
|
|
VKD3D_SIV_INSTANCE_ID = 8,
|
|
|
|
|
VKD3D_SIV_IS_FRONT_FACE = 9,
|
|
|
|
|
VKD3D_SIV_SAMPLE_INDEX = 10,
|
|
|
|
|
VKD3D_SIV_QUAD_U0_TESS_FACTOR = 11,
|
|
|
|
|
VKD3D_SIV_QUAD_V0_TESS_FACTOR = 12,
|
|
|
|
|
VKD3D_SIV_QUAD_U1_TESS_FACTOR = 13,
|
|
|
|
|
VKD3D_SIV_QUAD_V1_TESS_FACTOR = 14,
|
|
|
|
|
VKD3D_SIV_QUAD_U_INNER_TESS_FACTOR = 15,
|
|
|
|
|
VKD3D_SIV_QUAD_V_INNER_TESS_FACTOR = 16,
|
|
|
|
|
VKD3D_SIV_TRIANGLE_U_TESS_FACTOR = 17,
|
|
|
|
|
VKD3D_SIV_TRIANGLE_V_TESS_FACTOR = 18,
|
|
|
|
|
VKD3D_SIV_TRIANGLE_W_TESS_FACTOR = 19,
|
|
|
|
|
VKD3D_SIV_TRIANGLE_INNER_TESS_FACTOR = 20,
|
|
|
|
|
VKD3D_SIV_LINE_DETAIL_TESS_FACTOR = 21,
|
|
|
|
|
VKD3D_SIV_LINE_DENSITY_TESS_FACTOR = 22,
|
|
|
|
|
};
|
|
|
|
|
|
2023-10-27 12:44:08 -05:00
|
|
|
#define SM1_COLOR_REGISTER_OFFSET 8
|
2023-10-27 12:44:38 -05:00
|
|
|
#define SM1_RASTOUT_REGISTER_OFFSET 10
|
2023-10-27 12:44:08 -05:00
|
|
|
|
2023-07-31 12:46:55 -05:00
|
|
|
#define SIGNATURE_TARGET_LOCATION_UNUSED (~0u)
|
|
|
|
|
|
2023-04-04 16:22:57 +10:00
|
|
|
struct signature_element
|
|
|
|
|
{
|
2024-10-08 16:26:53 +02:00
|
|
|
/* sort_index is not a property of the signature element, it is just a
|
|
|
|
|
* convenience field used to retain the original order in a signature and
|
|
|
|
|
* recover it after having permuted the signature itself. */
|
2023-04-26 15:27:08 +10:00
|
|
|
unsigned int sort_index;
|
2023-04-04 16:22:57 +10:00
|
|
|
const char *semantic_name;
|
|
|
|
|
unsigned int semantic_index;
|
|
|
|
|
unsigned int stream_index;
|
|
|
|
|
enum vkd3d_shader_sysval_semantic sysval_semantic;
|
|
|
|
|
enum vkd3d_shader_component_type component_type;
|
2023-07-31 12:40:07 -05:00
|
|
|
/* Register index in the source shader. */
|
2023-04-04 16:22:57 +10:00
|
|
|
unsigned int register_index;
|
|
|
|
|
unsigned int register_count;
|
|
|
|
|
unsigned int mask;
|
|
|
|
|
unsigned int used_mask;
|
|
|
|
|
enum vkd3d_shader_minimum_precision min_precision;
|
2023-09-28 16:33:11 +10:00
|
|
|
enum vkd3d_shader_interpolation_mode interpolation_mode;
|
2023-07-31 12:46:55 -05:00
|
|
|
/* Register index / location in the target shader.
|
|
|
|
|
* If SIGNATURE_TARGET_LOCATION_UNUSED, this element should not be written. */
|
2023-07-31 12:40:07 -05:00
|
|
|
unsigned int target_location;
|
2023-04-04 16:22:57 +10:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
struct shader_signature
|
|
|
|
|
{
|
|
|
|
|
struct signature_element *elements;
|
2023-02-24 13:12:30 -06:00
|
|
|
size_t elements_capacity;
|
2023-04-04 16:22:57 +10:00
|
|
|
unsigned int element_count;
|
|
|
|
|
};
|
|
|
|
|
|
2023-10-19 21:29:30 -05:00
|
|
|
static inline bool vsir_sysval_semantic_is_tess_factor(enum vkd3d_shader_sysval_semantic sysval_semantic)
|
|
|
|
|
{
|
|
|
|
|
return sysval_semantic >= VKD3D_SHADER_SV_TESS_FACTOR_QUADEDGE
|
|
|
|
|
&& sysval_semantic <= VKD3D_SHADER_SV_TESS_FACTOR_LINEDEN;
|
|
|
|
|
}
|
|
|
|
|
|
2023-12-06 15:07:18 +10:00
|
|
|
static inline bool vsir_sysval_semantic_is_clip_cull(enum vkd3d_shader_sysval_semantic sysval_semantic)
|
|
|
|
|
{
|
|
|
|
|
return sysval_semantic == VKD3D_SHADER_SV_CLIP_DISTANCE || sysval_semantic == VKD3D_SHADER_SV_CULL_DISTANCE;
|
|
|
|
|
}
|
|
|
|
|
|
2023-10-19 21:34:41 -05:00
|
|
|
struct signature_element *vsir_signature_find_element_for_reg(const struct shader_signature *signature,
|
|
|
|
|
unsigned int reg_idx, unsigned int write_mask);
|
2024-04-19 13:22:52 +10:00
|
|
|
bool vsir_signature_find_sysval(const struct shader_signature *signature,
|
|
|
|
|
enum vkd3d_shader_sysval_semantic sysval, unsigned int semantic_index, unsigned int *element_index);
|
2023-04-04 16:22:57 +10:00
|
|
|
void shader_signature_cleanup(struct shader_signature *signature);
|
|
|
|
|
|
2024-12-05 21:19:04 -03:00
|
|
|
struct vsir_features
|
|
|
|
|
{
|
|
|
|
|
/* The shader requires rasteriser-ordered views. */
|
|
|
|
|
bool rovs;
|
|
|
|
|
};
|
|
|
|
|
|
2024-03-01 13:52:37 +01:00
|
|
|
struct dxbc_shader_desc
|
|
|
|
|
{
|
|
|
|
|
const uint32_t *byte_code;
|
|
|
|
|
size_t byte_code_size;
|
|
|
|
|
bool is_dxil;
|
|
|
|
|
struct shader_signature input_signature;
|
|
|
|
|
struct shader_signature output_signature;
|
|
|
|
|
struct shader_signature patch_constant_signature;
|
2024-12-05 21:19:04 -03:00
|
|
|
struct vsir_features features;
|
2024-03-01 13:52:37 +01:00
|
|
|
};
|
|
|
|
|
|
2017-06-16 22:38:21 +02:00
|
|
|
struct vkd3d_shader_register_semantic
|
|
|
|
|
{
|
|
|
|
|
struct vkd3d_shader_dst_param reg;
|
|
|
|
|
enum vkd3d_shader_input_sysval_semantic sysval_semantic;
|
|
|
|
|
};
|
|
|
|
|
|
2019-04-29 11:38:15 +02:00
|
|
|
struct vkd3d_shader_sampler
|
|
|
|
|
{
|
|
|
|
|
struct vkd3d_shader_src_param src;
|
2021-06-24 14:03:47 +10:00
|
|
|
struct vkd3d_shader_register_range range;
|
2019-04-29 11:38:15 +02:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
struct vkd3d_shader_constant_buffer
|
|
|
|
|
{
|
|
|
|
|
struct vkd3d_shader_src_param src;
|
|
|
|
|
unsigned int size;
|
2021-06-24 14:03:48 +10:00
|
|
|
struct vkd3d_shader_register_range range;
|
2019-04-29 11:38:15 +02:00
|
|
|
};
|
|
|
|
|
|
2017-06-16 22:38:21 +02:00
|
|
|
struct vkd3d_shader_structured_resource
|
|
|
|
|
{
|
2020-06-30 15:02:03 +04:30
|
|
|
struct vkd3d_shader_resource resource;
|
2017-06-16 22:38:21 +02:00
|
|
|
unsigned int byte_stride;
|
2019-04-29 11:38:15 +02:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
struct vkd3d_shader_raw_resource
|
|
|
|
|
{
|
2020-06-30 15:02:03 +04:30
|
|
|
struct vkd3d_shader_resource resource;
|
2017-06-16 22:38:21 +02:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
struct vkd3d_shader_tgsm
|
|
|
|
|
{
|
|
|
|
|
unsigned int size;
|
|
|
|
|
unsigned int stride;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
struct vkd3d_shader_tgsm_raw
|
|
|
|
|
{
|
|
|
|
|
struct vkd3d_shader_dst_param reg;
|
2024-03-01 15:55:38 +10:00
|
|
|
unsigned int alignment;
|
2017-06-16 22:38:21 +02:00
|
|
|
unsigned int byte_count;
|
2023-12-01 12:54:08 +10:00
|
|
|
bool zero_init;
|
2017-06-16 22:38:21 +02:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
struct vkd3d_shader_tgsm_structured
|
|
|
|
|
{
|
|
|
|
|
struct vkd3d_shader_dst_param reg;
|
2024-03-01 15:56:31 +10:00
|
|
|
unsigned int alignment;
|
2017-06-16 22:38:21 +02:00
|
|
|
unsigned int byte_stride;
|
|
|
|
|
unsigned int structure_count;
|
2023-12-01 12:54:08 +10:00
|
|
|
bool zero_init;
|
2017-06-16 22:38:21 +02:00
|
|
|
};
|
|
|
|
|
|
2024-10-05 23:27:56 +02:00
|
|
|
struct vsir_thread_group_size
|
2017-06-16 22:38:21 +02:00
|
|
|
{
|
|
|
|
|
unsigned int x, y, z;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
struct vkd3d_shader_function_table_pointer
|
|
|
|
|
{
|
|
|
|
|
unsigned int index;
|
|
|
|
|
unsigned int array_size;
|
|
|
|
|
unsigned int body_count;
|
|
|
|
|
unsigned int table_count;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
struct vkd3d_shader_texel_offset
|
|
|
|
|
{
|
|
|
|
|
signed char u, v, w;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
enum vkd3d_primitive_type
|
|
|
|
|
{
|
|
|
|
|
VKD3D_PT_UNDEFINED = 0,
|
|
|
|
|
VKD3D_PT_POINTLIST = 1,
|
|
|
|
|
VKD3D_PT_LINELIST = 2,
|
|
|
|
|
VKD3D_PT_LINESTRIP = 3,
|
|
|
|
|
VKD3D_PT_TRIANGLELIST = 4,
|
|
|
|
|
VKD3D_PT_TRIANGLESTRIP = 5,
|
|
|
|
|
VKD3D_PT_TRIANGLEFAN = 6,
|
|
|
|
|
VKD3D_PT_LINELIST_ADJ = 10,
|
|
|
|
|
VKD3D_PT_LINESTRIP_ADJ = 11,
|
|
|
|
|
VKD3D_PT_TRIANGLELIST_ADJ = 12,
|
|
|
|
|
VKD3D_PT_TRIANGLESTRIP_ADJ = 13,
|
|
|
|
|
VKD3D_PT_PATCH = 14,
|
2024-04-19 12:43:24 +10:00
|
|
|
|
|
|
|
|
VKD3D_PT_COUNT = 15,
|
2017-06-16 22:38:21 +02:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
struct vkd3d_shader_primitive_type
|
|
|
|
|
{
|
|
|
|
|
enum vkd3d_primitive_type type;
|
|
|
|
|
unsigned int patch_vertex_count;
|
|
|
|
|
};
|
|
|
|
|
|
2023-09-05 11:31:31 +02:00
|
|
|
struct vkd3d_shader_location
|
|
|
|
|
{
|
|
|
|
|
const char *source_name;
|
|
|
|
|
unsigned int line, column;
|
|
|
|
|
};
|
|
|
|
|
|
2017-06-16 22:38:21 +02:00
|
|
|
struct vkd3d_shader_instruction
|
|
|
|
|
{
|
2023-09-05 11:31:31 +02:00
|
|
|
struct vkd3d_shader_location location;
|
2024-04-24 20:34:42 +02:00
|
|
|
enum vkd3d_shader_opcode opcode;
|
2023-12-05 23:44:05 +01:00
|
|
|
uint32_t flags;
|
2025-07-22 10:01:45 +02:00
|
|
|
size_t dst_count;
|
|
|
|
|
size_t src_count;
|
2024-01-11 11:19:39 +01:00
|
|
|
struct vkd3d_shader_dst_param *dst;
|
|
|
|
|
struct vkd3d_shader_src_param *src;
|
2017-06-16 22:38:21 +02:00
|
|
|
struct vkd3d_shader_texel_offset texel_offset;
|
2020-09-04 17:57:04 -05:00
|
|
|
enum vkd3d_shader_resource_type resource_type;
|
2021-02-19 15:57:11 +01:00
|
|
|
unsigned int resource_stride;
|
2025-07-17 15:22:54 +02:00
|
|
|
enum vsir_data_type resource_data_type[VKD3D_VEC4_SIZE];
|
2021-02-19 15:57:12 +01:00
|
|
|
bool coissue, structured, raw;
|
2018-05-29 12:50:32 +02:00
|
|
|
const struct vkd3d_shader_src_param *predicate;
|
2017-06-16 22:38:21 +02:00
|
|
|
union
|
|
|
|
|
{
|
2024-10-18 22:38:45 +02:00
|
|
|
enum vsir_global_flags global_flags;
|
2017-06-16 22:38:21 +02:00
|
|
|
struct vkd3d_shader_semantic semantic;
|
|
|
|
|
struct vkd3d_shader_register_semantic register_semantic;
|
|
|
|
|
struct vkd3d_shader_primitive_type primitive_type;
|
|
|
|
|
struct vkd3d_shader_dst_param dst;
|
2019-04-29 11:38:15 +02:00
|
|
|
struct vkd3d_shader_constant_buffer cb;
|
|
|
|
|
struct vkd3d_shader_sampler sampler;
|
2017-06-16 22:38:21 +02:00
|
|
|
unsigned int count;
|
|
|
|
|
unsigned int index;
|
|
|
|
|
const struct vkd3d_shader_immediate_constant_buffer *icb;
|
2019-04-29 11:38:15 +02:00
|
|
|
struct vkd3d_shader_raw_resource raw_resource;
|
2017-06-16 22:38:21 +02:00
|
|
|
struct vkd3d_shader_structured_resource structured_resource;
|
|
|
|
|
struct vkd3d_shader_tgsm_raw tgsm_raw;
|
|
|
|
|
struct vkd3d_shader_tgsm_structured tgsm_structured;
|
2024-10-05 23:27:56 +02:00
|
|
|
struct vsir_thread_group_size thread_group_size;
|
2017-06-16 22:38:21 +02:00
|
|
|
enum vkd3d_tessellator_domain tessellator_domain;
|
2020-06-23 13:50:13 +04:30
|
|
|
enum vkd3d_shader_tessellator_output_primitive tessellator_output_primitive;
|
2020-06-23 13:50:14 +04:30
|
|
|
enum vkd3d_shader_tessellator_partitioning tessellator_partitioning;
|
2017-06-16 22:38:21 +02:00
|
|
|
float max_tessellation_factor;
|
|
|
|
|
struct vkd3d_shader_index_range index_range;
|
|
|
|
|
struct vkd3d_shader_indexable_temp indexable_temp;
|
|
|
|
|
struct vkd3d_shader_function_table_pointer fp;
|
|
|
|
|
} declaration;
|
|
|
|
|
};
|
|
|
|
|
|
2023-10-30 17:14:26 +01:00
|
|
|
static inline bool vkd3d_shader_ver_ge(const struct vkd3d_shader_version *v, unsigned int major, unsigned int minor)
|
|
|
|
|
{
|
|
|
|
|
return v->major > major || (v->major == major && v->minor >= minor);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static inline bool vkd3d_shader_ver_le(const struct vkd3d_shader_version *v, unsigned int major, unsigned int minor)
|
|
|
|
|
{
|
|
|
|
|
return v->major < major || (v->major == major && v->minor <= minor);
|
|
|
|
|
}
|
|
|
|
|
|
2024-04-24 20:34:42 +02:00
|
|
|
void vsir_instruction_init(struct vkd3d_shader_instruction *ins,
|
|
|
|
|
const struct vkd3d_shader_location *location, enum vkd3d_shader_opcode opcode);
|
2023-05-22 16:21:46 +10:00
|
|
|
|
2025-10-01 13:21:58 -03:00
|
|
|
static inline void vkd3d_shader_instruction_make_nop(struct vkd3d_shader_instruction *ins)
|
|
|
|
|
{
|
|
|
|
|
struct vkd3d_shader_location location = ins->location;
|
|
|
|
|
|
|
|
|
|
vsir_instruction_init(ins, &location, VSIR_OP_NOP);
|
|
|
|
|
}
|
|
|
|
|
|
2018-12-11 15:48:04 +01:00
|
|
|
static inline bool vkd3d_shader_instruction_has_texel_offset(const struct vkd3d_shader_instruction *ins)
|
2017-06-16 22:38:21 +02:00
|
|
|
{
|
|
|
|
|
return ins->texel_offset.u || ins->texel_offset.v || ins->texel_offset.w;
|
|
|
|
|
}
|
|
|
|
|
|
2023-08-08 12:09:10 +10:00
|
|
|
static inline bool register_is_constant(const struct vkd3d_shader_register *reg)
|
|
|
|
|
{
|
|
|
|
|
return (reg->type == VKD3DSPR_IMMCONST || reg->type == VKD3DSPR_IMMCONST64);
|
|
|
|
|
}
|
|
|
|
|
|
2024-01-25 13:28:46 +10:00
|
|
|
static inline bool register_is_undef(const struct vkd3d_shader_register *reg)
|
|
|
|
|
{
|
|
|
|
|
return reg->type == VKD3DSPR_UNDEF;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static inline bool register_is_constant_or_undef(const struct vkd3d_shader_register *reg)
|
|
|
|
|
{
|
|
|
|
|
return register_is_constant(reg) || register_is_undef(reg);
|
|
|
|
|
}
|
|
|
|
|
|
2024-02-15 12:08:46 +10:00
|
|
|
static inline bool register_is_numeric_array(const struct vkd3d_shader_register *reg)
|
|
|
|
|
{
|
|
|
|
|
return (reg->type == VKD3DSPR_IMMCONSTBUFFER || reg->type == VKD3DSPR_IDXTEMP
|
|
|
|
|
|| reg->type == VKD3DSPR_GROUPSHAREDMEM);
|
|
|
|
|
}
|
|
|
|
|
|
2024-01-05 00:55:51 +10:00
|
|
|
static inline bool vsir_register_is_label(const struct vkd3d_shader_register *reg)
|
|
|
|
|
{
|
|
|
|
|
return reg->type == VKD3DSPR_LABEL;
|
|
|
|
|
}
|
|
|
|
|
|
2023-11-24 11:23:09 +10:00
|
|
|
static inline bool register_is_ssa(const struct vkd3d_shader_register *reg)
|
|
|
|
|
{
|
|
|
|
|
return reg->type == VKD3DSPR_SSA;
|
|
|
|
|
}
|
|
|
|
|
|
2023-01-20 11:13:01 +10:00
|
|
|
struct vkd3d_shader_param_node
|
|
|
|
|
{
|
|
|
|
|
struct vkd3d_shader_param_node *next;
|
|
|
|
|
uint8_t param[];
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
struct vkd3d_shader_param_allocator
|
|
|
|
|
{
|
|
|
|
|
struct vkd3d_shader_param_node *head;
|
|
|
|
|
struct vkd3d_shader_param_node *current;
|
2025-07-22 10:01:45 +02:00
|
|
|
size_t count;
|
|
|
|
|
size_t stride;
|
|
|
|
|
size_t index;
|
2023-01-20 11:13:01 +10:00
|
|
|
};
|
|
|
|
|
|
2025-07-22 10:01:45 +02:00
|
|
|
void *shader_param_allocator_get(struct vkd3d_shader_param_allocator *allocator, size_t count);
|
2023-01-20 11:13:01 +10:00
|
|
|
|
|
|
|
|
struct vkd3d_shader_instruction_array
|
|
|
|
|
{
|
|
|
|
|
struct vkd3d_shader_instruction *elements;
|
|
|
|
|
size_t capacity;
|
|
|
|
|
size_t count;
|
|
|
|
|
};
|
|
|
|
|
|
2025-09-15 09:33:45 -03:00
|
|
|
struct vkd3d_shader_instruction *shader_instruction_array_append(struct vkd3d_shader_instruction_array *array);
|
|
|
|
|
bool shader_instruction_array_insert_at(struct vkd3d_shader_instruction_array *instructions, size_t idx, size_t count);
|
2023-01-20 11:13:01 +10:00
|
|
|
|
2025-07-16 21:58:36 +02:00
|
|
|
struct vsir_program_iterator
|
|
|
|
|
{
|
|
|
|
|
struct vkd3d_shader_instruction_array *array;
|
|
|
|
|
size_t idx;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
static inline struct vsir_program_iterator vsir_program_iterator(struct vkd3d_shader_instruction_array *array)
|
|
|
|
|
{
|
|
|
|
|
return (struct vsir_program_iterator){ .array = array };
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static inline struct vkd3d_shader_instruction *vsir_program_iterator_current(
|
|
|
|
|
struct vsir_program_iterator *iterator)
|
|
|
|
|
{
|
|
|
|
|
if (iterator->idx >= iterator->array->count)
|
|
|
|
|
return NULL;
|
|
|
|
|
|
|
|
|
|
return &iterator->array->elements[iterator->idx];
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static inline struct vkd3d_shader_instruction *vsir_program_iterator_head(
|
|
|
|
|
struct vsir_program_iterator *iterator)
|
|
|
|
|
{
|
|
|
|
|
iterator->idx = 0;
|
|
|
|
|
|
|
|
|
|
return vsir_program_iterator_current(iterator);
|
|
|
|
|
}
|
|
|
|
|
|
2025-07-27 16:28:02 +02:00
|
|
|
static inline struct vkd3d_shader_instruction *vsir_program_iterator_tail(struct vsir_program_iterator *iterator)
|
|
|
|
|
{
|
|
|
|
|
iterator->idx = iterator->array->count - 1;
|
|
|
|
|
|
|
|
|
|
return vsir_program_iterator_current(iterator);
|
|
|
|
|
}
|
|
|
|
|
|
2025-07-16 21:58:36 +02:00
|
|
|
static inline struct vkd3d_shader_instruction *vsir_program_iterator_next(
|
|
|
|
|
struct vsir_program_iterator *iterator)
|
|
|
|
|
{
|
2025-07-31 18:08:07 -04:00
|
|
|
if (iterator->idx < iterator->array->count || iterator->idx == SIZE_MAX)
|
2025-07-16 21:58:36 +02:00
|
|
|
++iterator->idx;
|
|
|
|
|
|
|
|
|
|
return vsir_program_iterator_current(iterator);
|
|
|
|
|
}
|
|
|
|
|
|
2025-07-31 18:08:07 -04:00
|
|
|
static inline struct vkd3d_shader_instruction *vsir_program_iterator_prev(
|
|
|
|
|
struct vsir_program_iterator *iterator)
|
|
|
|
|
{
|
|
|
|
|
if (iterator->idx != SIZE_MAX)
|
|
|
|
|
--iterator->idx;
|
|
|
|
|
|
|
|
|
|
return vsir_program_iterator_current(iterator);
|
|
|
|
|
}
|
|
|
|
|
|
2025-07-16 22:06:00 +02:00
|
|
|
/* When insertion takes place, argument `it' is updated to point to the same
|
2025-09-16 03:12:59 -03:00
|
|
|
* instruction as before the insertion, but all existing pointers to the same
|
|
|
|
|
* container, as well as any iterators pointing to instructions after the
|
|
|
|
|
* insertion point should be considered invalid. */
|
2025-07-22 10:08:44 +02:00
|
|
|
static inline bool vsir_program_iterator_insert_after(struct vsir_program_iterator *it, size_t count)
|
2025-07-16 22:06:00 +02:00
|
|
|
{
|
|
|
|
|
return shader_instruction_array_insert_at(it->array, it->idx + 1, count);
|
|
|
|
|
}
|
|
|
|
|
|
2025-09-01 20:01:32 -04:00
|
|
|
/* When insertion takes place, argument `it' is updated to point to the same
|
|
|
|
|
* instruction as before the insertion, and the optional argument `ins_it' is
|
|
|
|
|
* initialized to point to the first inserted instruction.
|
|
|
|
|
* A pointer to the first inserted instruction is returned. */
|
|
|
|
|
static inline struct vkd3d_shader_instruction *vsir_program_iterator_insert_before(
|
|
|
|
|
struct vsir_program_iterator *it, struct vsir_program_iterator *ins_it, size_t count)
|
|
|
|
|
{
|
|
|
|
|
VKD3D_ASSERT(it != ins_it);
|
|
|
|
|
VKD3D_ASSERT(it->idx != SIZE_MAX);
|
|
|
|
|
|
|
|
|
|
if (!shader_instruction_array_insert_at(it->array, it->idx, count))
|
|
|
|
|
return NULL;
|
|
|
|
|
|
|
|
|
|
*ins_it = *it;
|
|
|
|
|
it->idx += count;
|
|
|
|
|
|
|
|
|
|
return vsir_program_iterator_current(ins_it);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* When insertion takes place, argument `it' is updated to point to the first
|
|
|
|
|
* inserted instruction. A pointer to this first inserted instruction is
|
|
|
|
|
* returned. */
|
2025-08-15 01:31:27 -04:00
|
|
|
static inline struct vkd3d_shader_instruction *vsir_program_iterator_insert_before_and_move(
|
|
|
|
|
struct vsir_program_iterator *it, size_t count)
|
|
|
|
|
{
|
|
|
|
|
VKD3D_ASSERT(it->idx != SIZE_MAX);
|
|
|
|
|
|
|
|
|
|
if (!shader_instruction_array_insert_at(it->array, it->idx, count))
|
|
|
|
|
return NULL;
|
|
|
|
|
return vsir_program_iterator_current(it);
|
|
|
|
|
}
|
|
|
|
|
|
2023-08-29 21:20:35 +02:00
|
|
|
enum vkd3d_shader_config_flags
|
|
|
|
|
{
|
|
|
|
|
VKD3D_SHADER_CONFIG_FLAG_FORCE_VALIDATION = 0x00000001,
|
|
|
|
|
};
|
|
|
|
|
|
2024-09-10 22:22:24 +02:00
|
|
|
enum vsir_control_flow_type
|
|
|
|
|
{
|
|
|
|
|
VSIR_CF_STRUCTURED,
|
|
|
|
|
VSIR_CF_BLOCKS,
|
|
|
|
|
};
|
|
|
|
|
|
2024-10-17 21:56:39 +02:00
|
|
|
enum vsir_normalisation_level
|
|
|
|
|
{
|
2024-12-06 22:27:01 +01:00
|
|
|
VSIR_NORMALISED_SM1,
|
2024-12-10 20:18:07 +01:00
|
|
|
VSIR_NORMALISED_SM4,
|
2024-10-17 21:56:39 +02:00
|
|
|
VSIR_NORMALISED_HULL_CONTROL_POINT_IO,
|
2024-12-10 20:18:07 +01:00
|
|
|
VSIR_NORMALISED_SM6,
|
2024-10-17 21:56:39 +02:00
|
|
|
};
|
|
|
|
|
|
2025-03-14 23:14:06 +01:00
|
|
|
struct vkd3d_shader_descriptor_info1
|
|
|
|
|
{
|
|
|
|
|
enum vkd3d_shader_descriptor_type type;
|
|
|
|
|
unsigned int register_space;
|
|
|
|
|
unsigned int register_index;
|
|
|
|
|
unsigned int register_id;
|
|
|
|
|
enum vkd3d_shader_resource_type resource_type;
|
2025-07-17 15:22:54 +02:00
|
|
|
enum vsir_data_type resource_data_type;
|
2025-03-14 23:14:06 +01:00
|
|
|
unsigned int flags;
|
|
|
|
|
unsigned int sample_count;
|
|
|
|
|
unsigned int buffer_size;
|
|
|
|
|
unsigned int structure_stride;
|
|
|
|
|
unsigned int count;
|
|
|
|
|
uint32_t uav_flags;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
struct vkd3d_shader_scan_descriptor_info1
|
|
|
|
|
{
|
|
|
|
|
struct vkd3d_shader_descriptor_info1 *descriptors;
|
|
|
|
|
unsigned int descriptor_count;
|
|
|
|
|
};
|
|
|
|
|
|
2025-03-15 16:03:50 +01:00
|
|
|
const struct vkd3d_shader_descriptor_info1 *vkd3d_shader_find_descriptor(
|
|
|
|
|
const struct vkd3d_shader_scan_descriptor_info1 *info,
|
|
|
|
|
enum vkd3d_shader_descriptor_type type, unsigned int register_id);
|
2025-03-14 23:14:06 +01:00
|
|
|
void vkd3d_shader_free_scan_descriptor_info1(struct vkd3d_shader_scan_descriptor_info1 *scan_descriptor_info);
|
|
|
|
|
|
2024-01-16 14:47:34 +01:00
|
|
|
struct vsir_program
|
|
|
|
|
{
|
2024-01-16 16:40:30 +01:00
|
|
|
struct vkd3d_shader_version shader_version;
|
2024-01-16 14:47:34 +01:00
|
|
|
struct vkd3d_shader_instruction_array instructions;
|
2024-01-17 20:39:55 +01:00
|
|
|
|
2024-03-01 13:36:11 +01:00
|
|
|
struct shader_signature input_signature;
|
|
|
|
|
struct shader_signature output_signature;
|
|
|
|
|
struct shader_signature patch_constant_signature;
|
|
|
|
|
|
2025-03-14 23:14:06 +01:00
|
|
|
struct vkd3d_shader_scan_descriptor_info1 descriptors;
|
2025-03-15 16:03:50 +01:00
|
|
|
bool has_descriptor_info;
|
2025-03-14 23:14:06 +01:00
|
|
|
|
2024-06-07 17:32:56 -05:00
|
|
|
unsigned int parameter_count;
|
|
|
|
|
const struct vkd3d_shader_parameter1 *parameters;
|
|
|
|
|
bool free_parameters;
|
|
|
|
|
|
2024-01-17 21:35:22 +01:00
|
|
|
unsigned int input_control_point_count, output_control_point_count;
|
2024-10-05 23:27:56 +02:00
|
|
|
struct vsir_thread_group_size thread_group_size;
|
2024-04-18 23:29:18 +02:00
|
|
|
unsigned int flat_constant_count[3];
|
2024-05-24 15:30:44 +10:00
|
|
|
unsigned int block_count; /* maximum block count in any function */
|
2024-01-17 21:28:23 +01:00
|
|
|
unsigned int temp_count;
|
2024-01-17 21:14:41 +01:00
|
|
|
unsigned int ssa_count;
|
2024-10-18 22:38:45 +02:00
|
|
|
enum vsir_global_flags global_flags;
|
2024-01-17 20:39:55 +01:00
|
|
|
bool use_vocp;
|
2024-10-03 13:10:10 -05:00
|
|
|
bool has_point_size;
|
2024-10-15 19:04:19 -05:00
|
|
|
bool has_point_coord;
|
2024-11-13 19:16:39 -06:00
|
|
|
bool has_fog;
|
2024-10-28 10:52:02 -05:00
|
|
|
uint8_t diffuse_written_mask;
|
2024-09-10 22:22:24 +02:00
|
|
|
enum vsir_control_flow_type cf_type;
|
2024-10-17 21:56:39 +02:00
|
|
|
enum vsir_normalisation_level normalisation_level;
|
2024-11-15 14:51:52 +01:00
|
|
|
enum vkd3d_tessellator_domain tess_domain;
|
2024-11-26 17:50:19 -03:00
|
|
|
enum vkd3d_shader_tessellator_partitioning tess_partitioning;
|
|
|
|
|
enum vkd3d_shader_tessellator_output_primitive tess_output_primitive;
|
2025-03-12 16:09:42 -04:00
|
|
|
enum vkd3d_primitive_type input_primitive, output_topology;
|
|
|
|
|
unsigned int vertices_out_count;
|
|
|
|
|
|
2024-11-17 23:27:49 +01:00
|
|
|
uint32_t io_dcls[VKD3D_BITMAP_SIZE(VKD3DSPR_COUNT)];
|
2024-01-18 20:41:27 +01:00
|
|
|
|
2024-12-05 21:19:04 -03:00
|
|
|
struct vsir_features features;
|
|
|
|
|
|
2025-08-05 21:17:49 +02:00
|
|
|
struct vkd3d_shader_source_list source_files;
|
2024-01-18 20:41:27 +01:00
|
|
|
const char **block_names;
|
|
|
|
|
size_t block_name_count;
|
2025-09-12 15:11:31 -03:00
|
|
|
|
|
|
|
|
struct vkd3d_shader_immediate_constant_buffer **icbs;
|
|
|
|
|
size_t icb_capacity;
|
|
|
|
|
size_t icb_count;
|
2025-09-12 18:17:08 -03:00
|
|
|
|
|
|
|
|
struct vkd3d_shader_param_allocator src_params;
|
|
|
|
|
struct vkd3d_shader_param_allocator dst_params;
|
2024-01-16 14:47:34 +01:00
|
|
|
};
|
|
|
|
|
|
2025-05-20 12:53:00 -05:00
|
|
|
enum vkd3d_result vsir_allocate_temp_registers(struct vsir_program *program,
|
|
|
|
|
struct vkd3d_shader_message_context *message_context);
|
2025-07-19 22:50:08 +02:00
|
|
|
enum vkd3d_result vsir_update_dcl_temps(struct vsir_program *program,
|
|
|
|
|
struct vkd3d_shader_message_context *message_context);
|
2025-09-12 15:11:31 -03:00
|
|
|
|
|
|
|
|
bool vsir_program_add_icb(struct vsir_program *program, struct vkd3d_shader_immediate_constant_buffer *icb);
|
2024-01-16 14:47:34 +01:00
|
|
|
void vsir_program_cleanup(struct vsir_program *program);
|
2024-07-18 21:38:37 -05:00
|
|
|
const struct vkd3d_shader_parameter1 *vsir_program_get_parameter(
|
|
|
|
|
const struct vsir_program *program, enum vkd3d_shader_parameter_name name);
|
2024-06-07 17:32:56 -05:00
|
|
|
bool vsir_program_init(struct vsir_program *program, const struct vkd3d_shader_compile_info *compile_info,
|
2024-10-02 14:44:38 +02:00
|
|
|
const struct vkd3d_shader_version *version, unsigned int reserve, enum vsir_control_flow_type cf_type,
|
2024-10-17 21:56:39 +02:00
|
|
|
enum vsir_normalisation_level normalisation_level);
|
2025-08-05 22:26:23 -05:00
|
|
|
enum vkd3d_result vsir_program_lower_d3dbc(struct vsir_program *program, uint64_t config_flags,
|
|
|
|
|
const struct vkd3d_shader_compile_info *compile_info, struct vkd3d_shader_message_context *message_context);
|
2025-03-05 14:23:40 -06:00
|
|
|
enum vkd3d_result vsir_program_optimize(struct vsir_program *program, uint64_t config_flags,
|
|
|
|
|
const struct vkd3d_shader_compile_info *compile_info, struct vkd3d_shader_message_context *message_context);
|
2024-09-05 20:20:03 +02:00
|
|
|
enum vkd3d_result vsir_program_transform(struct vsir_program *program, uint64_t config_flags,
|
2024-03-13 14:52:34 +01:00
|
|
|
const struct vkd3d_shader_compile_info *compile_info, struct vkd3d_shader_message_context *message_context);
|
2024-10-28 10:52:02 -05:00
|
|
|
enum vkd3d_result vsir_program_transform_early(struct vsir_program *program, uint64_t config_flags,
|
|
|
|
|
const struct vkd3d_shader_compile_info *compile_info, struct vkd3d_shader_message_context *message_context);
|
2024-03-13 14:37:45 +01:00
|
|
|
enum vkd3d_result vsir_program_validate(struct vsir_program *program, uint64_t config_flags,
|
|
|
|
|
const char *source_name, struct vkd3d_shader_message_context *message_context);
|
2024-09-05 17:25:53 +02:00
|
|
|
struct vkd3d_shader_src_param *vsir_program_create_outpointid_param(
|
|
|
|
|
struct vsir_program *program);
|
2024-05-23 12:57:44 -04:00
|
|
|
bool vsir_instruction_init_with_params(struct vsir_program *program,
|
|
|
|
|
struct vkd3d_shader_instruction *ins, const struct vkd3d_shader_location *location,
|
|
|
|
|
enum vkd3d_shader_opcode opcode, unsigned int dst_count, unsigned int src_count);
|
2024-01-16 14:47:34 +01:00
|
|
|
|
2025-07-21 21:41:16 +02:00
|
|
|
static inline struct vkd3d_shader_instruction *vsir_program_append(struct vsir_program *program)
|
|
|
|
|
{
|
2025-09-15 09:33:45 -03:00
|
|
|
return shader_instruction_array_append(&program->instructions);
|
2025-07-21 21:41:16 +02:00
|
|
|
}
|
|
|
|
|
|
2024-01-24 14:07:20 +01:00
|
|
|
static inline struct vkd3d_shader_dst_param *vsir_program_get_dst_params(
|
|
|
|
|
struct vsir_program *program, unsigned int count)
|
|
|
|
|
{
|
2025-09-12 18:17:08 -03:00
|
|
|
struct vkd3d_shader_param_allocator *allocator = &program->dst_params;
|
|
|
|
|
|
|
|
|
|
VKD3D_ASSERT(allocator->stride == sizeof(struct vkd3d_shader_dst_param));
|
|
|
|
|
|
|
|
|
|
return shader_param_allocator_get(allocator, count);
|
2024-01-24 14:07:20 +01:00
|
|
|
}
|
|
|
|
|
|
2024-01-24 14:26:35 +01:00
|
|
|
static inline struct vkd3d_shader_src_param *vsir_program_get_src_params(
|
|
|
|
|
struct vsir_program *program, unsigned int count)
|
|
|
|
|
{
|
2025-09-12 18:17:08 -03:00
|
|
|
struct vkd3d_shader_param_allocator *allocator = &program->src_params;
|
|
|
|
|
|
|
|
|
|
VKD3D_ASSERT(allocator->stride == sizeof(struct vkd3d_shader_src_param));
|
|
|
|
|
|
|
|
|
|
return shader_param_allocator_get(allocator, count);
|
2024-01-24 14:26:35 +01:00
|
|
|
}
|
|
|
|
|
|
2021-09-01 15:45:08 +02:00
|
|
|
struct vkd3d_shader_parser
|
|
|
|
|
{
|
2021-10-01 17:51:14 +02:00
|
|
|
struct vkd3d_shader_message_context *message_context;
|
2021-10-01 17:51:15 +02:00
|
|
|
struct vkd3d_shader_location location;
|
2025-10-01 12:02:54 -03:00
|
|
|
enum vkd3d_result status;
|
2021-09-01 15:45:08 +02:00
|
|
|
};
|
|
|
|
|
|
2021-10-06 17:11:46 +02:00
|
|
|
void vkd3d_shader_parser_error(struct vkd3d_shader_parser *parser,
|
|
|
|
|
enum vkd3d_shader_error error, const char *format, ...) VKD3D_PRINTF_FUNC(3, 4);
|
2025-08-20 15:24:37 +02:00
|
|
|
void vkd3d_shader_parser_init(struct vkd3d_shader_parser *parser,
|
2024-05-16 11:42:29 +02:00
|
|
|
struct vkd3d_shader_message_context *message_context, const char *source_name);
|
2021-10-06 17:11:48 +02:00
|
|
|
void vkd3d_shader_parser_warning(struct vkd3d_shader_parser *parser,
|
|
|
|
|
enum vkd3d_shader_error error, const char *format, ...) VKD3D_PRINTF_FUNC(3, 4);
|
2023-01-20 11:13:01 +10:00
|
|
|
|
2025-07-21 21:53:27 +02:00
|
|
|
void vsir_program_trace(struct vsir_program *program);
|
2021-07-02 13:12:48 +10:00
|
|
|
|
2021-10-06 17:11:47 +02:00
|
|
|
const char *shader_get_type_prefix(enum vkd3d_shader_type type);
|
2017-06-16 22:38:21 +02:00
|
|
|
|
2020-07-23 13:41:25 +04:30
|
|
|
struct vkd3d_string_buffer
|
|
|
|
|
{
|
|
|
|
|
char *buffer;
|
2021-09-30 21:36:16 +02:00
|
|
|
size_t buffer_size, content_size;
|
2020-07-23 13:41:25 +04:30
|
|
|
};
|
|
|
|
|
|
2021-02-27 18:03:09 -06:00
|
|
|
struct vkd3d_string_buffer_cache
|
|
|
|
|
{
|
|
|
|
|
struct vkd3d_string_buffer **buffers;
|
|
|
|
|
size_t count, max_count, capacity;
|
|
|
|
|
};
|
|
|
|
|
|
2024-01-17 23:14:33 +01:00
|
|
|
enum vsir_asm_flags
|
2023-11-30 12:09:04 +01:00
|
|
|
{
|
2024-01-17 23:14:33 +01:00
|
|
|
VSIR_ASM_FLAG_NONE = 0,
|
|
|
|
|
VSIR_ASM_FLAG_DUMP_TYPES = 0x1,
|
2024-09-26 22:19:55 +02:00
|
|
|
VSIR_ASM_FLAG_DUMP_ALL_INDICES = 0x2,
|
2024-10-05 22:02:12 +02:00
|
|
|
VSIR_ASM_FLAG_DUMP_SIGNATURES = 0x4,
|
2025-03-28 10:27:32 +01:00
|
|
|
VSIR_ASM_FLAG_DUMP_DESCRIPTORS = 0x8,
|
2025-08-12 15:49:05 +02:00
|
|
|
VSIR_ASM_FLAG_ALLOCATE_TEMPS = 0x10,
|
2023-11-30 12:09:04 +01:00
|
|
|
};
|
|
|
|
|
|
2025-07-21 21:53:27 +02:00
|
|
|
enum vkd3d_result d3d_asm_compile(struct vsir_program *program,
|
2025-08-12 15:49:05 +02:00
|
|
|
const struct vkd3d_shader_compile_info *compile_info, struct vkd3d_shader_code *out,
|
|
|
|
|
enum vsir_asm_flags flags, struct vkd3d_shader_message_context *message_context);
|
2021-08-09 01:11:49 -05:00
|
|
|
void vkd3d_string_buffer_cleanup(struct vkd3d_string_buffer *buffer);
|
|
|
|
|
struct vkd3d_string_buffer *vkd3d_string_buffer_get(struct vkd3d_string_buffer_cache *list);
|
|
|
|
|
void vkd3d_string_buffer_init(struct vkd3d_string_buffer *buffer);
|
|
|
|
|
void vkd3d_string_buffer_cache_cleanup(struct vkd3d_string_buffer_cache *list);
|
|
|
|
|
void vkd3d_string_buffer_cache_init(struct vkd3d_string_buffer_cache *list);
|
2024-01-30 15:07:50 +01:00
|
|
|
void vkd3d_string_buffer_clear(struct vkd3d_string_buffer *buffer);
|
2024-02-06 15:08:49 +01:00
|
|
|
void vkd3d_string_buffer_truncate(struct vkd3d_string_buffer *buffer, size_t size);
|
2022-03-01 13:21:33 +01:00
|
|
|
int vkd3d_string_buffer_print_f32(struct vkd3d_string_buffer *buffer, float f);
|
2022-03-01 13:21:34 +01:00
|
|
|
int vkd3d_string_buffer_print_f64(struct vkd3d_string_buffer *buffer, double d);
|
2025-03-14 00:11:55 +01:00
|
|
|
int vkd3d_string_buffer_print_string_escaped(struct vkd3d_string_buffer *buffer, const char *s, size_t len);
|
2021-08-09 01:11:49 -05:00
|
|
|
int vkd3d_string_buffer_printf(struct vkd3d_string_buffer *buffer, const char *format, ...) VKD3D_PRINTF_FUNC(2, 3);
|
|
|
|
|
void vkd3d_string_buffer_release(struct vkd3d_string_buffer_cache *list, struct vkd3d_string_buffer *buffer);
|
2020-12-07 12:56:30 -06:00
|
|
|
#define vkd3d_string_buffer_trace(buffer) \
|
|
|
|
|
vkd3d_string_buffer_trace_(buffer, __FUNCTION__)
|
2021-08-09 01:11:49 -05:00
|
|
|
void vkd3d_string_buffer_trace_(const struct vkd3d_string_buffer *buffer, const char *function);
|
|
|
|
|
int vkd3d_string_buffer_vprintf(struct vkd3d_string_buffer *buffer, const char *format, va_list args);
|
2024-01-10 16:16:23 +01:00
|
|
|
void vkd3d_shader_code_from_string_buffer(struct vkd3d_shader_code *code, struct vkd3d_string_buffer *buffer);
|
2020-07-23 13:41:25 +04:30
|
|
|
|
2021-07-26 15:51:29 -05:00
|
|
|
struct vkd3d_bytecode_buffer
|
|
|
|
|
{
|
|
|
|
|
uint8_t *data;
|
|
|
|
|
size_t size, capacity;
|
|
|
|
|
int status;
|
|
|
|
|
};
|
|
|
|
|
|
2023-04-05 16:55:50 -05:00
|
|
|
/* Align to the next 4-byte offset, and return that offset. */
|
|
|
|
|
size_t bytecode_align(struct vkd3d_bytecode_buffer *buffer);
|
2021-08-09 01:11:49 -05:00
|
|
|
size_t bytecode_put_bytes(struct vkd3d_bytecode_buffer *buffer, const void *bytes, size_t size);
|
2024-02-06 14:21:46 +01:00
|
|
|
size_t bytecode_put_bytes_unaligned(struct vkd3d_bytecode_buffer *buffer, const void *bytes, size_t size);
|
2023-11-05 22:07:01 +01:00
|
|
|
size_t bytecode_reserve_bytes(struct vkd3d_bytecode_buffer *buffer, size_t size);
|
2021-08-09 01:11:49 -05:00
|
|
|
void set_u32(struct vkd3d_bytecode_buffer *buffer, size_t offset, uint32_t value);
|
2023-11-05 22:07:01 +01:00
|
|
|
void set_string(struct vkd3d_bytecode_buffer *buffer, size_t offset, const char *string, size_t length);
|
2021-07-26 15:51:29 -05:00
|
|
|
|
|
|
|
|
static inline size_t put_u32(struct vkd3d_bytecode_buffer *buffer, uint32_t value)
|
|
|
|
|
{
|
|
|
|
|
return bytecode_put_bytes(buffer, &value, sizeof(value));
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static inline size_t put_f32(struct vkd3d_bytecode_buffer *buffer, float value)
|
|
|
|
|
{
|
|
|
|
|
return bytecode_put_bytes(buffer, &value, sizeof(value));
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static inline size_t put_string(struct vkd3d_bytecode_buffer *buffer, const char *string)
|
|
|
|
|
{
|
|
|
|
|
return bytecode_put_bytes(buffer, string, strlen(string) + 1);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static inline size_t bytecode_get_size(struct vkd3d_bytecode_buffer *buffer)
|
|
|
|
|
{
|
|
|
|
|
return buffer->size;
|
|
|
|
|
}
|
|
|
|
|
|
2022-05-11 16:39:08 +02:00
|
|
|
uint32_t vkd3d_parse_integer(const char *s);
|
|
|
|
|
|
2020-12-15 11:01:32 -06:00
|
|
|
struct vkd3d_shader_message_context
|
|
|
|
|
{
|
|
|
|
|
enum vkd3d_shader_log_level log_level;
|
2020-07-23 13:41:25 +04:30
|
|
|
struct vkd3d_string_buffer messages;
|
|
|
|
|
};
|
|
|
|
|
|
2021-08-09 01:11:49 -05:00
|
|
|
void vkd3d_shader_message_context_cleanup(struct vkd3d_shader_message_context *context);
|
|
|
|
|
bool vkd3d_shader_message_context_copy_messages(struct vkd3d_shader_message_context *context, char **out);
|
2020-10-09 01:14:03 -05:00
|
|
|
void vkd3d_shader_message_context_init(struct vkd3d_shader_message_context *context,
|
2021-08-09 01:11:49 -05:00
|
|
|
enum vkd3d_shader_log_level log_level);
|
2020-07-30 14:59:57 +04:30
|
|
|
void vkd3d_shader_message_context_trace_messages_(const struct vkd3d_shader_message_context *context,
|
2021-08-09 01:11:49 -05:00
|
|
|
const char *function);
|
2020-07-30 14:59:57 +04:30
|
|
|
#define vkd3d_shader_message_context_trace_messages(context) \
|
|
|
|
|
vkd3d_shader_message_context_trace_messages_(context, __FUNCTION__)
|
2020-12-15 11:01:32 -06:00
|
|
|
void vkd3d_shader_error(struct vkd3d_shader_message_context *context, const struct vkd3d_shader_location *location,
|
2021-08-09 01:11:49 -05:00
|
|
|
enum vkd3d_shader_error error, const char *format, ...) VKD3D_PRINTF_FUNC(4, 5);
|
2020-12-15 11:01:32 -06:00
|
|
|
void vkd3d_shader_verror(struct vkd3d_shader_message_context *context, const struct vkd3d_shader_location *location,
|
2021-08-09 01:11:49 -05:00
|
|
|
enum vkd3d_shader_error error, const char *format, va_list args);
|
2021-02-21 22:04:38 -06:00
|
|
|
void vkd3d_shader_vnote(struct vkd3d_shader_message_context *context, const struct vkd3d_shader_location *location,
|
2021-08-09 01:11:49 -05:00
|
|
|
enum vkd3d_shader_log_level level, const char *format, va_list args);
|
2023-12-15 14:07:21 +01:00
|
|
|
void vkd3d_shader_warning(struct vkd3d_shader_message_context *context, const struct vkd3d_shader_location *location,
|
|
|
|
|
enum vkd3d_shader_error error, const char *format, ...) VKD3D_PRINTF_FUNC(4, 5);
|
2020-12-21 14:37:06 -06:00
|
|
|
void vkd3d_shader_vwarning(struct vkd3d_shader_message_context *context, const struct vkd3d_shader_location *location,
|
2021-08-09 01:11:49 -05:00
|
|
|
enum vkd3d_shader_error error, const char *format, va_list args);
|
2020-07-23 13:41:25 +04:30
|
|
|
|
2024-05-16 11:42:16 +02:00
|
|
|
uint64_t vkd3d_shader_init_config_flags(void);
|
2021-09-16 22:36:35 -05:00
|
|
|
void vkd3d_shader_trace_text_(const char *text, size_t size, const char *function);
|
|
|
|
|
#define vkd3d_shader_trace_text(text, size) \
|
|
|
|
|
vkd3d_shader_trace_text_(text, size, __FUNCTION__)
|
2021-01-27 10:29:44 -06:00
|
|
|
|
2024-10-04 15:22:42 -03:00
|
|
|
bool sm1_register_from_semantic_name(const struct vkd3d_shader_version *version, const char *semantic_name,
|
2025-03-07 17:22:19 -06:00
|
|
|
unsigned int semantic_index, bool output, enum vkd3d_shader_sysval_semantic *sysval,
|
|
|
|
|
enum vkd3d_shader_register_type *type, unsigned int *reg);
|
2024-10-04 15:22:42 -03:00
|
|
|
bool sm1_usage_from_semantic_name(const char *semantic_name,
|
|
|
|
|
uint32_t semantic_index, enum vkd3d_decl_usage *usage, uint32_t *usage_idx);
|
2024-10-07 17:21:32 -03:00
|
|
|
bool sm4_register_from_semantic_name(const struct vkd3d_shader_version *version,
|
|
|
|
|
const char *semantic_name, bool output, enum vkd3d_shader_register_type *type, bool *has_idx);
|
2024-11-04 13:38:09 -05:00
|
|
|
bool shader_sm4_is_scalar_register(const struct vkd3d_shader_register *reg);
|
2024-10-04 14:01:08 -03:00
|
|
|
bool sm4_sysval_semantic_from_semantic_name(enum vkd3d_shader_sysval_semantic *sysval_semantic,
|
2024-10-15 16:33:21 -04:00
|
|
|
const struct vkd3d_shader_version *version, bool semantic_compat_mapping, enum vkd3d_tessellator_domain domain,
|
2025-03-13 14:31:28 -04:00
|
|
|
const char *semantic_name, unsigned int semantic_idx, bool output,
|
|
|
|
|
bool is_patch_constant_func, bool is_primitive);
|
2024-10-04 15:22:42 -03:00
|
|
|
|
2024-05-16 11:42:22 +02:00
|
|
|
int d3dbc_parse(const struct vkd3d_shader_compile_info *compile_info, uint64_t config_flags,
|
|
|
|
|
struct vkd3d_shader_message_context *message_context, struct vsir_program *program);
|
2024-05-16 11:42:29 +02:00
|
|
|
int dxil_parse(const struct vkd3d_shader_compile_info *compile_info, uint64_t config_flags,
|
|
|
|
|
struct vkd3d_shader_message_context *message_context, struct vsir_program *program);
|
2024-05-16 11:42:26 +02:00
|
|
|
int tpf_parse(const struct vkd3d_shader_compile_info *compile_info, uint64_t config_flags,
|
|
|
|
|
struct vkd3d_shader_message_context *message_context, struct vsir_program *program);
|
2024-10-04 23:36:28 +02:00
|
|
|
int fx_parse(const struct vkd3d_shader_compile_info *compile_info,
|
|
|
|
|
struct vkd3d_shader_code *out, struct vkd3d_shader_message_context *message_context);
|
2025-06-12 00:38:10 +02:00
|
|
|
int tx_parse(const struct vkd3d_shader_compile_info *compile_info,
|
|
|
|
|
struct vkd3d_shader_code *out, struct vkd3d_shader_message_context *message_context);
|
2021-10-01 17:51:11 +02:00
|
|
|
|
2024-03-01 13:52:37 +01:00
|
|
|
void free_dxbc_shader_desc(struct dxbc_shader_desc *desc);
|
2017-06-16 22:38:21 +02:00
|
|
|
|
2023-04-20 12:11:22 +02:00
|
|
|
int shader_extract_from_dxbc(const struct vkd3d_shader_code *dxbc,
|
2024-03-01 13:52:37 +01:00
|
|
|
struct vkd3d_shader_message_context *message_context, const char *source_name, struct dxbc_shader_desc *desc);
|
2023-02-20 14:57:27 +01:00
|
|
|
int shader_parse_input_signature(const struct vkd3d_shader_code *dxbc,
|
2023-04-04 16:22:57 +10:00
|
|
|
struct vkd3d_shader_message_context *message_context, struct shader_signature *signature);
|
2017-09-11 22:35:16 +02:00
|
|
|
|
2024-11-26 15:36:52 -03:00
|
|
|
int d3dbc_compile(struct vsir_program *program, uint64_t config_flags,
|
|
|
|
|
const struct vkd3d_shader_compile_info *compile_info, const struct vkd3d_shader_code *ctab,
|
|
|
|
|
struct vkd3d_shader_code *out, struct vkd3d_shader_message_context *message_context);
|
|
|
|
|
|
2024-02-24 15:13:06 +01:00
|
|
|
int glsl_compile(struct vsir_program *program, uint64_t config_flags,
|
2024-05-06 14:00:58 +02:00
|
|
|
const struct vkd3d_shader_scan_combined_resource_sampler_info *combined_sampler_info,
|
2024-02-25 00:35:48 +01:00
|
|
|
const struct vkd3d_shader_compile_info *compile_info,
|
|
|
|
|
struct vkd3d_shader_code *out, struct vkd3d_shader_message_context *message_context);
|
2021-08-19 20:18:13 +05:30
|
|
|
|
2022-03-12 15:47:38 -06:00
|
|
|
#define SPIRV_MAX_SRC_COUNT 6
|
|
|
|
|
|
2024-04-18 22:14:18 +02:00
|
|
|
int spirv_compile(struct vsir_program *program, uint64_t config_flags,
|
2022-08-06 18:39:40 -05:00
|
|
|
const struct vkd3d_shader_compile_info *compile_info,
|
|
|
|
|
struct vkd3d_shader_code *out, struct vkd3d_shader_message_context *message_context);
|
2017-06-19 18:05:53 +02:00
|
|
|
|
2024-08-29 01:21:39 +08:00
|
|
|
int msl_compile(struct vsir_program *program, uint64_t config_flags,
|
2024-10-20 21:25:10 +08:00
|
|
|
const struct vkd3d_shader_compile_info *compile_info, struct vkd3d_shader_code *out,
|
|
|
|
|
struct vkd3d_shader_message_context *message_context);
|
2024-08-27 10:34:57 +08:00
|
|
|
|
2025-03-05 14:23:40 -06:00
|
|
|
int tpf_compile(struct vsir_program *program, uint64_t config_flags,
|
|
|
|
|
const struct vkd3d_shader_compile_info *compile_info, const struct vkd3d_shader_code *rdef,
|
2024-11-26 17:05:40 -03:00
|
|
|
struct vkd3d_shader_code *out, struct vkd3d_shader_message_context *message_context);
|
|
|
|
|
|
2024-08-12 15:17:30 +02:00
|
|
|
enum vkd3d_md5_variant
|
|
|
|
|
{
|
|
|
|
|
VKD3D_MD5_STANDARD,
|
|
|
|
|
VKD3D_MD5_DXBC,
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
void vkd3d_compute_md5(const void *dxbc, size_t size, uint32_t checksum[4], enum vkd3d_md5_variant variant);
|
2018-12-17 21:21:15 +01:00
|
|
|
|
2020-12-07 12:56:30 -06:00
|
|
|
int preproc_lexer_parse(const struct vkd3d_shader_compile_info *compile_info,
|
2021-08-09 01:11:49 -05:00
|
|
|
struct vkd3d_shader_code *out, struct vkd3d_shader_message_context *message_context);
|
2020-12-07 12:56:30 -06:00
|
|
|
|
2025-07-22 22:48:27 +02:00
|
|
|
int hlsl_compile_effect(const struct vkd3d_shader_compile_info *compile_info,
|
|
|
|
|
struct vkd3d_shader_message_context *message_context, struct vkd3d_shader_code *out);
|
2025-08-05 21:17:49 +02:00
|
|
|
int hlsl_parse(const struct vkd3d_shader_compile_info *compile_info,
|
|
|
|
|
struct vkd3d_shader_message_context *message_context,
|
|
|
|
|
struct vsir_program *program, struct vkd3d_shader_code *reflection_data);
|
2021-01-27 10:29:44 -06:00
|
|
|
|
2025-07-17 15:22:54 +02:00
|
|
|
static inline enum vsir_data_type vsir_data_type_from_component_type(enum vkd3d_shader_component_type component_type)
|
2017-07-17 16:25:29 +02:00
|
|
|
{
|
|
|
|
|
switch (component_type)
|
|
|
|
|
{
|
2025-08-31 19:50:16 +02:00
|
|
|
case VKD3D_SHADER_COMPONENT_VOID:
|
|
|
|
|
return VSIR_DATA_UNUSED;
|
2020-07-10 16:44:00 +04:30
|
|
|
case VKD3D_SHADER_COMPONENT_UINT:
|
2025-07-17 16:47:43 +02:00
|
|
|
return VSIR_DATA_U32;
|
2020-07-10 16:44:00 +04:30
|
|
|
case VKD3D_SHADER_COMPONENT_INT:
|
2025-07-17 16:29:38 +02:00
|
|
|
return VSIR_DATA_I32;
|
2025-08-31 19:50:16 +02:00
|
|
|
case VKD3D_SHADER_COMPONENT_FLOAT:
|
|
|
|
|
return VSIR_DATA_F32;
|
|
|
|
|
case VKD3D_SHADER_COMPONENT_BOOL:
|
|
|
|
|
return VSIR_DATA_BOOL;
|
2021-07-10 01:31:37 +10:00
|
|
|
case VKD3D_SHADER_COMPONENT_DOUBLE:
|
2025-07-17 16:03:55 +02:00
|
|
|
return VSIR_DATA_F64;
|
2025-08-31 19:50:16 +02:00
|
|
|
case VKD3D_SHADER_COMPONENT_UINT64:
|
|
|
|
|
return VSIR_DATA_U64;
|
|
|
|
|
case VKD3D_SHADER_COMPONENT_INT64:
|
|
|
|
|
return VSIR_DATA_I64;
|
|
|
|
|
case VKD3D_SHADER_COMPONENT_FLOAT16:
|
|
|
|
|
return VSIR_DATA_F16;
|
|
|
|
|
case VKD3D_SHADER_COMPONENT_UINT16:
|
|
|
|
|
return VSIR_DATA_U16;
|
|
|
|
|
case VKD3D_SHADER_COMPONENT_INT16:
|
|
|
|
|
return VSIR_DATA_I16;
|
|
|
|
|
case VKD3D_SHADER_COMPONENT_TYPE_FORCE_32BIT:
|
|
|
|
|
break;
|
2017-07-17 16:25:29 +02:00
|
|
|
}
|
2025-08-31 19:50:16 +02:00
|
|
|
|
|
|
|
|
FIXME("Unhandled component type %#x.\n", component_type);
|
|
|
|
|
|
|
|
|
|
return VSIR_DATA_UNUSED;
|
2017-07-17 16:25:29 +02:00
|
|
|
}
|
|
|
|
|
|
2023-12-05 22:19:07 +01:00
|
|
|
static inline unsigned int vsir_write_mask_get_component_idx(uint32_t write_mask)
|
2017-06-20 13:34:44 +02:00
|
|
|
{
|
|
|
|
|
unsigned int i;
|
|
|
|
|
|
2024-08-05 16:50:30 +02:00
|
|
|
VKD3D_ASSERT(write_mask);
|
2017-06-20 13:34:44 +02:00
|
|
|
for (i = 0; i < VKD3D_VEC4_SIZE; ++i)
|
|
|
|
|
{
|
|
|
|
|
if (write_mask & (VKD3DSP_WRITEMASK_0 << i))
|
|
|
|
|
return i;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
FIXME("Invalid write mask %#x.\n", write_mask);
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
2023-12-05 22:35:37 +01:00
|
|
|
static inline unsigned int vsir_write_mask_component_count(uint32_t write_mask)
|
2017-06-20 13:34:44 +02:00
|
|
|
{
|
2019-04-30 14:33:47 +02:00
|
|
|
unsigned int count = vkd3d_popcount(write_mask & VKD3DSP_WRITEMASK_ALL);
|
2024-08-05 16:50:30 +02:00
|
|
|
VKD3D_ASSERT(1 <= count && count <= VKD3D_VEC4_SIZE);
|
2019-04-30 14:33:47 +02:00
|
|
|
return count;
|
2017-06-20 13:34:44 +02:00
|
|
|
}
|
|
|
|
|
|
2018-06-26 14:41:44 +02:00
|
|
|
static inline unsigned int vkd3d_write_mask_from_component_count(unsigned int component_count)
|
|
|
|
|
{
|
2024-08-05 16:50:30 +02:00
|
|
|
VKD3D_ASSERT(component_count <= VKD3D_VEC4_SIZE);
|
2018-06-26 14:41:44 +02:00
|
|
|
return (VKD3DSP_WRITEMASK_0 << component_count) - 1;
|
|
|
|
|
}
|
|
|
|
|
|
2023-12-05 22:39:12 +01:00
|
|
|
static inline uint32_t vsir_write_mask_64_from_32(uint32_t write_mask32)
|
2021-07-28 00:26:10 +10:00
|
|
|
{
|
2024-01-20 23:30:23 +01:00
|
|
|
switch (write_mask32)
|
|
|
|
|
{
|
|
|
|
|
case VKD3DSP_WRITEMASK_0 | VKD3DSP_WRITEMASK_1:
|
|
|
|
|
return VKD3DSP_WRITEMASK_0;
|
|
|
|
|
|
|
|
|
|
case VKD3DSP_WRITEMASK_2 | VKD3DSP_WRITEMASK_3:
|
|
|
|
|
return VKD3DSP_WRITEMASK_1;
|
|
|
|
|
|
|
|
|
|
case VKD3DSP_WRITEMASK_0 | VKD3DSP_WRITEMASK_1 | VKD3DSP_WRITEMASK_2 | VKD3DSP_WRITEMASK_3:
|
|
|
|
|
return VKD3DSP_WRITEMASK_0 | VKD3DSP_WRITEMASK_1;
|
|
|
|
|
|
|
|
|
|
default:
|
|
|
|
|
ERR("Invalid 32 bit writemask when converting to 64 bit: %#x.\n", write_mask32);
|
|
|
|
|
return VKD3DSP_WRITEMASK_0;
|
|
|
|
|
}
|
2021-07-28 00:26:10 +10:00
|
|
|
}
|
|
|
|
|
|
2023-12-05 22:42:32 +01:00
|
|
|
static inline uint32_t vsir_write_mask_32_from_64(uint32_t write_mask64)
|
2021-07-19 12:30:15 +10:00
|
|
|
{
|
2024-01-20 23:30:23 +01:00
|
|
|
switch (write_mask64)
|
|
|
|
|
{
|
|
|
|
|
case VKD3DSP_WRITEMASK_0:
|
|
|
|
|
return VKD3DSP_WRITEMASK_0 | VKD3DSP_WRITEMASK_1;
|
|
|
|
|
|
|
|
|
|
case VKD3DSP_WRITEMASK_1:
|
|
|
|
|
return VKD3DSP_WRITEMASK_2 | VKD3DSP_WRITEMASK_3;
|
|
|
|
|
|
|
|
|
|
case VKD3DSP_WRITEMASK_0 | VKD3DSP_WRITEMASK_1:
|
|
|
|
|
return VKD3DSP_WRITEMASK_0 | VKD3DSP_WRITEMASK_1 | VKD3DSP_WRITEMASK_2 | VKD3DSP_WRITEMASK_3;
|
|
|
|
|
|
|
|
|
|
default:
|
|
|
|
|
ERR("Invalid 64 bit writemask: %#x.\n", write_mask64);
|
|
|
|
|
return VKD3DSP_WRITEMASK_0;
|
|
|
|
|
}
|
2021-07-19 12:30:15 +10:00
|
|
|
}
|
|
|
|
|
|
2025-05-20 12:59:27 -05:00
|
|
|
const char *debug_vsir_writemask(unsigned int writemask);
|
|
|
|
|
|
2024-01-22 17:15:36 +01:00
|
|
|
static inline uint32_t vsir_swizzle_64_from_32(uint32_t swizzle32)
|
2017-06-20 13:34:44 +02:00
|
|
|
{
|
2024-01-22 17:15:36 +01:00
|
|
|
switch (swizzle32)
|
|
|
|
|
{
|
|
|
|
|
case VKD3D_SHADER_SWIZZLE(X, Y, X, Y):
|
|
|
|
|
return VKD3D_SHADER_SWIZZLE(X, X, X, X);
|
|
|
|
|
|
|
|
|
|
case VKD3D_SHADER_SWIZZLE(X, Y, Z, W):
|
|
|
|
|
return VKD3D_SHADER_SWIZZLE(X, Y, X, X);
|
|
|
|
|
|
|
|
|
|
case VKD3D_SHADER_SWIZZLE(Z, W, X, Y):
|
|
|
|
|
return VKD3D_SHADER_SWIZZLE(Y, X, X, X);
|
|
|
|
|
|
|
|
|
|
case VKD3D_SHADER_SWIZZLE(Z, W, Z, W):
|
|
|
|
|
return VKD3D_SHADER_SWIZZLE(Y, Y, X, X);
|
|
|
|
|
|
|
|
|
|
default:
|
|
|
|
|
ERR("Invalid 32 bit swizzle when converting to 64 bit: %#x.\n", swizzle32);
|
|
|
|
|
return VKD3D_SHADER_SWIZZLE(X, X, X, X);
|
|
|
|
|
}
|
2017-06-20 13:34:44 +02:00
|
|
|
}
|
2021-07-30 23:27:21 +10:00
|
|
|
|
2024-01-22 17:15:36 +01:00
|
|
|
static inline uint32_t vsir_swizzle_32_from_64(uint32_t swizzle64)
|
2021-07-30 23:27:21 +10:00
|
|
|
{
|
2024-01-22 17:15:36 +01:00
|
|
|
switch (swizzle64)
|
|
|
|
|
{
|
|
|
|
|
case VKD3D_SHADER_SWIZZLE(X, X, X, X):
|
|
|
|
|
return VKD3D_SHADER_SWIZZLE(X, Y, X, Y);
|
|
|
|
|
|
|
|
|
|
case VKD3D_SHADER_SWIZZLE(X, Y, X, X):
|
|
|
|
|
return VKD3D_SHADER_SWIZZLE(X, Y, Z, W);
|
|
|
|
|
|
|
|
|
|
case VKD3D_SHADER_SWIZZLE(Y, X, X, X):
|
|
|
|
|
return VKD3D_SHADER_SWIZZLE(Z, W, X, Y);
|
|
|
|
|
|
|
|
|
|
case VKD3D_SHADER_SWIZZLE(Y, Y, X, X):
|
|
|
|
|
return VKD3D_SHADER_SWIZZLE(Z, W, Z, W);
|
|
|
|
|
|
|
|
|
|
default:
|
|
|
|
|
ERR("Invalid 64 bit swizzle: %#x.\n", swizzle64);
|
|
|
|
|
return VKD3D_SHADER_SWIZZLE(X, Y, X, Y);
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static inline unsigned int vsir_swizzle_get_component(uint32_t swizzle, unsigned int idx)
|
|
|
|
|
{
|
|
|
|
|
return (swizzle >> VKD3D_SHADER_SWIZZLE_SHIFT(idx)) & VKD3D_SHADER_SWIZZLE_MASK;
|
2021-07-30 23:27:21 +10:00
|
|
|
}
|
2017-06-20 13:34:44 +02:00
|
|
|
|
2025-05-20 12:59:27 -05:00
|
|
|
static inline void vsir_swizzle_set_component(uint32_t *swizzle, unsigned int idx, unsigned int component)
|
|
|
|
|
{
|
|
|
|
|
*swizzle &= ~(VKD3D_SHADER_SWIZZLE_MASK << VKD3D_SHADER_SWIZZLE_SHIFT(idx));
|
|
|
|
|
*swizzle |= component << VKD3D_SHADER_SWIZZLE_SHIFT(idx);
|
|
|
|
|
}
|
|
|
|
|
|
2023-12-05 23:05:40 +01:00
|
|
|
static inline unsigned int vkd3d_compact_swizzle(uint32_t swizzle, uint32_t write_mask)
|
2018-10-31 15:26:46 +01:00
|
|
|
{
|
|
|
|
|
unsigned int i, compacted_swizzle = 0;
|
|
|
|
|
|
|
|
|
|
for (i = 0; i < VKD3D_VEC4_SIZE; ++i)
|
|
|
|
|
{
|
|
|
|
|
if (write_mask & (VKD3DSP_WRITEMASK_0 << i))
|
|
|
|
|
{
|
2020-07-10 16:44:02 +04:30
|
|
|
compacted_swizzle <<= VKD3D_SHADER_SWIZZLE_SHIFT(1);
|
2023-12-05 23:05:40 +01:00
|
|
|
compacted_swizzle |= vsir_swizzle_get_component(swizzle, i);
|
2018-10-31 15:26:46 +01:00
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
return compacted_swizzle;
|
|
|
|
|
}
|
|
|
|
|
|
2024-04-11 12:38:24 +02:00
|
|
|
static inline uint32_t vsir_swizzle_from_writemask(unsigned int writemask)
|
|
|
|
|
{
|
|
|
|
|
static const unsigned int swizzles[16] =
|
|
|
|
|
{
|
|
|
|
|
0,
|
|
|
|
|
VKD3D_SHADER_SWIZZLE(X, X, X, X),
|
|
|
|
|
VKD3D_SHADER_SWIZZLE(Y, Y, Y, Y),
|
|
|
|
|
VKD3D_SHADER_SWIZZLE(X, Y, X, X),
|
|
|
|
|
VKD3D_SHADER_SWIZZLE(Z, Z, Z, Z),
|
|
|
|
|
VKD3D_SHADER_SWIZZLE(X, Z, X, X),
|
|
|
|
|
VKD3D_SHADER_SWIZZLE(Y, Z, X, X),
|
|
|
|
|
VKD3D_SHADER_SWIZZLE(X, Y, Z, X),
|
|
|
|
|
VKD3D_SHADER_SWIZZLE(W, W, W, W),
|
|
|
|
|
VKD3D_SHADER_SWIZZLE(X, W, X, X),
|
|
|
|
|
VKD3D_SHADER_SWIZZLE(Y, W, X, X),
|
|
|
|
|
VKD3D_SHADER_SWIZZLE(X, Y, W, X),
|
|
|
|
|
VKD3D_SHADER_SWIZZLE(Z, W, X, X),
|
|
|
|
|
VKD3D_SHADER_SWIZZLE(X, Z, W, X),
|
|
|
|
|
VKD3D_SHADER_SWIZZLE(Y, Z, W, X),
|
|
|
|
|
VKD3D_SHADER_SWIZZLE(X, Y, Z, W),
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
return swizzles[writemask & 0xf];
|
|
|
|
|
}
|
|
|
|
|
|
2020-07-30 14:59:55 +04:30
|
|
|
struct vkd3d_struct
|
|
|
|
|
{
|
|
|
|
|
enum vkd3d_shader_structure_type type;
|
|
|
|
|
const void *next;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
#define vkd3d_find_struct(c, t) vkd3d_find_struct_(c, VKD3D_SHADER_STRUCTURE_TYPE_##t)
|
|
|
|
|
static inline void *vkd3d_find_struct_(const struct vkd3d_struct *chain,
|
|
|
|
|
enum vkd3d_shader_structure_type type)
|
|
|
|
|
{
|
|
|
|
|
while (chain)
|
|
|
|
|
{
|
|
|
|
|
if (chain->type == type)
|
|
|
|
|
return (void *)chain;
|
|
|
|
|
|
|
|
|
|
chain = chain->next;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
return NULL;
|
|
|
|
|
}
|
|
|
|
|
|
2018-04-11 13:21:41 +02:00
|
|
|
#define VKD3D_DXBC_HEADER_SIZE (8 * sizeof(uint32_t))
|
2022-11-15 15:16:41 +10:00
|
|
|
#define VKD3D_DXBC_CHUNK_ALIGNMENT sizeof(uint32_t)
|
2017-06-20 14:14:44 +02:00
|
|
|
|
2024-10-15 16:33:21 -04:00
|
|
|
#define DXBC_MAX_SECTION_COUNT 7
|
2021-08-17 12:38:57 -05:00
|
|
|
|
2024-12-05 21:19:04 -03:00
|
|
|
#define DXBC_SFI0_REQUIRES_DOUBLES 0x00000001u
|
|
|
|
|
#define DXBC_SFI0_REQUIRES_EARLY_DEPTH_STENCIL 0x00000002u
|
|
|
|
|
#define DXBC_SFI0_REQUIRES_UAVS_AT_EVERY_STAGE 0x00000004u
|
|
|
|
|
#define DXBC_SFI0_REQUIRES_64_UAVS 0x00000008u
|
|
|
|
|
#define DXBC_SFI0_REQUIRES_MINIMUM_PRECISION 0x00000010u
|
|
|
|
|
#define DXBC_SFI0_REQUIRES_11_1_DOUBLE_EXTENSIONS 0x00000020u
|
|
|
|
|
#define DXBC_SFI0_REQUIRES_11_1_SHADER_EXTENSIONS 0x00000040u
|
|
|
|
|
#define DXBC_SFI0_REQUIRES_LEVEL_9_COMPARISON_FILTERING 0x00000080u
|
|
|
|
|
#define DXBC_SFI0_REQUIRES_TILED_RESOURCES 0x00000100u
|
|
|
|
|
#define DXBC_SFI0_REQUIRES_STENCIL_REF 0x00000200u
|
|
|
|
|
#define DXBC_SFI0_REQUIRES_INNER_COVERAGE 0x00000400u
|
|
|
|
|
#define DXBC_SFI0_REQUIRES_TYPED_UAV_LOAD_ADDITIONAL_FORMATS 0x00000800u
|
|
|
|
|
#define DXBC_SFI0_REQUIRES_ROVS 0x00001000u
|
|
|
|
|
#define DXBC_SFI0_REQUIRES_VIEWPORT_AND_RT_ARRAY_INDEX_FROM_ANY_SHADER_FEEDING_RASTERIZER 0x00002000u
|
|
|
|
|
|
2021-08-17 12:38:57 -05:00
|
|
|
struct dxbc_writer
|
|
|
|
|
{
|
|
|
|
|
unsigned int section_count;
|
2023-02-20 13:50:22 +01:00
|
|
|
struct vkd3d_shader_dxbc_section_desc sections[DXBC_MAX_SECTION_COUNT];
|
2021-08-17 12:38:57 -05:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
void dxbc_writer_add_section(struct dxbc_writer *dxbc, uint32_t tag, const void *data, size_t size);
|
|
|
|
|
void dxbc_writer_init(struct dxbc_writer *dxbc);
|
|
|
|
|
int dxbc_writer_write(struct dxbc_writer *dxbc, struct vkd3d_shader_code *code);
|
|
|
|
|
|
2017-06-16 22:38:21 +02:00
|
|
|
#endif /* __VKD3D_SHADER_PRIVATE_H */
|