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vkd3d-shader: Implement DMOV instruction.

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Signed-off-by: Conor McCarthy <cmccarthy@codeweavers.com>
Signed-off-by: Henri Verbeet <hverbeet@codeweavers.com>
Signed-off-by: Alexandre Julliard <julliard@winehq.org>
This commit is contained in:
Conor McCarthy 2021-07-28 00:26:10 +10:00 committed by Alexandre Julliard
parent 82237796ad
commit 4e63842a73
5 changed files with 23 additions and 4 deletions
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4
libs/vkd3d-shader/dxbc.c
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@ -311,6 +311,7 @@ enum vkd3d_sm4_opcode
VKD3D_SM5_OP_IMM_ATOMIC_UMIN = 0xbd,
VKD3D_SM5_OP_SYNC = 0xbe,
VKD3D_SM5_OP_DEQ = 0xc3,
VKD3D_SM5_OP_DMOV = 0xc7,
VKD3D_SM5_OP_EVAL_SAMPLE_INDEX = 0xcc,
VKD3D_SM5_OP_EVAL_CENTROID = 0xcd,
VKD3D_SM5_OP_DCL_GS_INSTANCES = 0xce,
@ -1250,6 +1251,7 @@ static const struct vkd3d_sm4_opcode_info opcode_table[] =
{VKD3D_SM5_OP_SYNC, VKD3DSIH_SYNC, "", "",
shader_sm5_read_sync},
{VKD3D_SM5_OP_DEQ, VKD3DSIH_DEQ, "u", "dd"},
{VKD3D_SM5_OP_DMOV, VKD3DSIH_DMOV, "d", "d"},
{VKD3D_SM5_OP_EVAL_SAMPLE_INDEX, VKD3DSIH_EVAL_SAMPLE_INDEX, "f", "fi"},
{VKD3D_SM5_OP_EVAL_CENTROID, VKD3DSIH_EVAL_CENTROID, "f", "f"},
{VKD3D_SM5_OP_DCL_GS_INSTANCES, VKD3DSIH_DCL_GS_INSTANCES, "", "",
@ -1804,6 +1806,8 @@ static bool shader_sm4_read_dst_param(struct vkd3d_sm4_data *priv, const DWORD *
}
dst_param->write_mask = (token & VKD3D_SM4_WRITEMASK_MASK) >> VKD3D_SM4_WRITEMASK_SHIFT;
if (data_type == VKD3D_DATA_DOUBLE)
dst_param->write_mask = vkd3d_write_mask_64_from_32(dst_param->write_mask);
/* Scalar registers are declared with no write mask in shader bytecode. */
if (!dst_param->write_mask && shader_sm4_is_scalar_register(&dst_param->reg))
dst_param->write_mask = VKD3DSP_WRITEMASK_0;

10
libs/vkd3d-shader/spirv.c
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@ -3613,6 +3613,7 @@ static void vkd3d_dxbc_compiler_emit_store_reg(struct vkd3d_dxbc_compiler *compi
struct vkd3d_spirv_builder *builder = &compiler->spirv_builder;
enum vkd3d_shader_component_type component_type;
struct vkd3d_shader_register_info reg_info;
unsigned int src_write_mask = write_mask;
uint32_t type_id;
assert(reg->type != VKD3DSPR_IMMCONST);
@ -3624,14 +3625,16 @@ static void vkd3d_dxbc_compiler_emit_store_reg(struct vkd3d_dxbc_compiler *compi
component_type = vkd3d_component_type_from_data_type(reg->data_type);
if (component_type != reg_info.component_type)
{
unsigned int component_count = vkd3d_write_mask_component_count(write_mask);
type_id = vkd3d_spirv_get_type_id(builder, reg_info.component_type, component_count);
if (reg->data_type == VKD3D_DATA_DOUBLE)
src_write_mask = vkd3d_write_mask_32_from_64(write_mask);
type_id = vkd3d_spirv_get_type_id(builder, reg_info.component_type,
vkd3d_write_mask_component_count(src_write_mask));
val_id = vkd3d_spirv_build_op_bitcast(builder, type_id, val_id);
component_type = reg_info.component_type;
}
vkd3d_dxbc_compiler_emit_store(compiler,
reg_info.id, reg_info.write_mask, component_type, reg_info.storage_class, write_mask, val_id);
reg_info.id, reg_info.write_mask, component_type, reg_info.storage_class, src_write_mask, val_id);
}
static uint32_t vkd3d_dxbc_compiler_emit_sat(struct vkd3d_dxbc_compiler *compiler,
@ -9349,6 +9352,7 @@ int vkd3d_dxbc_compiler_handle_instruction(struct vkd3d_dxbc_compiler *compiler,
case VKD3DSIH_HS_JOIN_PHASE:
vkd3d_dxbc_compiler_enter_shader_phase(compiler, instruction);
break;
case VKD3DSIH_DMOV:
case VKD3DSIH_MOV:
vkd3d_dxbc_compiler_emit_mov(compiler, instruction);
break;

4
libs/vkd3d-shader/trace.c
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@ -105,6 +105,7 @@ static const char * const shader_opcode_names[] =
/* VKD3DSIH_DEFI */ "defi",
/* VKD3DSIH_DEQ */ "deq",
/* VKD3DSIH_DIV */ "div",
/* VKD3DSIH_DMOV */ "dmov",
/* VKD3DSIH_DP2 */ "dp2",
/* VKD3DSIH_DP2ADD */ "dp2add",
/* VKD3DSIH_DP3 */ "dp3",
@ -1122,6 +1123,9 @@ static void shader_dump_dst_param(struct vkd3d_d3d_asm_compiler *compiler,
{
static const char write_mask_chars[] = "xyzw";
if (param->reg.data_type == VKD3D_DATA_DOUBLE)
write_mask = vkd3d_write_mask_32_from_64(write_mask);
shader_addline(buffer, ".%s", compiler->colours.write_mask);
if (write_mask & VKD3DSP_WRITEMASK_0)
shader_addline(buffer, "%c", write_mask_chars[0]);

7
libs/vkd3d-shader/vkd3d_shader_private.h
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@ -193,6 +193,7 @@ enum vkd3d_shader_opcode
VKD3DSIH_DEFI,
VKD3DSIH_DEQ,
VKD3DSIH_DIV,
VKD3DSIH_DMOV,
VKD3DSIH_DP2,
VKD3DSIH_DP2ADD,
VKD3DSIH_DP3,
@ -1064,6 +1065,12 @@ static inline unsigned int vkd3d_write_mask_from_component_count(unsigned int co
return (VKD3DSP_WRITEMASK_0 << component_count) - 1;
}
static inline unsigned int vkd3d_write_mask_64_from_32(DWORD write_mask32)
{
unsigned int write_mask64 = write_mask32 | (write_mask32 >> 1);
return (write_mask64 & VKD3DSP_WRITEMASK_0) | ((write_mask64 & VKD3DSP_WRITEMASK_2) >> 1);
}
static inline unsigned int vkd3d_write_mask_32_from_64(unsigned int write_mask64)
{
unsigned int write_mask32 = (write_mask64 | (write_mask64 << 1))

2
tests/d3d12.c
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@ -9878,7 +9878,7 @@ static void test_shader_instructions(void)
{&ps_movc, {{{0, 1, 1, 0}, {1, 2, 3, 4}, {5, 6, 7, 8}}}, {{5, 2, 3, 8}}},
{&ps_movc, {{{1, 1, 1, 1}, {1, 2, 3, 4}, {5, 6, 7, 8}}}, {{1, 2, 3, 4}}},
{&ps_dmov, {.d = {{2.5 + 1.0e-9, -3.5 - 1.0e-9}}}, {.d = {3.5 + 1.0e-9, -2.5 - 1.0e-9}}, true, true},
{&ps_dmov, {.d = {{2.5 + 1.0e-9, -3.5 - 1.0e-9}}}, {.d = {3.5 + 1.0e-9, -2.5 - 1.0e-9}}, true},
{&ps_dadd, {.d = {{2.5, 0.0}}}, {.d = {2.5 + 1.0000002433080226, 2.5 + 2.000000481493771}}, true, true},
{&ps_dmin_dmax, {.d = {{-1.0, 1.0}}}, {.d = {-1.0, 1.0}}, true, true},
{&ps_dmovc, {.d = {{0.5, 0.0}}}, {.d = {4.5, 4.5}}, true, true},