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874 Commits

Author SHA1 Message Date
Conor McCarthy
065ef0c5e4 vkd3d-shader/spirv: Implement the WAVE_IS_FIRST_LANE instruction. 2024-05-13 11:50:21 +02:00
Conor McCarthy
feef2577ef vkd3d-shader/spirv: Implement the WAVE_ALL_BIT_COUNT instruction. 2024-05-13 11:50:19 +02:00
Conor McCarthy
cfcc789b42 vkd3d-shader/spirv: Implement the WAVE_OP_* instructions. 2024-05-06 22:12:27 +02:00
Conor McCarthy
fef5760af0 vkd3d-shader/spirv: Implement the WAVE_ACTIVE_BIT_* instructions. 2024-05-06 22:12:24 +02:00
Conor McCarthy
1c49b3a779 vkd3d-shader/spirv: Implement the WAVE_ACTIVE_BALLOT instruction. 2024-05-06 22:12:21 +02:00
Henri Verbeet
f948520504 vkd3d-shader/spirv: Pass a struct vsir_program to spirv_compile(). 2024-05-02 22:19:17 +02:00
Henri Verbeet
e21215f466 vkd3d-shader/spirv: Pass a struct vsir_program to spirv_compiler_generate_spirv(). 2024-05-02 22:19:16 +02:00
Conor McCarthy
95489899be vkd3d-shader/spirv: Handle the WAVE_ANY_TRUE instruction. 2024-05-02 22:19:02 +02:00
Conor McCarthy
77ec2a5caa vkd3d-shader/spirv: Handle the WAVE_ALL_TRUE instruction. 2024-05-02 22:18:59 +02:00
Conor McCarthy
78f2d2936d vkd3d-shader/spirv: Handle the WAVE_ACTIVE_ALL_EQUAL instruction. 2024-05-02 22:18:57 +02:00
Conor McCarthy
c770efc530 vkd3d-shader/spirv: Handle the WAVELANEINDEX register. 2024-05-02 22:18:54 +02:00
Conor McCarthy
a130c970a6 vkd3d-shader/spirv: Handle the WAVELANECOUNT register. 2024-05-02 22:18:49 +02:00
Henri Verbeet
b761f1a263 vkd3d-shader/spirv: Use location information from the current instruction. 2024-04-30 16:31:14 +02:00
Conor McCarthy
6975a8d726 vkd3d-shader: Introduce SPIRV_ENVIRONMENT_VULKAN_1_1. 
The SPIR-V backend may emit SPIR-V 1.3 if Vulkan 1.1 is available.
Some extensions which provide wave op instructions are available in
SPIR-V 1.0, but these are not sufficient to implement all Shader Model 6
wave op intrinsics. SPIR-V 1.3 has all of the required instructions, but
does not support reading from a quad at a non-constant (but uniform) lane
index, so it may later prove necessary to introduce a Vulkan 1.2
environment.
 2024-04-17 22:51:49 +02:00
Conor McCarthy
a7870e1793 vkd3d-shader/spirv: Emit a compiler warning if an atomic op is flagged volatile. 2024-04-17 22:51:43 +02:00
Henri Verbeet
1d6c3eae78 vkd3d-shader/ir: Remove VKD3DSIH_DCL_CONSTANT_BUFFER instructions. 2024-04-16 22:18:52 +02:00
Conor McCarthy
54016b3ced vkd3d-shader/dxil: Load hull shader properties. 2024-04-16 22:18:15 +02:00
Conor McCarthy
e72c3bab71 vkd3d-shader/spirv: Ensure the data register is UINT in spirv_compiler_emit_store_tgsm(). 2024-04-09 12:27:30 -05:00
Conor McCarthy
dc99159dd8 vkd3d-shader/spirv: Bitcast if necessary in spirv_compiler_emit_store_dst_components(). 2024-04-09 12:27:29 -05:00
Conor McCarthy
1c61776c18 vkd3d-shader/spirv: Handle uint2 to double bitcast in spirv_compiler_emit_mov(). 
Necessary for MakeDouble if the dst is SSA.
 2024-04-09 12:27:18 -05:00
Conor McCarthy
c8eb7e1c81 vkd3d-shader/spirv: Emit a uint result for RESINFO_UINT if the dst register is SSA. 2024-04-09 12:27:16 -05:00
Conor McCarthy
8d947ce868 vkd3d-shader/spirv: Support bool source in spirv_compiler_emit_discard(). 2024-03-27 22:37:40 +01:00
Francisco Casas
11e7265815 vkd3d-shader/spirv: Throw compiler error on unrecognized register. 
This codepath path is currently triggered when transpiling d3dbc shaders
that use vPos (or other of these special registers).

While vPos gets added to the input signature and gets assigned an INPUT
register, the registers in the shader instructions are still of
VKD3DSPR_MISCTYPE type and are not propperly mapped yet. This gives
invalid results.

Some SM1 tests must be set back to "todo" but they only work because, by
coincidence, we are assigning vPos the input register with index 0.
Propper mapping of these registers is still required.
 2024-03-27 22:37:15 +01:00
Zebediah Figura
172cb75872 vkd3d-shader/spirv: Implement VKD3DSIH_ABS. 2024-03-27 22:37:10 +01:00
Conor McCarthy
68b31b7396 vkd3d-shader/spirv: Handle the sequentially consistent ordering flag for atomic instructions. 2024-03-27 22:37:01 +01:00
Conor McCarthy
a8dd788f41 vkd3d-shader/spirv: Emit a warning if the atomic instruction volatile flag is unhandled. 2024-03-27 22:37:00 +01:00
Conor McCarthy
47e56cdfed vkd3d-shader/spirv: Support 64-bit register info component type in spirv_compiler_emit_load_reg(). 
For 64-bit indexable temps (and any other 64-bit declarations) the write
mask must not be converted.
 2024-03-27 22:36:55 +01:00
Conor McCarthy
83a67366da vkd3d-shader/spirv: Do not assert if a TGSM store data register is not UINT. 2024-03-27 22:36:54 +01:00
Conor McCarthy
9da375414e vkd3d-shader/spirv: Do not assert if a TGSM load dst register is not UINT. 2024-03-27 22:36:52 +01:00
Henri Verbeet
5de5f241a6 vkd3d-shader/ir: Pass a struct vsir_program to vkd3d_shader_normalise(). 2024-03-19 22:57:56 +01:00
Conor McCarthy
421d311a49 vkd3d-shader/spirv: Use dst register data type in spirv_compiler_emit_imad(). 2024-03-18 23:07:36 +01:00
Conor McCarthy
b22632ff1a vkd3d-shader/spirv: Emit a trace message if TGSM alignment is ignored. 
This would cause a lot of warning spam if it was a warning.
 2024-03-14 22:48:45 +01:00
Conor McCarthy
6dd54eeb09 vkd3d-shader/spirv: Support zero-initialisation for workgroup memory. 2024-03-14 22:48:41 +01:00
Conor McCarthy
0dc174ebd7 vkd3d-shader/spirv: Emit an error if a FIRSTBIT instruction has a 64-bit source. 2024-03-13 21:50:37 +01:00
Conor McCarthy
a64eb75c1d vkd3d-shader/spirv: Emit an error if COUNTBITS has a 64-bit source. 2024-03-13 21:50:36 +01:00
Conor McCarthy
066ea75945 vkd3d-shader/spirv: Introduce HALF and UINT16 types for minimum precision. 
Minimum precision types must always be implemented as 32-bit to match how
reduced precision works in SPIR-V.
 2024-03-11 22:10:05 +01:00
Conor McCarthy
58123c2e10 vkd3d-shader/spirv: Introduce a data_type_is_floating_point() helper function. 2024-03-11 22:10:03 +01:00
Zebediah Figura
ad495970e0 vkd3d-shader/spirv: Implement SLT and SGE. 2024-03-11 22:09:48 +01:00
Zebediah Figura
27196d8b0f vkd3d-shader/spirv: Implement CMP. 2024-03-11 22:09:44 +01:00
Giovanni Mascellani
470d83a9da vkd3d-shader: Move shader signatures to vsir_program. 2024-03-11 22:09:31 +01:00
Evan Tang
4553b2a0dc vkd3d-shader/spirv: Implement support for rasteriser-ordered views. 
Using SPV_EXT_fragment_shader_interlock.
 2024-03-08 23:36:35 +01:00
Conor McCarthy
e65055b435 vkd3d-shader/spirv: Handle the ORD and UNO instructions. 2024-03-08 23:36:14 +01:00
Conor McCarthy
5082893e5d vkd3d-shader/spirv: Always use a 64-bit write mask for IMMCONST64 src params. 
There is no way to tell in spirv_compiler_emit_load_reg() if the write
mask is 64-bit. All loads are 32-bit except for IMMCONST64 and SSA, and
the latter ignores the mask, so the only issue lies with IMMCONST64.
 2024-03-06 23:04:12 +01:00
Henri Verbeet
f866fb95ad Release 1.11. 2024-03-05 20:39:45 +01:00
Conor McCarthy
625e289574 vkd3d-shader/dxil: Handle hyperbolic trigonometric functions in sm6_parser_emit_dx_unary(). 2024-02-07 22:59:23 +01:00
Conor McCarthy
7f87a3e5fc vkd3d-shader/spirv: Handle the ACOS, ASIN and ATAN instructions in spirv_compiler_emit_ext_glsl_instruction(). 2024-02-06 23:09:55 +01:00
Giovanni Mascellani
eb723a8d2b vkd3d-shader/spirv: Support bool TEMP registers. 2024-02-06 23:06:58 +01:00
Giovanni Mascellani
49f0fd42b8 vkd3d-shader/spirv: Move bool casting helpers above register loading helpers. 2024-02-06 23:06:55 +01:00
Giovanni Mascellani
ee994e95dd vkd3d-shader/spirv: Convert the swizzle according to the source bit width. 
Fixes: 1f536238a8
 2024-02-06 23:06:53 +01:00
Conor McCarthy
95e4222cc6 vkd3d-shader/spirv: Emit a vector bitcast if necessary in spirv_compiler_emit_load_ssa_reg(). 2024-02-01 22:25:04 +01:00
Conor McCarthy
ebec0aa434 vkd3d-shader/dxil: Implement DX intrinsic TextureLoad. 2024-02-01 22:25:02 +01:00
Giovanni Mascellani
cc72a8d311 vkd3d-shader/spirv: Free binary SPIR-V code (Valgrind). 2024-02-01 00:08:28 +01:00
Giovanni Mascellani
1f536238a8 vkd3d-shader: Use 64 bit swizzles for 64 bit data types in VSIR. 
The handling of write masks and swizzles for 64 bit data types is
currently irregular: write masks are always 64 bit, while swizzles
are usually 32 bit, except for SSA registers with are 64 bit.
With this change we always use 64 bit swizzles, in order to make
the situation less surprising and make it easier to convert
registers between SSA and TEMP.

64 bit swizzles are always required to have X in their last two
components.
 2024-01-29 22:33:33 +01:00
Conor McCarthy
92f0b37133 vkd3d-shader/spirv: Support 64-bit source value for bitfield instructions. 2024-01-29 22:33:22 +01:00
Giovanni Mascellani
378109051c vkd3d-shader/ir: Lower monolithic switches to selection ladders. 
PHI nodes must be fixed up after this pass, because the block references
might have become broken. For simplicitly this is not handled yet.

The goal for this pass is to make the CFG structurizer simpler, because
only conditional and unconditional branches must be supported.
Eventually this limitation might be lifted if there is advantage in
doing so.
 2024-01-29 22:33:15 +01:00
Giovanni Mascellani
b97edee03d vkd3d-shader/spirv: Emit an error if merge information is missing. 
Instead of crashing.
 2024-01-29 22:33:14 +01:00
Conor McCarthy
f954724870 vkd3d-shader/spirv: Handle the TAN instruction in spirv_compiler_emit_ext_glsl_instruction(). 2024-01-25 22:24:44 +01:00
Conor McCarthy
8ae69c745b vkd3d-shader/spirv: Handle thread group UAV barriers. 2024-01-25 22:24:23 +01:00
Conor McCarthy
18e9148f58 vkd3d-shader/spirv: Include Uniform in the memory semantics for UAV barriers. 
The UniformMemory semantic applies the constraints to Uniform storage
class memory, which matches how UAV variables are declared.
 2024-01-25 22:24:22 +01:00
Conor McCarthy
adfbecef3c vkd3d-shader/spirv: Handle globally coherent UAVs. 2024-01-25 22:24:20 +01:00
Conor McCarthy
54f6e6dd67 vkd3d-shader/spirv: Check for FEATURE_FLOAT64 when double precision use is flagged. 2024-01-24 22:38:09 +01:00
Conor McCarthy
e973271a40 vkd3d-shader/spirv: Handle the ISINF and ISNAN instructions in spirv_compiler_emit_alu_instruction(). 2024-01-24 22:38:04 +01:00
Conor McCarthy
cd674d593e vkd3d-shader/spirv: Implement the ISFINITE instruction. 2024-01-24 22:38:03 +01:00
Francisco Casas
b92f6c448a vkd3d-shader/ir: Lower texkill instructions to discard_nz. 2024-01-24 22:37:41 +01:00
Henri Verbeet
bf628f0c74 vkd3d-shader/ir: Store block names in struct vsir_program. 2024-01-23 20:27:35 +01:00
Henri Verbeet
f3c7d2d05c vkd3d-shader/ir: Store the block count in struct vsir_program. 2024-01-23 20:27:34 +01:00
Henri Verbeet
98c6e85b33 vkd3d-shader/ir: Store control point counts in struct vsir_program. 2024-01-23 20:27:32 +01:00
Conor McCarthy
e4660fe0e6 vkd3d-shader/spirv: Emit DISCARD as a function call. 2024-01-23 20:26:59 +01:00
Giovanni Mascellani
de9725b6ba vkd3d-shader/ir: Remove DCL_TEMPS instructions. 
We have to do work to keep it updated across passes and we never read it.
 2024-01-23 20:26:38 +01:00
Giovanni Mascellani
45495f54f2 vkd3d-shader/spirv: Use capability ShaderViewportIndexLayerEXT for decoration ViewportIndex. 2024-01-22 22:19:11 +01:00
Giovanni Mascellani
6ac525d6c3 vkd3d-shader/spirv: Use capability ShaderViewportIndexLayerEXT for decoration Layer. 
Capability Geometry allows to use the Layer builtin in geometry and pixel
shaders. For vertex and domain shaders ShaderLayer should be used, but it's only
available starting from SPIR-V 1.5. ShaderViewportIndexLayerEXT can be used
instead with extension SPV_EXT_shader_viewport_index_layer.
 2024-01-22 22:19:09 +01:00
Henri Verbeet
adc02eada8 vkd3d-shader/ir: Store the temporary register count in struct vsir_program. 2024-01-22 22:18:53 +01:00
Henri Verbeet
94ca46916a vkd3d-shader/ir: Store the SSA register count in struct vsir_program. 2024-01-22 22:18:52 +01:00
Henri Verbeet
7b85cd6a31 vkd3d-shader/ir: Store the "use_vocp" field in struct vsir_program. 2024-01-22 22:18:51 +01:00
Henri Verbeet
23dcd4f22b vkd3d-shader/ir: Store the shader version in struct vsir_program. 2024-01-22 22:18:50 +01:00
Henri Verbeet
fc9043be3c vkd3d-shader/ir: Introduce struct vsir_program. 2024-01-22 22:18:48 +01:00
Conor McCarthy
ca7487a56d vkd3d-shader/spirv: Handle UINT32_MAX result from FIRSTBIT_HI and FIRSTBIT_SHI instructions. 2024-01-22 22:18:27 +01:00
Conor McCarthy
5ebe0cc717 vkd3d-shader/spirv: Do not assert VKD3D_DATA_UINT in spirv_compiler_emit_ld_raw_structured_srv_uav(). 2024-01-22 22:18:17 +01:00
Giovanni Mascellani
1d45b7a422 vkd3d-shader/spirv: Normalise the shader before allocating registers. 
So registers are allocated after normalisation (which could require
additional registers).
 2024-01-18 23:15:48 +01:00
Conor McCarthy
ba1ee27b4b vkd3d-shader/dxil: Handle the DXIL PHI instruction. 2024-01-18 23:15:12 +01:00
Conor McCarthy
4c30b23821 vkd3d-shader: Make the control point count the outer dimension of I/O arrays. 
The relative-addressed case in shader_register_normalise_arrayed_addressing()
leaves the control point id in idx[0], while for constant register
indices it is placed in idx[1]. The latter case could be fixed instead,
but placing the control point count in the outer dimension is more
logical.
 2024-01-17 22:28:59 +01:00
Conor McCarthy
559d9d4ee0 vkd3d-shader/ir: Include an initial label instruction in the first control flow block. 2024-01-17 22:28:41 +01:00
Conor McCarthy
d402804851 vkd3d-shader/spirv: Do not emit function code before the main prolog. 2024-01-17 22:28:40 +01:00
Conor McCarthy
b4b2b0d3ac vkd3d-shader/spirv: Declare indexable temps as Private unless function scope is specified. 2024-01-17 22:28:39 +01:00
Conor McCarthy
37d9dba512 vkd3d-shader/ir: Store code block names in struct vkd3d_shader_desc. 2024-01-17 22:28:38 +01:00
Conor McCarthy
ffc65215ba vkd3d-shader/ir: Flatten SWITCH/CASE/DEFAULT/ENDSWITCH control flow instructions. 2024-01-17 22:28:36 +01:00
Conor McCarthy
dcb8527327 vkd3d-shader/ir: Flatten LOOP/BREAK/CONTINUE/ENDLOOP control flow instructions. 2024-01-17 22:28:35 +01:00
Conor McCarthy
e1dddc01b7 vkd3d-shader/ir: Flatten IF/ELSE/ENDIF control flow instructions. 2024-01-17 22:28:34 +01:00
Conor McCarthy
f3d464de0e vkd3d-shader/spirv: Handle RETP in spirv_compiler_handle_instruction(). 2024-01-17 22:28:33 +01:00
Conor McCarthy
bc1b5e7132 vkd3d-shader/spirv: Handle DISCARD and TEXKILL in spirv_compiler_handle_instruction(). 2024-01-17 22:28:31 +01:00
Conor McCarthy
db0d51675c vkd3d-shader/spirv: Emit descriptor offset loads in the function entry block. 
Ensures they are loaded only once per function independent of the
control flow graph.
 2024-01-17 22:28:29 +01:00
Conor McCarthy
52902b042f vkd3d-shader/spirv: Support vector source param for FIRSTBIT_HI and FIRSTBIT_SHI instructions. 2024-01-15 19:56:35 +01:00
Henri Verbeet
fd8a0d7fb6 vkd3d-shader/spirv: Pass a uint32_t write mask to spirv_compiler_emit_neg(). 2024-01-11 23:05:03 +01:00
Henri Verbeet
b4da553d28 vkd3d-shader/spirv: Pass a uint32_t write mask to spirv_compiler_emit_abs(). 2024-01-11 23:05:02 +01:00
Henri Verbeet
97acca715e vkd3d-shader/spirv: Pass a uin32_t write mask to spirv_compiler_emit_load_src(). 2024-01-11 23:05:01 +01:00
Henri Verbeet
5c2d0f42b5 vkd3d-shader/spirv: Pass a uint32_t write mask to vkd3d_symbol_set_register_info(). 2024-01-11 23:05:00 +01:00
Giovanni Mascellani
7f9803620f vkd3d-shader/spirv: Specify behavior for bit field instructions. 
Bit field instructions in SPIR-V do not specify what happens when
offset + count exceeds the type bit width. After this commit we
refine the emitted code's behavior to match TPF.

This fixes a few failures on MoltenVK.
 2024-01-08 21:44:52 +01:00
Henri Verbeet
60842b7181 vkd3d-shader/ir: Store source parameter swizzles as a uint32_t. 2024-01-04 22:23:51 +01:00
Henri Verbeet
9f4ca3bc9c vkd3d-shader/ir: Store instruction flags as a uint32_t. 2024-01-04 22:23:49 +01:00
Henri Verbeet
7f94fda05c vkd3d-shader/ir: Rename the "immconst_uint64" field of struct vkd3d_shader_register to "immconst_u64". 2024-01-03 22:37:43 +01:00