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vkd3d/libs/vkd3d-shader/ir.c

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vkd3d-shader/ir: Merge all shader IR fork and join phases into a single phase. Normalise the incoming vkd3d_shader_instruction IR to the shader model 6 pattern. This allows generation of a single patch constant function in SPIR-V.
2023-02-28 17:59:28 -08:00
/*
* Copyright 2023 Conor McCarthy for CodeWeavers
*
* This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU Lesser General Public
* License as published by the Free Software Foundation; either
* version 2.1 of the License, or (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public
* License along with this library; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA
*/
#include "vkd3d_shader_private.h"
vkd3d-shader/ir: Store the shader version in struct vsir_program.
2024-01-16 07:40:30 -08:00
bool vsir_program_init(struct vsir_program *program, const struct vkd3d_shader_version *version, unsigned int reserve)
vkd3d-shader/ir: Introduce struct vsir_program.
2024-01-16 05:47:34 -08:00
{
vkd3d-shader/ir: Store the shader version in struct vsir_program.
2024-01-16 07:40:30 -08:00
program->shader_version = *version;
vkd3d-shader/ir: Introduce struct vsir_program.
2024-01-16 05:47:34 -08:00
return shader_instruction_array_init(&program->instructions, reserve);
}
void vsir_program_cleanup(struct vsir_program *program)
{
shader_instruction_array_destroy(&program->instructions);
}
vkd3d-shader/ir: Merge all shader IR fork and join phases into a single phase. Normalise the incoming vkd3d_shader_instruction IR to the shader model 6 pattern. This allows generation of a single patch constant function in SPIR-V.
2023-02-28 17:59:28 -08:00
static inline bool shader_register_is_phase_instance_id(const struct vkd3d_shader_register *reg)
{
return reg->type == VKD3DSPR_FORKINSTID || reg->type == VKD3DSPR_JOININSTID;
}
static bool shader_instruction_is_dcl(const struct vkd3d_shader_instruction *ins)
{
return (VKD3DSIH_DCL <= ins->handler_idx && ins->handler_idx <= VKD3DSIH_DCL_VERTICES_OUT)
|| ins->handler_idx == VKD3DSIH_HS_DECLS;
}
static void vkd3d_shader_instruction_make_nop(struct vkd3d_shader_instruction *ins)
{
vkd3d-shader: Embed the parsing location in vkd3d_shader_instruction. So that it can be used for printing meaningful error locations by downstream processors.
2023-09-05 02:31:31 -07:00
struct vkd3d_shader_location location = ins->location;
vsir_instruction_init(ins, &location, VKD3DSIH_NOP);
vkd3d-shader/ir: Merge all shader IR fork and join phases into a single phase. Normalise the incoming vkd3d_shader_instruction IR to the shader model 6 pattern. This allows generation of a single patch constant function in SPIR-V.
2023-02-28 17:59:28 -08:00
}
static void shader_register_eliminate_phase_addressing(struct vkd3d_shader_register *reg,
unsigned int instance_id)
{
unsigned int i;
vkd3d-shader/tpf: Validate input/output register index counts.
2023-05-03 00:10:37 -07:00
for (i = 0; i < reg->idx_count; ++i)
vkd3d-shader/ir: Merge all shader IR fork and join phases into a single phase. Normalise the incoming vkd3d_shader_instruction IR to the shader model 6 pattern. This allows generation of a single patch constant function in SPIR-V.
2023-02-28 17:59:28 -08:00
{
if (reg->idx[i].rel_addr && shader_register_is_phase_instance_id(&reg->idx[i].rel_addr->reg))
{
reg->idx[i].rel_addr = NULL;
reg->idx[i].offset += instance_id;
}
}
}
static void shader_instruction_eliminate_phase_instance_id(struct vkd3d_shader_instruction *ins,
unsigned int instance_id)
{
struct vkd3d_shader_register *reg;
unsigned int i;
for (i = 0; i < ins->src_count; ++i)
{
reg = (struct vkd3d_shader_register *)&ins->src[i].reg;
if (shader_register_is_phase_instance_id(reg))
{
vkd3d-shader/ir: Use vsir_register_init() to initialize a register.
2023-11-08 02:11:39 -08:00
vsir_register_init(reg, VKD3DSPR_IMMCONST, reg->data_type, 0);
vkd3d-shader/ir: Rename the "immconst_uint" field of struct vkd3d_shader_register to "immconst_u32". For consistency with the rest of vkd3d-shader; e.g. put_u32() and read_u32().
2023-12-05 14:24:36 -08:00
reg->u.immconst_u32[0] = instance_id;
vkd3d-shader/ir: Merge all shader IR fork and join phases into a single phase. Normalise the incoming vkd3d_shader_instruction IR to the shader model 6 pattern. This allows generation of a single patch constant function in SPIR-V.
2023-02-28 17:59:28 -08:00
continue;
}
shader_register_eliminate_phase_addressing(reg, instance_id);
}
for (i = 0; i < ins->dst_count; ++i)
shader_register_eliminate_phase_addressing((struct vkd3d_shader_register *)&ins->dst[i].reg, instance_id);
}
vkd3d-shader: Implement remapping shader output registers to match the next shader's semantics.
2023-07-20 19:52:25 -07:00
static const struct vkd3d_shader_varying_map *find_varying_map(
vkd3d-shader: Rename vkd3d_shader_next_stage_info to vkd3d_shader_varying_map_info. It was originally intended that this structure could hold other information about the next stage which compilation might depend on. For example, compilation to GLSL needs to know the type of the next shader in some circumstances. That was never actualized, and since the API is fixed at this point for 1.9, it makes the most sense to rename the structure to match its actual scope. The documentation was written and arranged to imply that the structure would hold other information about the next shader than the varying map; this is changed accordingly as well.
2023-09-19 14:04:53 -07:00
const struct vkd3d_shader_varying_map_info *varying_map, unsigned int signature_idx)
vkd3d-shader: Implement remapping shader output registers to match the next shader's semantics.
2023-07-20 19:52:25 -07:00
{
unsigned int i;
vkd3d-shader: Rename vkd3d_shader_next_stage_info to vkd3d_shader_varying_map_info. It was originally intended that this structure could hold other information about the next stage which compilation might depend on. For example, compilation to GLSL needs to know the type of the next shader in some circumstances. That was never actualized, and since the API is fixed at this point for 1.9, it makes the most sense to rename the structure to match its actual scope. The documentation was written and arranged to imply that the structure would hold other information about the next shader than the varying map; this is changed accordingly as well.
2023-09-19 14:04:53 -07:00
for (i = 0; i < varying_map->varying_count; ++i)
vkd3d-shader: Implement remapping shader output registers to match the next shader's semantics.
2023-07-20 19:52:25 -07:00
{
vkd3d-shader: Rename vkd3d_shader_next_stage_info to vkd3d_shader_varying_map_info. It was originally intended that this structure could hold other information about the next stage which compilation might depend on. For example, compilation to GLSL needs to know the type of the next shader in some circumstances. That was never actualized, and since the API is fixed at this point for 1.9, it makes the most sense to rename the structure to match its actual scope. The documentation was written and arranged to imply that the structure would hold other information about the next shader than the varying map; this is changed accordingly as well.
2023-09-19 14:04:53 -07:00
if (varying_map->varying_map[i].output_signature_index == signature_idx)
return &varying_map->varying_map[i];
vkd3d-shader: Implement remapping shader output registers to match the next shader's semantics.
2023-07-20 19:52:25 -07:00
}
return NULL;
}
static enum vkd3d_result remap_output_signature(struct vkd3d_shader_parser *parser,
const struct vkd3d_shader_compile_info *compile_info)
{
struct shader_signature *signature = &parser->shader_desc.output_signature;
vkd3d-shader: Rename vkd3d_shader_next_stage_info to vkd3d_shader_varying_map_info. It was originally intended that this structure could hold other information about the next stage which compilation might depend on. For example, compilation to GLSL needs to know the type of the next shader in some circumstances. That was never actualized, and since the API is fixed at this point for 1.9, it makes the most sense to rename the structure to match its actual scope. The documentation was written and arranged to imply that the structure would hold other information about the next shader than the varying map; this is changed accordingly as well.
2023-09-19 14:04:53 -07:00
const struct vkd3d_shader_varying_map_info *varying_map;
vkd3d-shader: Implement remapping shader output registers to match the next shader's semantics.
2023-07-20 19:52:25 -07:00
unsigned int i;
vkd3d-shader: Rename vkd3d_shader_next_stage_info to vkd3d_shader_varying_map_info. It was originally intended that this structure could hold other information about the next stage which compilation might depend on. For example, compilation to GLSL needs to know the type of the next shader in some circumstances. That was never actualized, and since the API is fixed at this point for 1.9, it makes the most sense to rename the structure to match its actual scope. The documentation was written and arranged to imply that the structure would hold other information about the next shader than the varying map; this is changed accordingly as well.
2023-09-19 14:04:53 -07:00
if (!(varying_map = vkd3d_find_struct(compile_info->next, VARYING_MAP_INFO)))
vkd3d-shader: Implement remapping shader output registers to match the next shader's semantics.
2023-07-20 19:52:25 -07:00
return VKD3D_OK;
for (i = 0; i < signature->element_count; ++i)
{
vkd3d-shader: Rename vkd3d_shader_next_stage_info to vkd3d_shader_varying_map_info. It was originally intended that this structure could hold other information about the next stage which compilation might depend on. For example, compilation to GLSL needs to know the type of the next shader in some circumstances. That was never actualized, and since the API is fixed at this point for 1.9, it makes the most sense to rename the structure to match its actual scope. The documentation was written and arranged to imply that the structure would hold other information about the next shader than the varying map; this is changed accordingly as well.
2023-09-19 14:04:53 -07:00
const struct vkd3d_shader_varying_map *map = find_varying_map(varying_map, i);
vkd3d-shader: Implement remapping shader output registers to match the next shader's semantics.
2023-07-20 19:52:25 -07:00
struct signature_element *e = &signature->elements[i];
if (map)
{
unsigned int input_mask = map->input_mask;
e->target_location = map->input_register_index;
/* It is illegal in Vulkan if the next shader uses the same varying
* location with a different mask. */
if (input_mask && input_mask != e->mask)
{
vkd3d_shader_parser_error(parser, VKD3D_SHADER_ERROR_VSIR_NOT_IMPLEMENTED,
"Aborting due to not yet implemented feature: "
"Output mask %#x does not match input mask %#x.",
e->mask, input_mask);
return VKD3D_ERROR_NOT_IMPLEMENTED;
}
}
else
{
vkd3d-shader/spirv: Make output varyings not consumed by the next stage private variables.
2023-07-31 10:46:55 -07:00
e->target_location = SIGNATURE_TARGET_LOCATION_UNUSED;
vkd3d-shader: Implement remapping shader output registers to match the next shader's semantics.
2023-07-20 19:52:25 -07:00
}
}
vkd3d-shader: Rename vkd3d_shader_next_stage_info to vkd3d_shader_varying_map_info. It was originally intended that this structure could hold other information about the next stage which compilation might depend on. For example, compilation to GLSL needs to know the type of the next shader in some circumstances. That was never actualized, and since the API is fixed at this point for 1.9, it makes the most sense to rename the structure to match its actual scope. The documentation was written and arranged to imply that the structure would hold other information about the next shader than the varying map; this is changed accordingly as well.
2023-09-19 14:04:53 -07:00
for (i = 0; i < varying_map->varying_count; ++i)
vkd3d-shader: Implement remapping shader output registers to match the next shader's semantics.
2023-07-20 19:52:25 -07:00
{
vkd3d-shader: Rename vkd3d_shader_next_stage_info to vkd3d_shader_varying_map_info. It was originally intended that this structure could hold other information about the next stage which compilation might depend on. For example, compilation to GLSL needs to know the type of the next shader in some circumstances. That was never actualized, and since the API is fixed at this point for 1.9, it makes the most sense to rename the structure to match its actual scope. The documentation was written and arranged to imply that the structure would hold other information about the next shader than the varying map; this is changed accordingly as well.
2023-09-19 14:04:53 -07:00
if (varying_map->varying_map[i].output_signature_index >= signature->element_count)
vkd3d-shader: Implement remapping shader output registers to match the next shader's semantics.
2023-07-20 19:52:25 -07:00
{
vkd3d_shader_parser_error(parser, VKD3D_SHADER_ERROR_VSIR_NOT_IMPLEMENTED,
"Aborting due to not yet implemented feature: "
"The next stage consumes varyings not written by this stage.");
return VKD3D_ERROR_NOT_IMPLEMENTED;
}
}
return VKD3D_OK;
}
vkd3d-shader/ir: Eliminate struct vkd3d_shader_normaliser.
2023-05-05 00:23:56 -07:00
struct hull_flattener
vkd3d-shader/ir: Normalise control point phase output registers to include the control point id. In SPIR-V the address must include the invocation id, but in TPF it is implicit. Move the register index up one slot and insert an OUTPOINTID relative address.
2023-04-04 00:55:05 -07:00
{
vkd3d-shader/ir: Eliminate struct vkd3d_shader_normaliser.
2023-05-05 00:23:56 -07:00
struct vkd3d_shader_instruction_array instructions;
unsigned int max_temp_count;
unsigned int temp_dcl_idx;
unsigned int instance_count;
unsigned int phase_body_idx;
enum vkd3d_shader_opcode phase;
vkd3d-shader: Embed the parsing location in vkd3d_shader_instruction. So that it can be used for printing meaningful error locations by downstream processors.
2023-09-05 02:31:31 -07:00
struct vkd3d_shader_location last_ret_location;
vkd3d-shader/ir: Eliminate struct vkd3d_shader_normaliser.
2023-05-05 00:23:56 -07:00
};
vkd3d-shader/ir: Normalise control point phase output registers to include the control point id. In SPIR-V the address must include the invocation id, but in TPF it is implicit. Move the register index up one slot and insert an OUTPOINTID relative address.
2023-04-04 00:55:05 -07:00
vkd3d-shader/ir: Eliminate struct vkd3d_shader_normaliser.
2023-05-05 00:23:56 -07:00
static bool flattener_is_in_fork_or_join_phase(const struct hull_flattener *flattener)
vkd3d-shader/ir: Merge all shader IR fork and join phases into a single phase. Normalise the incoming vkd3d_shader_instruction IR to the shader model 6 pattern. This allows generation of a single patch constant function in SPIR-V.
2023-02-28 17:59:28 -08:00
{
vkd3d-shader/ir: Eliminate struct vkd3d_shader_normaliser.
2023-05-05 00:23:56 -07:00
return flattener->phase == VKD3DSIH_HS_FORK_PHASE || flattener->phase == VKD3DSIH_HS_JOIN_PHASE;
vkd3d-shader/ir: Merge all shader IR fork and join phases into a single phase. Normalise the incoming vkd3d_shader_instruction IR to the shader model 6 pattern. This allows generation of a single patch constant function in SPIR-V.
2023-02-28 17:59:28 -08:00
}
struct shader_phase_location
{
unsigned int index;
unsigned int instance_count;
unsigned int instruction_count;
};
struct shader_phase_location_array
{
/* Unlikely worst case: one phase for each component of each output register. */
struct shader_phase_location locations[MAX_REG_OUTPUT * VKD3D_VEC4_SIZE];
unsigned int count;
};
vkd3d-shader/ir: Eliminate struct vkd3d_shader_normaliser.
2023-05-05 00:23:56 -07:00
static void flattener_eliminate_phase_related_dcls(struct hull_flattener *normaliser,
vkd3d-shader/ir: Merge all shader IR fork and join phases into a single phase. Normalise the incoming vkd3d_shader_instruction IR to the shader model 6 pattern. This allows generation of a single patch constant function in SPIR-V.
2023-02-28 17:59:28 -08:00
unsigned int index, struct shader_phase_location_array *locations)
{
struct vkd3d_shader_instruction *ins = &normaliser->instructions.elements[index];
struct shader_phase_location *loc;
bool b;
if (ins->handler_idx == VKD3DSIH_HS_FORK_PHASE || ins->handler_idx == VKD3DSIH_HS_JOIN_PHASE)
{
vkd3d-shader/ir: Eliminate struct vkd3d_shader_normaliser.
2023-05-05 00:23:56 -07:00
b = flattener_is_in_fork_or_join_phase(normaliser);
vkd3d-shader/ir: Merge all shader IR fork and join phases into a single phase. Normalise the incoming vkd3d_shader_instruction IR to the shader model 6 pattern. This allows generation of a single patch constant function in SPIR-V.
2023-02-28 17:59:28 -08:00
/* Reset the phase info. */
normaliser->phase_body_idx = ~0u;
normaliser->phase = ins->handler_idx;
normaliser->instance_count = 1;
/* Leave the first occurrence and delete the rest. */
if (b)
vkd3d_shader_instruction_make_nop(ins);
return;
}
else if (ins->handler_idx == VKD3DSIH_DCL_HS_FORK_PHASE_INSTANCE_COUNT
|| ins->handler_idx == VKD3DSIH_DCL_HS_JOIN_PHASE_INSTANCE_COUNT)
{
normaliser->instance_count = ins->declaration.count + !ins->declaration.count;
vkd3d_shader_instruction_make_nop(ins);
return;
}
else if (ins->handler_idx == VKD3DSIH_DCL_INPUT && shader_register_is_phase_instance_id(
&ins->declaration.dst.reg))
{
vkd3d_shader_instruction_make_nop(ins);
return;
}
else if (ins->handler_idx == VKD3DSIH_DCL_TEMPS && normaliser->phase != VKD3DSIH_INVALID)
{
/* Leave only the first temp declaration and set it to the max count later. */
if (!normaliser->max_temp_count)
vkd3d-shader/ir: Correctly compute the TEMP count after hull shader flattening. The previous computation was incorrect because the count was taken after resetting it to zero (as part of setting the instruction to NOP).
2023-11-16 14:07:27 -08:00
{
normaliser->max_temp_count = ins->declaration.count;
vkd3d-shader/ir: Merge all shader IR fork and join phases into a single phase. Normalise the incoming vkd3d_shader_instruction IR to the shader model 6 pattern. This allows generation of a single patch constant function in SPIR-V.
2023-02-28 17:59:28 -08:00
normaliser->temp_dcl_idx = index;
vkd3d-shader/ir: Correctly compute the TEMP count after hull shader flattening. The previous computation was incorrect because the count was taken after resetting it to zero (as part of setting the instruction to NOP).
2023-11-16 14:07:27 -08:00
}
vkd3d-shader/ir: Merge all shader IR fork and join phases into a single phase. Normalise the incoming vkd3d_shader_instruction IR to the shader model 6 pattern. This allows generation of a single patch constant function in SPIR-V.
2023-02-28 17:59:28 -08:00
else
vkd3d-shader/ir: Correctly compute the TEMP count after hull shader flattening. The previous computation was incorrect because the count was taken after resetting it to zero (as part of setting the instruction to NOP).
2023-11-16 14:07:27 -08:00
{
normaliser->max_temp_count = max(normaliser->max_temp_count, ins->declaration.count);
vkd3d-shader/ir: Merge all shader IR fork and join phases into a single phase. Normalise the incoming vkd3d_shader_instruction IR to the shader model 6 pattern. This allows generation of a single patch constant function in SPIR-V.
2023-02-28 17:59:28 -08:00
vkd3d_shader_instruction_make_nop(ins);
vkd3d-shader/ir: Correctly compute the TEMP count after hull shader flattening. The previous computation was incorrect because the count was taken after resetting it to zero (as part of setting the instruction to NOP).
2023-11-16 14:07:27 -08:00
}
vkd3d-shader/ir: Merge all shader IR fork and join phases into a single phase. Normalise the incoming vkd3d_shader_instruction IR to the shader model 6 pattern. This allows generation of a single patch constant function in SPIR-V.
2023-02-28 17:59:28 -08:00
return;
}
if (normaliser->phase == VKD3DSIH_INVALID || shader_instruction_is_dcl(ins))
return;
if (normaliser->phase_body_idx == ~0u)
normaliser->phase_body_idx = index;
if (ins->handler_idx == VKD3DSIH_RET)
{
vkd3d-shader: Embed the parsing location in vkd3d_shader_instruction. So that it can be used for printing meaningful error locations by downstream processors.
2023-09-05 02:31:31 -07:00
normaliser->last_ret_location = ins->location;
vkd3d-shader/ir: Merge all shader IR fork and join phases into a single phase. Normalise the incoming vkd3d_shader_instruction IR to the shader model 6 pattern. This allows generation of a single patch constant function in SPIR-V.
2023-02-28 17:59:28 -08:00
vkd3d_shader_instruction_make_nop(ins);
if (locations->count >= ARRAY_SIZE(locations->locations))
{
FIXME("Insufficient space for phase location.\n");
return;
}
loc = &locations->locations[locations->count++];
loc->index = normaliser->phase_body_idx;
loc->instance_count = normaliser->instance_count;
loc->instruction_count = index - normaliser->phase_body_idx;
}
}
vkd3d-shader/ir: Eliminate struct vkd3d_shader_normaliser.
2023-05-05 00:23:56 -07:00
static enum vkd3d_result flattener_flatten_phases(struct hull_flattener *normaliser,
vkd3d-shader/ir: Merge all shader IR fork and join phases into a single phase. Normalise the incoming vkd3d_shader_instruction IR to the shader model 6 pattern. This allows generation of a single patch constant function in SPIR-V.
2023-02-28 17:59:28 -08:00
struct shader_phase_location_array *locations)
{
struct shader_phase_location *loc;
unsigned int i, j, k, end, count;
for (i = 0, count = 0; i < locations->count; ++i)
count += (locations->locations[i].instance_count - 1) * locations->locations[i].instruction_count;
if (!shader_instruction_array_reserve(&normaliser->instructions, normaliser->instructions.count + count))
return VKD3D_ERROR_OUT_OF_MEMORY;
end = normaliser->instructions.count;
normaliser->instructions.count += count;
for (i = locations->count; i > 0; --i)
{
loc = &locations->locations[i - 1];
j = loc->index + loc->instruction_count;
memmove(&normaliser->instructions.elements[j + count], &normaliser->instructions.elements[j],
(end - j) * sizeof(*normaliser->instructions.elements));
end = j;
count -= (loc->instance_count - 1) * loc->instruction_count;
loc->index += count;
}
for (i = 0, count = 0; i < locations->count; ++i)
{
loc = &locations->locations[i];
/* Make a copy of the non-dcl instructions for each instance. */
for (j = 1; j < loc->instance_count; ++j)
{
for (k = 0; k < loc->instruction_count; ++k)
{
if (!shader_instruction_array_clone_instruction(&normaliser->instructions,
loc->index + loc->instruction_count * j + k, loc->index + k))
return VKD3D_ERROR_OUT_OF_MEMORY;
}
}
/* Replace each reference to the instance id with a constant instance id. */
for (j = 0; j < loc->instance_count; ++j)
{
for (k = 0; k < loc->instruction_count; ++k)
shader_instruction_eliminate_phase_instance_id(
&normaliser->instructions.elements[loc->index + loc->instruction_count * j + k], j);
}
}
return VKD3D_OK;
}
vkd3d-shader: Rename shader_register_init() to vsir_register_init().
2023-08-29 10:20:44 -07:00
void vsir_register_init(struct vkd3d_shader_register *reg, enum vkd3d_shader_register_type reg_type,
vkd3d-shader/tpf: Validate input/output register index counts.
2023-05-03 00:10:37 -07:00
enum vkd3d_data_type data_type, unsigned int idx_count)
vkd3d-shader/ir: Normalise control point phase output registers to include the control point id. In SPIR-V the address must include the invocation id, but in TPF it is implicit. Move the register index up one slot and insert an OUTPOINTID relative address.
2023-04-04 00:55:05 -07:00
{
reg->type = reg_type;
reg->precision = VKD3D_SHADER_REGISTER_PRECISION_DEFAULT;
reg->non_uniform = false;
reg->data_type = data_type;
reg->idx[0].offset = ~0u;
reg->idx[0].rel_addr = NULL;
vkd3d-shader/dxil: Implement the DXIL GEP instruction.
2023-11-12 22:52:45 -08:00
reg->idx[0].is_in_bounds = false;
vkd3d-shader/ir: Normalise control point phase output registers to include the control point id. In SPIR-V the address must include the invocation id, but in TPF it is implicit. Move the register index up one slot and insert an OUTPOINTID relative address.
2023-04-04 00:55:05 -07:00
reg->idx[1].offset = ~0u;
reg->idx[1].rel_addr = NULL;
vkd3d-shader/dxil: Implement the DXIL GEP instruction.
2023-11-12 22:52:45 -08:00
reg->idx[1].is_in_bounds = false;
vkd3d-shader/ir: Normalise control point phase output registers to include the control point id. In SPIR-V the address must include the invocation id, but in TPF it is implicit. Move the register index up one slot and insert an OUTPOINTID relative address.
2023-04-04 00:55:05 -07:00
reg->idx[2].offset = ~0u;
reg->idx[2].rel_addr = NULL;
vkd3d-shader/dxil: Implement the DXIL GEP instruction.
2023-11-12 22:52:45 -08:00
reg->idx[2].is_in_bounds = false;
vkd3d-shader/tpf: Validate input/output register index counts.
2023-05-03 00:10:37 -07:00
reg->idx_count = idx_count;
vkd3d-shader: Turn vkd3d_shader_register.immconst_type into vkd3d_shader_register.dimension.
2023-08-14 10:21:41 -07:00
reg->dimension = VSIR_DIMENSION_SCALAR;
vkd3d-shader/dxil: Implement the DXIL LOAD instruction.
2023-11-21 18:42:23 -08:00
reg->alignment = 0;
vkd3d-shader/ir: Normalise control point phase output registers to include the control point id. In SPIR-V the address must include the invocation id, but in TPF it is implicit. Move the register index up one slot and insert an OUTPOINTID relative address.
2023-04-04 00:55:05 -07:00
}
vkd3d-shader/dxil: Handle the DXIL SWITCH instruction.
2023-11-23 19:14:44 -08:00
void vsir_src_param_init(struct vkd3d_shader_src_param *param, enum vkd3d_shader_register_type reg_type,
vkd3d-shader/ir: Flatten IF/ELSE/ENDIF control flow instructions.
2024-01-04 06:55:51 -08:00
enum vkd3d_data_type data_type, unsigned int idx_count)
{
vsir_register_init(&param->reg, reg_type, data_type, idx_count);
param->swizzle = 0;
param->modifiers = VKD3DSPSM_NONE;
}
vkd3d-shader/ir: Include an initial label instruction in the first control flow block.
2024-01-11 19:20:32 -08:00
void vsir_src_param_init_label(struct vkd3d_shader_src_param *param, unsigned int label_id)
vkd3d-shader/ir: Flatten IF/ELSE/ENDIF control flow instructions.
2024-01-04 06:55:51 -08:00
{
vsir_src_param_init(param, VKD3DSPR_LABEL, VKD3D_DATA_UINT, 1);
param->reg.dimension = VSIR_DIMENSION_NONE;
param->reg.idx[0].offset = label_id;
}
vkd3d-shader: Embed the parsing location in vkd3d_shader_instruction. So that it can be used for printing meaningful error locations by downstream processors.
2023-09-05 02:31:31 -07:00
void vsir_instruction_init(struct vkd3d_shader_instruction *ins, const struct vkd3d_shader_location *location,
enum vkd3d_shader_opcode handler_idx)
vkd3d-shader/ir: Merge all shader IR fork and join phases into a single phase. Normalise the incoming vkd3d_shader_instruction IR to the shader model 6 pattern. This allows generation of a single patch constant function in SPIR-V.
2023-02-28 17:59:28 -08:00
{
memset(ins, 0, sizeof(*ins));
vkd3d-shader: Embed the parsing location in vkd3d_shader_instruction. So that it can be used for printing meaningful error locations by downstream processors.
2023-09-05 02:31:31 -07:00
ins->location = *location;
vkd3d-shader/ir: Merge all shader IR fork and join phases into a single phase. Normalise the incoming vkd3d_shader_instruction IR to the shader model 6 pattern. This allows generation of a single patch constant function in SPIR-V.
2023-02-28 17:59:28 -08:00
ins->handler_idx = handler_idx;
}
vkd3d-shader/ir: Flatten IF/ELSE/ENDIF control flow instructions.
2024-01-04 06:55:51 -08:00
static bool vsir_instruction_init_label(struct vkd3d_shader_instruction *ins, const struct vkd3d_shader_location *location,
unsigned int label_id, void *parser)
{
struct vkd3d_shader_src_param *src_param;
if (!(src_param = shader_parser_get_src_params(parser, 1)))
return false;
vsir_src_param_init_label(src_param, label_id);
vsir_instruction_init(ins, location, VKD3DSIH_LABEL);
ins->src = src_param;
ins->src_count = 1;
return true;
}
vkd3d-shader/ir: Move normalization code from spirv.c to ir.c. It is not spirv-specific and will (presumably) be used for GLSL as well.
2023-07-02 18:23:07 -07:00
static enum vkd3d_result instruction_array_flatten_hull_shader_phases(struct vkd3d_shader_instruction_array *src_instructions)
vkd3d-shader/ir: Merge all shader IR fork and join phases into a single phase. Normalise the incoming vkd3d_shader_instruction IR to the shader model 6 pattern. This allows generation of a single patch constant function in SPIR-V.
2023-02-28 17:59:28 -08:00
{
vkd3d-shader/ir: Eliminate struct vkd3d_shader_normaliser.
2023-05-05 00:23:56 -07:00
struct hull_flattener flattener = {*src_instructions};
struct vkd3d_shader_instruction_array *instructions;
vkd3d-shader/ir: Merge all shader IR fork and join phases into a single phase. Normalise the incoming vkd3d_shader_instruction IR to the shader model 6 pattern. This allows generation of a single patch constant function in SPIR-V.
2023-02-28 17:59:28 -08:00
struct shader_phase_location_array locations;
enum vkd3d_result result = VKD3D_OK;
unsigned int i;
vkd3d-shader/ir: Eliminate struct vkd3d_shader_normaliser.
2023-05-05 00:23:56 -07:00
instructions = &flattener.instructions;
flattener.phase = VKD3DSIH_INVALID;
vkd3d-shader/ir: Merge all shader IR fork and join phases into a single phase. Normalise the incoming vkd3d_shader_instruction IR to the shader model 6 pattern. This allows generation of a single patch constant function in SPIR-V.
2023-02-28 17:59:28 -08:00
for (i = 0, locations.count = 0; i < instructions->count; ++i)
vkd3d-shader/ir: Eliminate struct vkd3d_shader_normaliser.
2023-05-05 00:23:56 -07:00
flattener_eliminate_phase_related_dcls(&flattener, i, &locations);
vkd3d-shader/ir: Merge all shader IR fork and join phases into a single phase. Normalise the incoming vkd3d_shader_instruction IR to the shader model 6 pattern. This allows generation of a single patch constant function in SPIR-V.
2023-02-28 17:59:28 -08:00
vkd3d-shader/ir: Eliminate struct vkd3d_shader_normaliser.
2023-05-05 00:23:56 -07:00
if ((result = flattener_flatten_phases(&flattener, &locations)) < 0)
vkd3d-shader/ir: Merge all shader IR fork and join phases into a single phase. Normalise the incoming vkd3d_shader_instruction IR to the shader model 6 pattern. This allows generation of a single patch constant function in SPIR-V.
2023-02-28 17:59:28 -08:00
return result;
vkd3d-shader/ir: Eliminate struct vkd3d_shader_normaliser.
2023-05-05 00:23:56 -07:00
if (flattener.phase != VKD3DSIH_INVALID)
vkd3d-shader/ir: Merge all shader IR fork and join phases into a single phase. Normalise the incoming vkd3d_shader_instruction IR to the shader model 6 pattern. This allows generation of a single patch constant function in SPIR-V.
2023-02-28 17:59:28 -08:00
{
vkd3d-shader/ir: Eliminate struct vkd3d_shader_normaliser.
2023-05-05 00:23:56 -07:00
if (flattener.temp_dcl_idx)
instructions->elements[flattener.temp_dcl_idx].declaration.count = flattener.max_temp_count;
vkd3d-shader/ir: Merge all shader IR fork and join phases into a single phase. Normalise the incoming vkd3d_shader_instruction IR to the shader model 6 pattern. This allows generation of a single patch constant function in SPIR-V.
2023-02-28 17:59:28 -08:00
vkd3d-shader/ir: Eliminate struct vkd3d_shader_normaliser.
2023-05-05 00:23:56 -07:00
if (!shader_instruction_array_reserve(&flattener.instructions, flattener.instructions.count + 1))
vkd3d-shader/ir: Merge all shader IR fork and join phases into a single phase. Normalise the incoming vkd3d_shader_instruction IR to the shader model 6 pattern. This allows generation of a single patch constant function in SPIR-V.
2023-02-28 17:59:28 -08:00
return VKD3D_ERROR_OUT_OF_MEMORY;
vkd3d-shader: Embed the parsing location in vkd3d_shader_instruction. So that it can be used for printing meaningful error locations by downstream processors.
2023-09-05 02:31:31 -07:00
vsir_instruction_init(&instructions->elements[instructions->count++], &flattener.last_ret_location, VKD3DSIH_RET);
vkd3d-shader/ir: Merge all shader IR fork and join phases into a single phase. Normalise the incoming vkd3d_shader_instruction IR to the shader model 6 pattern. This allows generation of a single patch constant function in SPIR-V.
2023-02-28 17:59:28 -08:00
}
vkd3d-shader/ir: Eliminate struct vkd3d_shader_normaliser.
2023-05-05 00:23:56 -07:00
*src_instructions = flattener.instructions;
vkd3d-shader/ir: Merge all shader IR fork and join phases into a single phase. Normalise the incoming vkd3d_shader_instruction IR to the shader model 6 pattern. This allows generation of a single patch constant function in SPIR-V.
2023-02-28 17:59:28 -08:00
return result;
}
vkd3d-shader/ir: Eliminate struct vkd3d_shader_normaliser.
2023-05-05 00:23:56 -07:00
struct control_point_normaliser
{
struct vkd3d_shader_instruction_array instructions;
enum vkd3d_shader_opcode phase;
struct vkd3d_shader_src_param *outpointid_param;
};
static bool control_point_normaliser_is_in_control_point_phase(const struct control_point_normaliser *normaliser)
{
return normaliser->phase == VKD3DSIH_HS_CONTROL_POINT_PHASE;
}
static struct vkd3d_shader_src_param *instruction_array_create_outpointid_param(
struct vkd3d_shader_instruction_array *instructions)
vkd3d-shader/ir: Normalise control point phase output registers to include the control point id. In SPIR-V the address must include the invocation id, but in TPF it is implicit. Move the register index up one slot and insert an OUTPOINTID relative address.
2023-04-04 00:55:05 -07:00
{
struct vkd3d_shader_src_param *rel_addr;
vkd3d-shader/ir: Eliminate struct vkd3d_shader_normaliser.
2023-05-05 00:23:56 -07:00
if (!(rel_addr = shader_src_param_allocator_get(&instructions->src_params, 1)))
vkd3d-shader/ir: Normalise control point phase output registers to include the control point id. In SPIR-V the address must include the invocation id, but in TPF it is implicit. Move the register index up one slot and insert an OUTPOINTID relative address.
2023-04-04 00:55:05 -07:00
return NULL;
vkd3d-shader: Rename shader_register_init() to vsir_register_init().
2023-08-29 10:20:44 -07:00
vsir_register_init(&rel_addr->reg, VKD3DSPR_OUTPOINTID, VKD3D_DATA_UINT, 0);
vkd3d-shader/ir: Normalise control point phase output registers to include the control point id. In SPIR-V the address must include the invocation id, but in TPF it is implicit. Move the register index up one slot and insert an OUTPOINTID relative address.
2023-04-04 00:55:05 -07:00
rel_addr->swizzle = 0;
rel_addr->modifiers = 0;
return rel_addr;
}
vkd3d-shader/tpf: Validate input/output register index counts.
2023-05-03 00:10:37 -07:00
static void shader_dst_param_normalise_outpointid(struct vkd3d_shader_dst_param *dst_param,
vkd3d-shader/ir: Eliminate struct vkd3d_shader_normaliser.
2023-05-05 00:23:56 -07:00
struct control_point_normaliser *normaliser)
vkd3d-shader/ir: Normalise control point phase output registers to include the control point id. In SPIR-V the address must include the invocation id, but in TPF it is implicit. Move the register index up one slot and insert an OUTPOINTID relative address.
2023-04-04 00:55:05 -07:00
{
struct vkd3d_shader_register *reg = &dst_param->reg;
vkd3d-shader/ir: Eliminate struct vkd3d_shader_normaliser.
2023-05-05 00:23:56 -07:00
if (control_point_normaliser_is_in_control_point_phase(normaliser) && reg->type == VKD3DSPR_OUTPUT)
vkd3d-shader/ir: Normalise control point phase output registers to include the control point id. In SPIR-V the address must include the invocation id, but in TPF it is implicit. Move the register index up one slot and insert an OUTPOINTID relative address.
2023-04-04 00:55:05 -07:00
{
vkd3d-shader/tpf: Validate input/output register index counts.
2023-05-03 00:10:37 -07:00
/* The TPF reader validates idx_count. */
assert(reg->idx_count == 1);
vkd3d-shader/ir: Normalise control point phase output registers to include the control point id. In SPIR-V the address must include the invocation id, but in TPF it is implicit. Move the register index up one slot and insert an OUTPOINTID relative address.
2023-04-04 00:55:05 -07:00
reg->idx[1] = reg->idx[0];
/* The control point id param is implicit here. Avoid later complications by inserting it. */
reg->idx[0].offset = 0;
reg->idx[0].rel_addr = normaliser->outpointid_param;
vkd3d-shader/tpf: Validate input/output register index counts.
2023-05-03 00:10:37 -07:00
++reg->idx_count;
vkd3d-shader/ir: Normalise control point phase output registers to include the control point id. In SPIR-V the address must include the invocation id, but in TPF it is implicit. Move the register index up one slot and insert an OUTPOINTID relative address.
2023-04-04 00:55:05 -07:00
}
}
vkd3d-shader/tpf: Validate input/output register index counts.
2023-05-03 00:10:37 -07:00
static void shader_dst_param_io_init(struct vkd3d_shader_dst_param *param, const struct signature_element *e,
enum vkd3d_shader_register_type reg_type, unsigned int idx_count)
vkd3d-shader/ir: Insert hull shader control point input declarations if no control point phase is defined. The SPIR-V backend will emit a default control point phase. Inserting inputs into the IR allows handling of declarations via the usual path instead of an ad hoc implementation which may not match later changes to input handling.
2023-04-04 00:28:48 -07:00
{
param->write_mask = e->mask;
param->modifiers = 0;
param->shift = 0;
vkd3d-shader: Rename shader_register_init() to vsir_register_init().
2023-08-29 10:20:44 -07:00
vsir_register_init(&param->reg, reg_type, vkd3d_data_type_from_component_type(e->component_type), idx_count);
vkd3d-shader/ir: Insert hull shader control point input declarations if no control point phase is defined. The SPIR-V backend will emit a default control point phase. Inserting inputs into the IR allows handling of declarations via the usual path instead of an ad hoc implementation which may not match later changes to input handling.
2023-04-04 00:28:48 -07:00
}
vkd3d-shader/ir: Eliminate struct vkd3d_shader_normaliser.
2023-05-05 00:23:56 -07:00
static enum vkd3d_result control_point_normaliser_emit_hs_input(struct control_point_normaliser *normaliser,
vkd3d-shader: Embed the parsing location in vkd3d_shader_instruction. So that it can be used for printing meaningful error locations by downstream processors.
2023-09-05 02:31:31 -07:00
const struct shader_signature *s, unsigned int input_control_point_count, unsigned int dst,
const struct vkd3d_shader_location *location)
vkd3d-shader/ir: Insert hull shader control point input declarations if no control point phase is defined. The SPIR-V backend will emit a default control point phase. Inserting inputs into the IR allows handling of declarations via the usual path instead of an ad hoc implementation which may not match later changes to input handling.
2023-04-04 00:28:48 -07:00
{
struct vkd3d_shader_instruction *ins;
struct vkd3d_shader_dst_param *param;
vkd3d-shader: Introduce an internal shader signature structure. A register count is required for Shader Model 6 signatures, including those normalised from earlier models.
2023-04-03 23:22:57 -07:00
const struct signature_element *e;
vkd3d-shader/ir: Insert hull shader control point input declarations if no control point phase is defined. The SPIR-V backend will emit a default control point phase. Inserting inputs into the IR allows handling of declarations via the usual path instead of an ad hoc implementation which may not match later changes to input handling.
2023-04-04 00:28:48 -07:00
unsigned int i, count;
for (i = 0, count = 1; i < s->element_count; ++i)
count += !!s->elements[i].used_mask;
if (!shader_instruction_array_reserve(&normaliser->instructions, normaliser->instructions.count + count))
return VKD3D_ERROR_OUT_OF_MEMORY;
memmove(&normaliser->instructions.elements[dst + count], &normaliser->instructions.elements[dst],
(normaliser->instructions.count - dst) * sizeof(*normaliser->instructions.elements));
normaliser->instructions.count += count;
ins = &normaliser->instructions.elements[dst];
vkd3d-shader: Embed the parsing location in vkd3d_shader_instruction. So that it can be used for printing meaningful error locations by downstream processors.
2023-09-05 02:31:31 -07:00
vsir_instruction_init(ins, location, VKD3DSIH_HS_CONTROL_POINT_PHASE);
vkd3d-shader/ir: Insert hull shader control point input declarations if no control point phase is defined. The SPIR-V backend will emit a default control point phase. Inserting inputs into the IR allows handling of declarations via the usual path instead of an ad hoc implementation which may not match later changes to input handling.
2023-04-04 00:28:48 -07:00
ins->flags = 1;
++ins;
for (i = 0; i < s->element_count; ++i)
{
e = &s->elements[i];
if (!e->used_mask)
continue;
if (e->sysval_semantic != VKD3D_SHADER_SV_NONE)
{
vkd3d-shader: Embed the parsing location in vkd3d_shader_instruction. So that it can be used for printing meaningful error locations by downstream processors.
2023-09-05 02:31:31 -07:00
vsir_instruction_init(ins, location, VKD3DSIH_DCL_INPUT_SIV);
vkd3d-shader/ir: Insert hull shader control point input declarations if no control point phase is defined. The SPIR-V backend will emit a default control point phase. Inserting inputs into the IR allows handling of declarations via the usual path instead of an ad hoc implementation which may not match later changes to input handling.
2023-04-04 00:28:48 -07:00
param = &ins->declaration.register_semantic.reg;
ins->declaration.register_semantic.sysval_semantic = vkd3d_siv_from_sysval(e->sysval_semantic);
}
else
{
vkd3d-shader: Embed the parsing location in vkd3d_shader_instruction. So that it can be used for printing meaningful error locations by downstream processors.
2023-09-05 02:31:31 -07:00
vsir_instruction_init(ins, location, VKD3DSIH_DCL_INPUT);
vkd3d-shader/ir: Insert hull shader control point input declarations if no control point phase is defined. The SPIR-V backend will emit a default control point phase. Inserting inputs into the IR allows handling of declarations via the usual path instead of an ad hoc implementation which may not match later changes to input handling.
2023-04-04 00:28:48 -07:00
param = &ins->declaration.dst;
}
vkd3d-shader/tpf: Validate input/output register index counts.
2023-05-03 00:10:37 -07:00
shader_dst_param_io_init(param, e, VKD3DSPR_INPUT, 2);
vkd3d-shader/ir: Insert hull shader control point input declarations if no control point phase is defined. The SPIR-V backend will emit a default control point phase. Inserting inputs into the IR allows handling of declarations via the usual path instead of an ad hoc implementation which may not match later changes to input handling.
2023-04-04 00:28:48 -07:00
param->reg.idx[0].offset = input_control_point_count;
vkd3d-shader/ir: Synthesize HS inputs with the register index and write mask of the signature element. This pass was written as if to output normalized I/O, but it runs before the I/O normalization pass. Fixes: 98b5e2c6e01199d714d18fccfe54826a680aecbf
2023-10-24 14:55:16 -07:00
param->reg.idx[1].offset = e->register_index;
param->write_mask = e->mask;
vkd3d-shader/ir: Insert hull shader control point input declarations if no control point phase is defined. The SPIR-V backend will emit a default control point phase. Inserting inputs into the IR allows handling of declarations via the usual path instead of an ad hoc implementation which may not match later changes to input handling.
2023-04-04 00:28:48 -07:00
++ins;
}
return VKD3D_OK;
}
vkd3d-shader/ir: Move normalization code from spirv.c to ir.c. It is not spirv-specific and will (presumably) be used for GLSL as well.
2023-07-02 18:23:07 -07:00
static enum vkd3d_result instruction_array_normalise_hull_shader_control_point_io(
vkd3d-shader/ir: Eliminate struct vkd3d_shader_normaliser.
2023-05-05 00:23:56 -07:00
struct vkd3d_shader_instruction_array *src_instructions, const struct shader_signature *input_signature)
vkd3d-shader/ir: Normalise control point phase output registers to include the control point id. In SPIR-V the address must include the invocation id, but in TPF it is implicit. Move the register index up one slot and insert an OUTPOINTID relative address.
2023-04-04 00:55:05 -07:00
{
vkd3d-shader/ir: Eliminate struct vkd3d_shader_normaliser.
2023-05-05 00:23:56 -07:00
struct vkd3d_shader_instruction_array *instructions;
struct control_point_normaliser normaliser;
vkd3d-shader/ir: Insert hull shader control point input declarations if no control point phase is defined. The SPIR-V backend will emit a default control point phase. Inserting inputs into the IR allows handling of declarations via the usual path instead of an ad hoc implementation which may not match later changes to input handling.
2023-04-04 00:28:48 -07:00
unsigned int input_control_point_count;
vkd3d-shader/ir: Pass a local copy of location to control_point_normaliser_emit_hs_input().
2023-12-07 06:34:10 -08:00
struct vkd3d_shader_location location;
vkd3d-shader/ir: Normalise control point phase output registers to include the control point id. In SPIR-V the address must include the invocation id, but in TPF it is implicit. Move the register index up one slot and insert an OUTPOINTID relative address.
2023-04-04 00:55:05 -07:00
struct vkd3d_shader_instruction *ins;
vkd3d-shader/ir: Eliminate struct vkd3d_shader_normaliser.
2023-05-05 00:23:56 -07:00
enum vkd3d_result ret;
vkd3d-shader/ir: Normalise control point phase output registers to include the control point id. In SPIR-V the address must include the invocation id, but in TPF it is implicit. Move the register index up one slot and insert an OUTPOINTID relative address.
2023-04-04 00:55:05 -07:00
unsigned int i, j;
vkd3d-shader/ir: Eliminate struct vkd3d_shader_normaliser.
2023-05-05 00:23:56 -07:00
if (!(normaliser.outpointid_param = instruction_array_create_outpointid_param(src_instructions)))
vkd3d-shader/ir: Normalise control point phase output registers to include the control point id. In SPIR-V the address must include the invocation id, but in TPF it is implicit. Move the register index up one slot and insert an OUTPOINTID relative address.
2023-04-04 00:55:05 -07:00
{
ERR("Failed to allocate src param.\n");
return VKD3D_ERROR_OUT_OF_MEMORY;
}
vkd3d-shader/ir: Eliminate struct vkd3d_shader_normaliser.
2023-05-05 00:23:56 -07:00
normaliser.instructions = *src_instructions;
instructions = &normaliser.instructions;
normaliser.phase = VKD3DSIH_INVALID;
vkd3d-shader/ir: Normalise control point phase output registers to include the control point id. In SPIR-V the address must include the invocation id, but in TPF it is implicit. Move the register index up one slot and insert an OUTPOINTID relative address.
2023-04-04 00:55:05 -07:00
vkd3d-shader/ir: Eliminate struct vkd3d_shader_normaliser.
2023-05-05 00:23:56 -07:00
for (i = 0; i < normaliser.instructions.count; ++i)
vkd3d-shader/ir: Normalise control point phase output registers to include the control point id. In SPIR-V the address must include the invocation id, but in TPF it is implicit. Move the register index up one slot and insert an OUTPOINTID relative address.
2023-04-04 00:55:05 -07:00
{
ins = &instructions->elements[i];
switch (ins->handler_idx)
{
case VKD3DSIH_HS_CONTROL_POINT_PHASE:
case VKD3DSIH_HS_FORK_PHASE:
case VKD3DSIH_HS_JOIN_PHASE:
vkd3d-shader/ir: Eliminate struct vkd3d_shader_normaliser.
2023-05-05 00:23:56 -07:00
normaliser.phase = ins->handler_idx;
vkd3d-shader/ir: Normalise control point phase output registers to include the control point id. In SPIR-V the address must include the invocation id, but in TPF it is implicit. Move the register index up one slot and insert an OUTPOINTID relative address.
2023-04-04 00:55:05 -07:00
break;
default:
if (shader_instruction_is_dcl(ins))
break;
for (j = 0; j < ins->dst_count; ++j)
vkd3d-shader: Make *src and *dst mutable in vkd3d_shader_instruction. They were originally made const because no optimization/normalization pass existed. Now having to cast away const all the time is becoming more and more burdening.
2024-01-11 02:19:39 -08:00
shader_dst_param_normalise_outpointid(&ins->dst[j], &normaliser);
vkd3d-shader/ir: Normalise control point phase output registers to include the control point id. In SPIR-V the address must include the invocation id, but in TPF it is implicit. Move the register index up one slot and insert an OUTPOINTID relative address.
2023-04-04 00:55:05 -07:00
break;
}
}
vkd3d-shader/ir: Eliminate struct vkd3d_shader_normaliser.
2023-05-05 00:23:56 -07:00
normaliser.phase = VKD3DSIH_INVALID;
vkd3d-shader/ir: Insert hull shader control point input declarations if no control point phase is defined. The SPIR-V backend will emit a default control point phase. Inserting inputs into the IR allows handling of declarations via the usual path instead of an ad hoc implementation which may not match later changes to input handling.
2023-04-04 00:28:48 -07:00
input_control_point_count = 1;
for (i = 0; i < instructions->count; ++i)
{
ins = &instructions->elements[i];
switch (ins->handler_idx)
{
case VKD3DSIH_DCL_INPUT_CONTROL_POINT_COUNT:
input_control_point_count = ins->declaration.count;
break;
case VKD3DSIH_HS_CONTROL_POINT_PHASE:
vkd3d-shader/ir: Eliminate struct vkd3d_shader_normaliser.
2023-05-05 00:23:56 -07:00
*src_instructions = normaliser.instructions;
vkd3d-shader/ir: Insert hull shader control point input declarations if no control point phase is defined. The SPIR-V backend will emit a default control point phase. Inserting inputs into the IR allows handling of declarations via the usual path instead of an ad hoc implementation which may not match later changes to input handling.
2023-04-04 00:28:48 -07:00
return VKD3D_OK;
case VKD3DSIH_HS_FORK_PHASE:
case VKD3DSIH_HS_JOIN_PHASE:
vkd3d-shader/ir: Pass a local copy of location to control_point_normaliser_emit_hs_input().
2023-12-07 06:34:10 -08:00
/* ins may be relocated if the instruction array expands. */
location = ins->location;
vkd3d-shader/ir: Eliminate struct vkd3d_shader_normaliser.
2023-05-05 00:23:56 -07:00
ret = control_point_normaliser_emit_hs_input(&normaliser, input_signature,
vkd3d-shader/ir: Pass a local copy of location to control_point_normaliser_emit_hs_input().
2023-12-07 06:34:10 -08:00
input_control_point_count, i, &location);
vkd3d-shader/ir: Eliminate struct vkd3d_shader_normaliser.
2023-05-05 00:23:56 -07:00
*src_instructions = normaliser.instructions;
return ret;
vkd3d-shader/ir: Insert hull shader control point input declarations if no control point phase is defined. The SPIR-V backend will emit a default control point phase. Inserting inputs into the IR allows handling of declarations via the usual path instead of an ad hoc implementation which may not match later changes to input handling.
2023-04-04 00:28:48 -07:00
default:
break;
}
}
vkd3d-shader/ir: Eliminate struct vkd3d_shader_normaliser.
2023-05-05 00:23:56 -07:00
*src_instructions = normaliser.instructions;
vkd3d-shader/ir: Normalise control point phase output registers to include the control point id. In SPIR-V the address must include the invocation id, but in TPF it is implicit. Move the register index up one slot and insert an OUTPOINTID relative address.
2023-04-04 00:55:05 -07:00
return VKD3D_OK;
}
vkd3d-shader/ir: Normalise signatures and input/output registers to the Shader Model 6 pattern. In Shader Model 6 each signature element can span a range of register indices, or 'rows', and system values do not share a register index with non-system values. Inputs and outputs are referenced by element index instead of register index. This patch merges multiple signature elements into a single element under the following conditions: - The register index in a load or store is specified dynamically by including a relative address parameter with a base register index. The dcl_index_range instruction is used to identify these. - A register declaration is split across multiple elements which declare different components of the register. - A patch constant function writes tessellation factors. These are an array in SPIR-V, but in SM 5.x each factor is declared as a separate register, and these are dynamically indexed by the fork/join instance id. Elimination of multiple fork/join phases converts the indices to constants, but merging the signature elements into a single arrayed element matches the SPIR-V output. All references to input/output register indices are converted to element indices. If a relative address is present, the element index is moved up a slot so it cannot be confused with a constant offset. Existing code only handles register index relative addressing for tessellation factors. This patch adds generic support for it.
2023-04-25 22:27:08 -07:00
struct io_normaliser
{
struct vkd3d_shader_instruction_array instructions;
enum vkd3d_shader_type shader_type;
vkd3d-shader: Lower shader model 1/2 inter-stage I/O to a flat array. An alternative is that we stash the reg_type in the signature, but this seems far simpler for the backend to deal with.
2023-10-27 10:44:08 -07:00
uint8_t major;
vkd3d-shader/ir: Normalise signatures and input/output registers to the Shader Model 6 pattern. In Shader Model 6 each signature element can span a range of register indices, or 'rows', and system values do not share a register index with non-system values. Inputs and outputs are referenced by element index instead of register index. This patch merges multiple signature elements into a single element under the following conditions: - The register index in a load or store is specified dynamically by including a relative address parameter with a base register index. The dcl_index_range instruction is used to identify these. - A register declaration is split across multiple elements which declare different components of the register. - A patch constant function writes tessellation factors. These are an array in SPIR-V, but in SM 5.x each factor is declared as a separate register, and these are dynamically indexed by the fork/join instance id. Elimination of multiple fork/join phases converts the indices to constants, but merging the signature elements into a single arrayed element matches the SPIR-V output. All references to input/output register indices are converted to element indices. If a relative address is present, the element index is moved up a slot so it cannot be confused with a constant offset. Existing code only handles register index relative addressing for tessellation factors. This patch adds generic support for it.
2023-04-25 22:27:08 -07:00
struct shader_signature *input_signature;
struct shader_signature *output_signature;
struct shader_signature *patch_constant_signature;
unsigned int max_temp_count;
unsigned int temp_dcl_idx;
unsigned int instance_count;
unsigned int phase_body_idx;
enum vkd3d_shader_opcode phase;
unsigned int output_control_point_count;
struct vkd3d_shader_src_param *outpointid_param;
struct vkd3d_shader_dst_param *input_dcl_params[MAX_REG_OUTPUT];
struct vkd3d_shader_dst_param *output_dcl_params[MAX_REG_OUTPUT];
struct vkd3d_shader_dst_param *pc_dcl_params[MAX_REG_OUTPUT];
uint8_t input_range_map[MAX_REG_OUTPUT][VKD3D_VEC4_SIZE];
uint8_t output_range_map[MAX_REG_OUTPUT][VKD3D_VEC4_SIZE];
uint8_t pc_range_map[MAX_REG_OUTPUT][VKD3D_VEC4_SIZE];
vkd3d-shader/ir: Check for vocp usage during IR normalization. The hull shader barrier used for this was broken by I/O normalization, since vocp is no longer exposed to the spirv backend. Restore this barrier by checking for vocp during normalization instead.
2023-07-16 21:34:04 -07:00
bool use_vocp;
vkd3d-shader/ir: Normalise signatures and input/output registers to the Shader Model 6 pattern. In Shader Model 6 each signature element can span a range of register indices, or 'rows', and system values do not share a register index with non-system values. Inputs and outputs are referenced by element index instead of register index. This patch merges multiple signature elements into a single element under the following conditions: - The register index in a load or store is specified dynamically by including a relative address parameter with a base register index. The dcl_index_range instruction is used to identify these. - A register declaration is split across multiple elements which declare different components of the register. - A patch constant function writes tessellation factors. These are an array in SPIR-V, but in SM 5.x each factor is declared as a separate register, and these are dynamically indexed by the fork/join instance id. Elimination of multiple fork/join phases converts the indices to constants, but merging the signature elements into a single arrayed element matches the SPIR-V output. All references to input/output register indices are converted to element indices. If a relative address is present, the element index is moved up a slot so it cannot be confused with a constant offset. Existing code only handles register index relative addressing for tessellation factors. This patch adds generic support for it.
2023-04-25 22:27:08 -07:00
};
static bool io_normaliser_is_in_fork_or_join_phase(const struct io_normaliser *normaliser)
{
return normaliser->phase == VKD3DSIH_HS_FORK_PHASE || normaliser->phase == VKD3DSIH_HS_JOIN_PHASE;
}
static bool io_normaliser_is_in_control_point_phase(const struct io_normaliser *normaliser)
{
return normaliser->phase == VKD3DSIH_HS_CONTROL_POINT_PHASE;
}
static unsigned int shader_signature_find_element_for_reg(const struct shader_signature *signature,
unsigned int reg_idx, unsigned int write_mask)
{
vkd3d-shader/ir: Expand index range write masks to cover all element masks. For example, this occurred in a shader: reg_idx write_mask 0 xyz 1 xyzw 2 xyzw 3 xyz The dcl_indexrange instruction covered only xyz, so once merged, searching for xyzw failed. It is impossible to declare an input array where elements have different component counts, but the optimiser can create this case. One way for this to occur is to dynamically index input values via a local array containing copies of the input values. The optimiser converts this to dynamically indexed inputs.
2024-01-03 22:05:15 -08:00
unsigned int i, base_write_mask;
vkd3d-shader/ir: Normalise signatures and input/output registers to the Shader Model 6 pattern. In Shader Model 6 each signature element can span a range of register indices, or 'rows', and system values do not share a register index with non-system values. Inputs and outputs are referenced by element index instead of register index. This patch merges multiple signature elements into a single element under the following conditions: - The register index in a load or store is specified dynamically by including a relative address parameter with a base register index. The dcl_index_range instruction is used to identify these. - A register declaration is split across multiple elements which declare different components of the register. - A patch constant function writes tessellation factors. These are an array in SPIR-V, but in SM 5.x each factor is declared as a separate register, and these are dynamically indexed by the fork/join instance id. Elimination of multiple fork/join phases converts the indices to constants, but merging the signature elements into a single arrayed element matches the SPIR-V output. All references to input/output register indices are converted to element indices. If a relative address is present, the element index is moved up a slot so it cannot be confused with a constant offset. Existing code only handles register index relative addressing for tessellation factors. This patch adds generic support for it.
2023-04-25 22:27:08 -07:00
for (i = 0; i < signature->element_count; ++i)
{
struct signature_element *e = &signature->elements[i];
if (e->register_index <= reg_idx && e->register_index + e->register_count > reg_idx
&& (e->mask & write_mask) == write_mask)
{
return i;
}
}
vkd3d-shader/ir: Expand index range write masks to cover all element masks. For example, this occurred in a shader: reg_idx write_mask 0 xyz 1 xyzw 2 xyzw 3 xyz The dcl_indexrange instruction covered only xyz, so once merged, searching for xyzw failed. It is impossible to declare an input array where elements have different component counts, but the optimiser can create this case. One way for this to occur is to dynamically index input values via a local array containing copies of the input values. The optimiser converts this to dynamically indexed inputs.
2024-01-03 22:05:15 -08:00
/* Validated in the TPF reader, but failure in signature_element_range_expand_mask()
* can land us here on an unmatched vector mask. */
FIXME("Failed to find signature element for register index %u, mask %#x; using scalar mask.\n",
reg_idx, write_mask);
base_write_mask = 1u << vsir_write_mask_get_component_idx(write_mask);
if (base_write_mask != write_mask)
return shader_signature_find_element_for_reg(signature, reg_idx, base_write_mask);
vkd3d-shader/ir: Normalise signatures and input/output registers to the Shader Model 6 pattern. In Shader Model 6 each signature element can span a range of register indices, or 'rows', and system values do not share a register index with non-system values. Inputs and outputs are referenced by element index instead of register index. This patch merges multiple signature elements into a single element under the following conditions: - The register index in a load or store is specified dynamically by including a relative address parameter with a base register index. The dcl_index_range instruction is used to identify these. - A register declaration is split across multiple elements which declare different components of the register. - A patch constant function writes tessellation factors. These are an array in SPIR-V, but in SM 5.x each factor is declared as a separate register, and these are dynamically indexed by the fork/join instance id. Elimination of multiple fork/join phases converts the indices to constants, but merging the signature elements into a single arrayed element matches the SPIR-V output. All references to input/output register indices are converted to element indices. If a relative address is present, the element index is moved up a slot so it cannot be confused with a constant offset. Existing code only handles register index relative addressing for tessellation factors. This patch adds generic support for it.
2023-04-25 22:27:08 -07:00
vkd3d_unreachable();
}
vkd3d-shader/tpf: Set the interpolation mode for signature elements.
2023-10-19 19:34:41 -07:00
struct signature_element *vsir_signature_find_element_for_reg(const struct shader_signature *signature,
unsigned int reg_idx, unsigned int write_mask)
{
return &signature->elements[shader_signature_find_element_for_reg(signature, reg_idx, write_mask)];
}
vkd3d-shader/ir: Normalise signatures and input/output registers to the Shader Model 6 pattern. In Shader Model 6 each signature element can span a range of register indices, or 'rows', and system values do not share a register index with non-system values. Inputs and outputs are referenced by element index instead of register index. This patch merges multiple signature elements into a single element under the following conditions: - The register index in a load or store is specified dynamically by including a relative address parameter with a base register index. The dcl_index_range instruction is used to identify these. - A register declaration is split across multiple elements which declare different components of the register. - A patch constant function writes tessellation factors. These are an array in SPIR-V, but in SM 5.x each factor is declared as a separate register, and these are dynamically indexed by the fork/join instance id. Elimination of multiple fork/join phases converts the indices to constants, but merging the signature elements into a single arrayed element matches the SPIR-V output. All references to input/output register indices are converted to element indices. If a relative address is present, the element index is moved up a slot so it cannot be confused with a constant offset. Existing code only handles register index relative addressing for tessellation factors. This patch adds generic support for it.
2023-04-25 22:27:08 -07:00
static unsigned int range_map_get_register_count(uint8_t range_map[][VKD3D_VEC4_SIZE],
vkd3d-shader/ir: Pass a uint32_t write mask to vkd3d_write_mask_get_component_idx().
2023-12-05 13:19:07 -08:00
unsigned int register_idx, uint32_t write_mask)
vkd3d-shader/ir: Normalise signatures and input/output registers to the Shader Model 6 pattern. In Shader Model 6 each signature element can span a range of register indices, or 'rows', and system values do not share a register index with non-system values. Inputs and outputs are referenced by element index instead of register index. This patch merges multiple signature elements into a single element under the following conditions: - The register index in a load or store is specified dynamically by including a relative address parameter with a base register index. The dcl_index_range instruction is used to identify these. - A register declaration is split across multiple elements which declare different components of the register. - A patch constant function writes tessellation factors. These are an array in SPIR-V, but in SM 5.x each factor is declared as a separate register, and these are dynamically indexed by the fork/join instance id. Elimination of multiple fork/join phases converts the indices to constants, but merging the signature elements into a single arrayed element matches the SPIR-V output. All references to input/output register indices are converted to element indices. If a relative address is present, the element index is moved up a slot so it cannot be confused with a constant offset. Existing code only handles register index relative addressing for tessellation factors. This patch adds generic support for it.
2023-04-25 22:27:08 -07:00
{
vkd3d-shader/ir: Pass a uint32_t write mask to vkd3d_write_mask_get_component_idx().
2023-12-05 13:19:07 -08:00
return range_map[register_idx][vsir_write_mask_get_component_idx(write_mask)];
vkd3d-shader/ir: Normalise signatures and input/output registers to the Shader Model 6 pattern. In Shader Model 6 each signature element can span a range of register indices, or 'rows', and system values do not share a register index with non-system values. Inputs and outputs are referenced by element index instead of register index. This patch merges multiple signature elements into a single element under the following conditions: - The register index in a load or store is specified dynamically by including a relative address parameter with a base register index. The dcl_index_range instruction is used to identify these. - A register declaration is split across multiple elements which declare different components of the register. - A patch constant function writes tessellation factors. These are an array in SPIR-V, but in SM 5.x each factor is declared as a separate register, and these are dynamically indexed by the fork/join instance id. Elimination of multiple fork/join phases converts the indices to constants, but merging the signature elements into a single arrayed element matches the SPIR-V output. All references to input/output register indices are converted to element indices. If a relative address is present, the element index is moved up a slot so it cannot be confused with a constant offset. Existing code only handles register index relative addressing for tessellation factors. This patch adds generic support for it.
2023-04-25 22:27:08 -07:00
}
static void range_map_set_register_range(uint8_t range_map[][VKD3D_VEC4_SIZE], unsigned int register_idx,
vkd3d-shader/ir: Pass a uint32_t write mask to vkd3d_write_mask_get_component_idx().
2023-12-05 13:19:07 -08:00
unsigned int register_count, uint32_t write_mask, bool is_dcl_indexrange)
vkd3d-shader/ir: Normalise signatures and input/output registers to the Shader Model 6 pattern. In Shader Model 6 each signature element can span a range of register indices, or 'rows', and system values do not share a register index with non-system values. Inputs and outputs are referenced by element index instead of register index. This patch merges multiple signature elements into a single element under the following conditions: - The register index in a load or store is specified dynamically by including a relative address parameter with a base register index. The dcl_index_range instruction is used to identify these. - A register declaration is split across multiple elements which declare different components of the register. - A patch constant function writes tessellation factors. These are an array in SPIR-V, but in SM 5.x each factor is declared as a separate register, and these are dynamically indexed by the fork/join instance id. Elimination of multiple fork/join phases converts the indices to constants, but merging the signature elements into a single arrayed element matches the SPIR-V output. All references to input/output register indices are converted to element indices. If a relative address is present, the element index is moved up a slot so it cannot be confused with a constant offset. Existing code only handles register index relative addressing for tessellation factors. This patch adds generic support for it.
2023-04-25 22:27:08 -07:00
{
unsigned int i, j, r, c, component_idx, component_count;
assert(write_mask <= VKD3DSP_WRITEMASK_ALL);
vkd3d-shader/ir: Pass a uint32_t write mask to vkd3d_write_mask_get_component_idx().
2023-12-05 13:19:07 -08:00
component_idx = vsir_write_mask_get_component_idx(write_mask);
vkd3d-shader/ir: Pass a uint32_t write mask to vkd3d_write_mask_component_count().
2023-12-05 13:35:37 -08:00
component_count = vsir_write_mask_component_count(write_mask);
vkd3d-shader/ir: Normalise signatures and input/output registers to the Shader Model 6 pattern. In Shader Model 6 each signature element can span a range of register indices, or 'rows', and system values do not share a register index with non-system values. Inputs and outputs are referenced by element index instead of register index. This patch merges multiple signature elements into a single element under the following conditions: - The register index in a load or store is specified dynamically by including a relative address parameter with a base register index. The dcl_index_range instruction is used to identify these. - A register declaration is split across multiple elements which declare different components of the register. - A patch constant function writes tessellation factors. These are an array in SPIR-V, but in SM 5.x each factor is declared as a separate register, and these are dynamically indexed by the fork/join instance id. Elimination of multiple fork/join phases converts the indices to constants, but merging the signature elements into a single arrayed element matches the SPIR-V output. All references to input/output register indices are converted to element indices. If a relative address is present, the element index is moved up a slot so it cannot be confused with a constant offset. Existing code only handles register index relative addressing for tessellation factors. This patch adds generic support for it.
2023-04-25 22:27:08 -07:00
assert(register_idx < MAX_REG_OUTPUT && MAX_REG_OUTPUT - register_idx >= register_count);
if (range_map[register_idx][component_idx] > register_count && is_dcl_indexrange)
{
/* Validated in the TPF reader. */
assert(range_map[register_idx][component_idx] != UINT8_MAX);
return;
}
if (range_map[register_idx][component_idx] == register_count)
{
/* Already done. This happens when fxc splits a register declaration by
* component(s). The dcl_indexrange instructions are split too. */
return;
}
range_map[register_idx][component_idx] = register_count;
for (i = 0; i < register_count; ++i)
{
r = register_idx + i;
for (j = !i; j < component_count; ++j)
{
c = component_idx + j;
/* A synthetic patch constant range which overlaps an existing range can start upstream of it
* for fork/join phase instancing, but ranges declared by dcl_indexrange should not overlap.
* The latter is validated in the TPF reader. */
assert(!range_map[r][c] || !is_dcl_indexrange);
range_map[r][c] = UINT8_MAX;
}
}
}
static void io_normaliser_add_index_range(struct io_normaliser *normaliser,
const struct vkd3d_shader_instruction *ins)
{
const struct vkd3d_shader_index_range *range = &ins->declaration.index_range;
const struct vkd3d_shader_register *reg = &range->dst.reg;
unsigned int reg_idx, write_mask, element_idx;
const struct shader_signature *signature;
uint8_t (*range_map)[VKD3D_VEC4_SIZE];
switch (reg->type)
{
case VKD3DSPR_INPUT:
case VKD3DSPR_INCONTROLPOINT:
range_map = normaliser->input_range_map;
signature = normaliser->input_signature;
break;
case VKD3DSPR_OUTCONTROLPOINT:
range_map = normaliser->output_range_map;
signature = normaliser->output_signature;
break;
case VKD3DSPR_OUTPUT:
if (!io_normaliser_is_in_fork_or_join_phase(normaliser))
{
range_map = normaliser->output_range_map;
signature = normaliser->output_signature;
break;
}
/* fall through */
case VKD3DSPR_PATCHCONST:
range_map = normaliser->pc_range_map;
signature = normaliser->patch_constant_signature;
break;
default:
/* Validated in the TPF reader. */
vkd3d_unreachable();
}
reg_idx = reg->idx[reg->idx_count - 1].offset;
write_mask = range->dst.write_mask;
element_idx = shader_signature_find_element_for_reg(signature, reg_idx, write_mask);
range_map_set_register_range(range_map, reg_idx, range->register_count,
signature->elements[element_idx].mask, true);
}
static int signature_element_mask_compare(const void *a, const void *b)
{
const struct signature_element *e = a, *f = b;
int ret;
return (ret = vkd3d_u32_compare(e->mask, f->mask)) ? ret : vkd3d_u32_compare(e->register_index, f->register_index);
}
static bool sysval_semantics_should_merge(const struct signature_element *e, const struct signature_element *f)
{
if (e->sysval_semantic < VKD3D_SHADER_SV_TESS_FACTOR_QUADEDGE
|| e->sysval_semantic > VKD3D_SHADER_SV_TESS_FACTOR_LINEDEN)
return false;
return e->sysval_semantic == f->sysval_semantic
/* Line detail and density must be merged together to match the SPIR-V array.
* This deletes one of the two sysvals, but these are not used. */
|| (e->sysval_semantic == VKD3D_SHADER_SV_TESS_FACTOR_LINEDET
&& f->sysval_semantic == VKD3D_SHADER_SV_TESS_FACTOR_LINEDEN)
|| (e->sysval_semantic == VKD3D_SHADER_SV_TESS_FACTOR_LINEDEN
&& f->sysval_semantic == VKD3D_SHADER_SV_TESS_FACTOR_LINEDET);
}
/* Merge tess factor sysvals because they are an array in SPIR-V. */
static void shader_signature_map_patch_constant_index_ranges(struct shader_signature *s,
uint8_t range_map[][VKD3D_VEC4_SIZE])
{
struct signature_element *e, *f;
unsigned int i, j, register_count;
qsort(s->elements, s->element_count, sizeof(s->elements[0]), signature_element_mask_compare);
for (i = 0; i < s->element_count; i += register_count)
{
e = &s->elements[i];
register_count = 1;
if (!e->sysval_semantic)
continue;
for (j = i + 1; j < s->element_count; ++j, ++register_count)
{
f = &s->elements[j];
if (f->register_index != e->register_index + register_count || !sysval_semantics_should_merge(e, f))
break;
}
if (register_count < 2)
continue;
range_map_set_register_range(range_map, e->register_index, register_count, e->mask, false);
}
}
static int signature_element_register_compare(const void *a, const void *b)
{
const struct signature_element *e = a, *f = b;
return vkd3d_u32_compare(e->register_index, f->register_index);
}
static int signature_element_index_compare(const void *a, const void *b)
{
const struct signature_element *e = a, *f = b;
return vkd3d_u32_compare(e->sort_index, f->sort_index);
}
vkd3d-shader/ir: Expand index range write masks to cover all element masks. For example, this occurred in a shader: reg_idx write_mask 0 xyz 1 xyzw 2 xyzw 3 xyz The dcl_indexrange instruction covered only xyz, so once merged, searching for xyzw failed. It is impossible to declare an input array where elements have different component counts, but the optimiser can create this case. One way for this to occur is to dynamically index input values via a local array containing copies of the input values. The optimiser converts this to dynamically indexed inputs.
2024-01-03 22:05:15 -08:00
static unsigned int signature_element_range_expand_mask(struct signature_element *e, unsigned int register_count,
uint8_t range_map[][VKD3D_VEC4_SIZE])
{
unsigned int i, j, component_idx, component_count, merged_write_mask = e->mask;
/* dcl_indexrange instructions can declare a subset of the full mask, and the masks of
* the elements within the range may differ. TPF's handling of arrayed inputs with
* dcl_indexrange is really just a hack. Here we create a mask which covers all element
* masks, and check for collisions with other ranges. */
for (i = 1; i < register_count; ++i)
merged_write_mask |= e[i].mask;
if (merged_write_mask == e->mask)
return merged_write_mask;
/* Reaching this point is very rare to begin with, and collisions are even rarer or
* impossible. If the latter shows up, the fallback in shader_signature_find_element_for_reg()
* may be sufficient. */
component_idx = vsir_write_mask_get_component_idx(e->mask);
component_count = vsir_write_mask_component_count(e->mask);
for (i = e->register_index; i < e->register_index + register_count; ++i)
{
for (j = 0; j < component_idx; ++j)
if (range_map[i][j])
break;
for (j = component_idx + component_count; j < VKD3D_VEC4_SIZE; ++j)
if (range_map[i][j])
break;
}
if (i == register_count)
{
WARN("Expanding mask %#x to %#x for %s, base reg %u, count %u.\n", e->mask, merged_write_mask,
e->semantic_name, e->register_index, register_count);
return merged_write_mask;
}
WARN("Cannot expand mask %#x to %#x for %s, base reg %u, count %u.\n", e->mask, merged_write_mask,
e->semantic_name, e->register_index, register_count);
return e->mask;
}
vkd3d-shader/ir: Normalise signatures and input/output registers to the Shader Model 6 pattern. In Shader Model 6 each signature element can span a range of register indices, or 'rows', and system values do not share a register index with non-system values. Inputs and outputs are referenced by element index instead of register index. This patch merges multiple signature elements into a single element under the following conditions: - The register index in a load or store is specified dynamically by including a relative address parameter with a base register index. The dcl_index_range instruction is used to identify these. - A register declaration is split across multiple elements which declare different components of the register. - A patch constant function writes tessellation factors. These are an array in SPIR-V, but in SM 5.x each factor is declared as a separate register, and these are dynamically indexed by the fork/join instance id. Elimination of multiple fork/join phases converts the indices to constants, but merging the signature elements into a single arrayed element matches the SPIR-V output. All references to input/output register indices are converted to element indices. If a relative address is present, the element index is moved up a slot so it cannot be confused with a constant offset. Existing code only handles register index relative addressing for tessellation factors. This patch adds generic support for it.
2023-04-25 22:27:08 -07:00
static bool shader_signature_merge(struct shader_signature *s, uint8_t range_map[][VKD3D_VEC4_SIZE],
bool is_patch_constant)
{
unsigned int i, j, element_count, new_count, register_count;
struct signature_element *elements;
struct signature_element *e, *f;
vkd3d-shader/ir: Set merged signature element interpolation mode only from used elements.
2024-01-07 19:52:46 -08:00
bool used;
vkd3d-shader/ir: Normalise signatures and input/output registers to the Shader Model 6 pattern. In Shader Model 6 each signature element can span a range of register indices, or 'rows', and system values do not share a register index with non-system values. Inputs and outputs are referenced by element index instead of register index. This patch merges multiple signature elements into a single element under the following conditions: - The register index in a load or store is specified dynamically by including a relative address parameter with a base register index. The dcl_index_range instruction is used to identify these. - A register declaration is split across multiple elements which declare different components of the register. - A patch constant function writes tessellation factors. These are an array in SPIR-V, but in SM 5.x each factor is declared as a separate register, and these are dynamically indexed by the fork/join instance id. Elimination of multiple fork/join phases converts the indices to constants, but merging the signature elements into a single arrayed element matches the SPIR-V output. All references to input/output register indices are converted to element indices. If a relative address is present, the element index is moved up a slot so it cannot be confused with a constant offset. Existing code only handles register index relative addressing for tessellation factors. This patch adds generic support for it.
2023-04-25 22:27:08 -07:00
element_count = s->element_count;
if (!(elements = vkd3d_malloc(element_count * sizeof(*elements))))
return false;
memcpy(elements, s->elements, element_count * sizeof(*elements));
qsort(elements, element_count, sizeof(elements[0]), signature_element_register_compare);
for (i = 0, new_count = 0; i < element_count; i = j, elements[new_count++] = *e)
{
e = &elements[i];
j = i + 1;
if (e->register_index == ~0u)
continue;
/* Do not merge if the register index will be relative-addressed. */
if (range_map_get_register_count(range_map, e->register_index, e->mask) > 1)
continue;
vkd3d-shader/ir: Set merged signature element interpolation mode only from used elements.
2024-01-07 19:52:46 -08:00
used = e->used_mask;
vkd3d-shader/ir: Normalise signatures and input/output registers to the Shader Model 6 pattern. In Shader Model 6 each signature element can span a range of register indices, or 'rows', and system values do not share a register index with non-system values. Inputs and outputs are referenced by element index instead of register index. This patch merges multiple signature elements into a single element under the following conditions: - The register index in a load or store is specified dynamically by including a relative address parameter with a base register index. The dcl_index_range instruction is used to identify these. - A register declaration is split across multiple elements which declare different components of the register. - A patch constant function writes tessellation factors. These are an array in SPIR-V, but in SM 5.x each factor is declared as a separate register, and these are dynamically indexed by the fork/join instance id. Elimination of multiple fork/join phases converts the indices to constants, but merging the signature elements into a single arrayed element matches the SPIR-V output. All references to input/output register indices are converted to element indices. If a relative address is present, the element index is moved up a slot so it cannot be confused with a constant offset. Existing code only handles register index relative addressing for tessellation factors. This patch adds generic support for it.
2023-04-25 22:27:08 -07:00
for (; j < element_count; ++j)
{
f = &elements[j];
/* Merge different components of the same register unless sysvals are different,
vkd3d-shader/ir: Revert "Do not merge signature elements which have different interpolation modes.". This reverts commit b5c067b41a173e2ab252d5a3588f807c3ade5b2a. The commit causes regressions in other shaders because unused elements do not have an interpolation mode.
2024-01-03 17:23:16 -08:00
* or it will be relative-addressed. */
vkd3d-shader/ir: Normalise signatures and input/output registers to the Shader Model 6 pattern. In Shader Model 6 each signature element can span a range of register indices, or 'rows', and system values do not share a register index with non-system values. Inputs and outputs are referenced by element index instead of register index. This patch merges multiple signature elements into a single element under the following conditions: - The register index in a load or store is specified dynamically by including a relative address parameter with a base register index. The dcl_index_range instruction is used to identify these. - A register declaration is split across multiple elements which declare different components of the register. - A patch constant function writes tessellation factors. These are an array in SPIR-V, but in SM 5.x each factor is declared as a separate register, and these are dynamically indexed by the fork/join instance id. Elimination of multiple fork/join phases converts the indices to constants, but merging the signature elements into a single arrayed element matches the SPIR-V output. All references to input/output register indices are converted to element indices. If a relative address is present, the element index is moved up a slot so it cannot be confused with a constant offset. Existing code only handles register index relative addressing for tessellation factors. This patch adds generic support for it.
2023-04-25 22:27:08 -07:00
if (f->register_index != e->register_index || f->sysval_semantic != e->sysval_semantic
|| range_map_get_register_count(range_map, f->register_index, f->mask) > 1)
break;
TRACE("Merging %s, reg %u, mask %#x, sysval %#x with %s, mask %#x, sysval %#x.\n", e->semantic_name,
e->register_index, e->mask, e->sysval_semantic, f->semantic_name, f->mask, f->sysval_semantic);
assert(!(e->mask & f->mask));
e->mask |= f->mask;
e->used_mask |= f->used_mask;
e->semantic_index = min(e->semantic_index, f->semantic_index);
vkd3d-shader/ir: Set merged signature element interpolation mode only from used elements.
2024-01-07 19:52:46 -08:00
/* The first element may have no interpolation mode if it is unused. Elements which
* actually have different interpolation modes are assigned different registers. */
if (f->used_mask && !used)
{
if (e->interpolation_mode && e->interpolation_mode != f->interpolation_mode)
FIXME("Mismatching interpolation modes %u and %u.\n", e->interpolation_mode, f->interpolation_mode);
else
e->interpolation_mode = f->interpolation_mode;
}
vkd3d-shader/ir: Normalise signatures and input/output registers to the Shader Model 6 pattern. In Shader Model 6 each signature element can span a range of register indices, or 'rows', and system values do not share a register index with non-system values. Inputs and outputs are referenced by element index instead of register index. This patch merges multiple signature elements into a single element under the following conditions: - The register index in a load or store is specified dynamically by including a relative address parameter with a base register index. The dcl_index_range instruction is used to identify these. - A register declaration is split across multiple elements which declare different components of the register. - A patch constant function writes tessellation factors. These are an array in SPIR-V, but in SM 5.x each factor is declared as a separate register, and these are dynamically indexed by the fork/join instance id. Elimination of multiple fork/join phases converts the indices to constants, but merging the signature elements into a single arrayed element matches the SPIR-V output. All references to input/output register indices are converted to element indices. If a relative address is present, the element index is moved up a slot so it cannot be confused with a constant offset. Existing code only handles register index relative addressing for tessellation factors. This patch adds generic support for it.
2023-04-25 22:27:08 -07:00
}
}
element_count = new_count;
vkd3d-shader/spirv: Take ownership of the shader signatures in spirv_compiler_create(). Fixes leakage of the replacement elements in shader_signature_merge().
2023-06-16 04:44:50 -07:00
vkd3d_free(s->elements);
vkd3d-shader/ir: Normalise signatures and input/output registers to the Shader Model 6 pattern. In Shader Model 6 each signature element can span a range of register indices, or 'rows', and system values do not share a register index with non-system values. Inputs and outputs are referenced by element index instead of register index. This patch merges multiple signature elements into a single element under the following conditions: - The register index in a load or store is specified dynamically by including a relative address parameter with a base register index. The dcl_index_range instruction is used to identify these. - A register declaration is split across multiple elements which declare different components of the register. - A patch constant function writes tessellation factors. These are an array in SPIR-V, but in SM 5.x each factor is declared as a separate register, and these are dynamically indexed by the fork/join instance id. Elimination of multiple fork/join phases converts the indices to constants, but merging the signature elements into a single arrayed element matches the SPIR-V output. All references to input/output register indices are converted to element indices. If a relative address is present, the element index is moved up a slot so it cannot be confused with a constant offset. Existing code only handles register index relative addressing for tessellation factors. This patch adds generic support for it.
2023-04-25 22:27:08 -07:00
s->elements = elements;
s->element_count = element_count;
if (is_patch_constant)
shader_signature_map_patch_constant_index_ranges(s, range_map);
for (i = 0, new_count = 0; i < element_count; i += register_count, elements[new_count++] = *e)
{
e = &elements[i];
register_count = 1;
if (e->register_index >= MAX_REG_OUTPUT)
continue;
register_count = range_map_get_register_count(range_map, e->register_index, e->mask);
assert(register_count != UINT8_MAX);
register_count += !register_count;
if (register_count > 1)
{
TRACE("Merging %s, base reg %u, count %u.\n", e->semantic_name, e->register_index, register_count);
e->register_count = register_count;
vkd3d-shader/ir: Expand index range write masks to cover all element masks. For example, this occurred in a shader: reg_idx write_mask 0 xyz 1 xyzw 2 xyzw 3 xyz The dcl_indexrange instruction covered only xyz, so once merged, searching for xyzw failed. It is impossible to declare an input array where elements have different component counts, but the optimiser can create this case. One way for this to occur is to dynamically index input values via a local array containing copies of the input values. The optimiser converts this to dynamically indexed inputs.
2024-01-03 22:05:15 -08:00
e->mask = signature_element_range_expand_mask(e, register_count, range_map);
vkd3d-shader/ir: Normalise signatures and input/output registers to the Shader Model 6 pattern. In Shader Model 6 each signature element can span a range of register indices, or 'rows', and system values do not share a register index with non-system values. Inputs and outputs are referenced by element index instead of register index. This patch merges multiple signature elements into a single element under the following conditions: - The register index in a load or store is specified dynamically by including a relative address parameter with a base register index. The dcl_index_range instruction is used to identify these. - A register declaration is split across multiple elements which declare different components of the register. - A patch constant function writes tessellation factors. These are an array in SPIR-V, but in SM 5.x each factor is declared as a separate register, and these are dynamically indexed by the fork/join instance id. Elimination of multiple fork/join phases converts the indices to constants, but merging the signature elements into a single arrayed element matches the SPIR-V output. All references to input/output register indices are converted to element indices. If a relative address is present, the element index is moved up a slot so it cannot be confused with a constant offset. Existing code only handles register index relative addressing for tessellation factors. This patch adds generic support for it.
2023-04-25 22:27:08 -07:00
}
}
element_count = new_count;
/* Restoring the original order is required for sensible trace output. */
qsort(elements, element_count, sizeof(elements[0]), signature_element_index_compare);
s->element_count = element_count;
return true;
}
static unsigned int shader_register_normalise_arrayed_addressing(struct vkd3d_shader_register *reg,
unsigned int id_idx, unsigned int register_index)
{
assert(id_idx < ARRAY_SIZE(reg->idx) - 1);
/* For a relative-addressed register index, move the id up a slot to separate it from the address,
* because rel_addr can be replaced with a constant offset in some cases. */
if (reg->idx[id_idx].rel_addr)
{
reg->idx[id_idx + 1].rel_addr = NULL;
reg->idx[id_idx + 1].offset = reg->idx[id_idx].offset;
reg->idx[id_idx].offset -= register_index;
vkd3d-shader: Make the control point count the outer dimension of I/O arrays. The relative-addressed case in shader_register_normalise_arrayed_addressing() leaves the control point id in idx[0], while for constant register indices it is placed in idx[1]. The latter case could be fixed instead, but placing the control point count in the outer dimension is more logical.
2024-01-09 19:51:59 -08:00
if (id_idx)
{
/* idx[id_idx] now contains the array index, which must be moved below the control point id. */
struct vkd3d_shader_register_index tmp = reg->idx[id_idx];
reg->idx[id_idx] = reg->idx[id_idx - 1];
reg->idx[id_idx - 1] = tmp;
}
vkd3d-shader/ir: Normalise signatures and input/output registers to the Shader Model 6 pattern. In Shader Model 6 each signature element can span a range of register indices, or 'rows', and system values do not share a register index with non-system values. Inputs and outputs are referenced by element index instead of register index. This patch merges multiple signature elements into a single element under the following conditions: - The register index in a load or store is specified dynamically by including a relative address parameter with a base register index. The dcl_index_range instruction is used to identify these. - A register declaration is split across multiple elements which declare different components of the register. - A patch constant function writes tessellation factors. These are an array in SPIR-V, but in SM 5.x each factor is declared as a separate register, and these are dynamically indexed by the fork/join instance id. Elimination of multiple fork/join phases converts the indices to constants, but merging the signature elements into a single arrayed element matches the SPIR-V output. All references to input/output register indices are converted to element indices. If a relative address is present, the element index is moved up a slot so it cannot be confused with a constant offset. Existing code only handles register index relative addressing for tessellation factors. This patch adds generic support for it.
2023-04-25 22:27:08 -07:00
++id_idx;
}
/* Otherwise we have no address for the arrayed register, so insert one. This happens e.g. where
* tessellation level registers are merged into an array because they're an array in SPIR-V. */
else
{
++id_idx;
memmove(&reg->idx[1], &reg->idx[0], id_idx * sizeof(reg->idx[0]));
reg->idx[0].rel_addr = NULL;
reg->idx[0].offset = reg->idx[id_idx].offset - register_index;
}
return id_idx;
}
static bool shader_dst_param_io_normalise(struct vkd3d_shader_dst_param *dst_param, bool is_io_dcl,
struct io_normaliser *normaliser)
{
unsigned int id_idx, reg_idx, write_mask, element_idx;
struct vkd3d_shader_register *reg = &dst_param->reg;
struct vkd3d_shader_dst_param **dcl_params;
const struct shader_signature *signature;
const struct signature_element *e;
vkd3d-shader: Lower shader model 1/2 inter-stage I/O to a flat array. An alternative is that we stash the reg_type in the signature, but this seems far simpler for the backend to deal with.
2023-10-27 10:44:08 -07:00
switch (reg->type)
vkd3d-shader/ir: Normalise signatures and input/output registers to the Shader Model 6 pattern. In Shader Model 6 each signature element can span a range of register indices, or 'rows', and system values do not share a register index with non-system values. Inputs and outputs are referenced by element index instead of register index. This patch merges multiple signature elements into a single element under the following conditions: - The register index in a load or store is specified dynamically by including a relative address parameter with a base register index. The dcl_index_range instruction is used to identify these. - A register declaration is split across multiple elements which declare different components of the register. - A patch constant function writes tessellation factors. These are an array in SPIR-V, but in SM 5.x each factor is declared as a separate register, and these are dynamically indexed by the fork/join instance id. Elimination of multiple fork/join phases converts the indices to constants, but merging the signature elements into a single arrayed element matches the SPIR-V output. All references to input/output register indices are converted to element indices. If a relative address is present, the element index is moved up a slot so it cannot be confused with a constant offset. Existing code only handles register index relative addressing for tessellation factors. This patch adds generic support for it.
2023-04-25 22:27:08 -07:00
{
vkd3d-shader: Lower shader model 1/2 inter-stage I/O to a flat array. An alternative is that we stash the reg_type in the signature, but this seems far simpler for the backend to deal with.
2023-10-27 10:44:08 -07:00
case VKD3DSPR_OUTPUT:
reg_idx = reg->idx[reg->idx_count - 1].offset;
if (io_normaliser_is_in_fork_or_join_phase(normaliser))
{
signature = normaliser->patch_constant_signature;
/* Convert patch constant outputs to the patch constant register type to avoid the need
* to convert compiler symbols when accessed as inputs in a later stage. */
reg->type = VKD3DSPR_PATCHCONST;
dcl_params = normaliser->pc_dcl_params;
}
else
{
signature = normaliser->output_signature;
dcl_params = normaliser->output_dcl_params;
}
break;
case VKD3DSPR_PATCHCONST:
reg_idx = reg->idx[reg->idx_count - 1].offset;
signature = normaliser->patch_constant_signature;
dcl_params = normaliser->pc_dcl_params;
break;
case VKD3DSPR_COLOROUT:
reg_idx = reg->idx[0].offset;
signature = normaliser->output_signature;
reg->type = VKD3DSPR_OUTPUT;
dcl_params = normaliser->output_dcl_params;
break;
case VKD3DSPR_INCONTROLPOINT:
case VKD3DSPR_INPUT:
reg_idx = reg->idx[reg->idx_count - 1].offset;
signature = normaliser->input_signature;
reg->type = VKD3DSPR_INPUT;
dcl_params = normaliser->input_dcl_params;
break;
case VKD3DSPR_ATTROUT:
reg_idx = SM1_COLOR_REGISTER_OFFSET + reg->idx[0].offset;
signature = normaliser->output_signature;
reg->type = VKD3DSPR_OUTPUT;
dcl_params = normaliser->output_dcl_params;
break;
case VKD3DSPR_RASTOUT:
vkd3d-shader/d3dbc: Assign unique register indices for VKD3DSPR_RASTOUT.
2023-10-27 10:44:38 -07:00
reg_idx = SM1_RASTOUT_REGISTER_OFFSET + reg->idx[0].offset;
vkd3d-shader: Lower shader model 1/2 inter-stage I/O to a flat array. An alternative is that we stash the reg_type in the signature, but this seems far simpler for the backend to deal with.
2023-10-27 10:44:08 -07:00
signature = normaliser->output_signature;
reg->type = VKD3DSPR_OUTPUT;
dcl_params = normaliser->output_dcl_params;
break;
default:
return true;
vkd3d-shader/ir: Normalise signatures and input/output registers to the Shader Model 6 pattern. In Shader Model 6 each signature element can span a range of register indices, or 'rows', and system values do not share a register index with non-system values. Inputs and outputs are referenced by element index instead of register index. This patch merges multiple signature elements into a single element under the following conditions: - The register index in a load or store is specified dynamically by including a relative address parameter with a base register index. The dcl_index_range instruction is used to identify these. - A register declaration is split across multiple elements which declare different components of the register. - A patch constant function writes tessellation factors. These are an array in SPIR-V, but in SM 5.x each factor is declared as a separate register, and these are dynamically indexed by the fork/join instance id. Elimination of multiple fork/join phases converts the indices to constants, but merging the signature elements into a single arrayed element matches the SPIR-V output. All references to input/output register indices are converted to element indices. If a relative address is present, the element index is moved up a slot so it cannot be confused with a constant offset. Existing code only handles register index relative addressing for tessellation factors. This patch adds generic support for it.
2023-04-25 22:27:08 -07:00
}
id_idx = reg->idx_count - 1;
write_mask = dst_param->write_mask;
element_idx = shader_signature_find_element_for_reg(signature, reg_idx, write_mask);
e = &signature->elements[element_idx];
vkd3d-shader/ir: Pass a uint32_t write mask to vkd3d_write_mask_get_component_idx().
2023-12-05 13:19:07 -08:00
dst_param->write_mask >>= vsir_write_mask_get_component_idx(e->mask);
vkd3d-shader/ir: Normalise signatures and input/output registers to the Shader Model 6 pattern. In Shader Model 6 each signature element can span a range of register indices, or 'rows', and system values do not share a register index with non-system values. Inputs and outputs are referenced by element index instead of register index. This patch merges multiple signature elements into a single element under the following conditions: - The register index in a load or store is specified dynamically by including a relative address parameter with a base register index. The dcl_index_range instruction is used to identify these. - A register declaration is split across multiple elements which declare different components of the register. - A patch constant function writes tessellation factors. These are an array in SPIR-V, but in SM 5.x each factor is declared as a separate register, and these are dynamically indexed by the fork/join instance id. Elimination of multiple fork/join phases converts the indices to constants, but merging the signature elements into a single arrayed element matches the SPIR-V output. All references to input/output register indices are converted to element indices. If a relative address is present, the element index is moved up a slot so it cannot be confused with a constant offset. Existing code only handles register index relative addressing for tessellation factors. This patch adds generic support for it.
2023-04-25 22:27:08 -07:00
if (is_io_dcl)
{
/* Validated in the TPF reader. */
assert(element_idx < ARRAY_SIZE(normaliser->input_dcl_params));
if (dcl_params[element_idx])
{
/* Merge split declarations into a single one. */
dcl_params[element_idx]->write_mask |= dst_param->write_mask;
/* Turn this into a nop. */
return false;
}
else
{
dcl_params[element_idx] = dst_param;
}
}
if (io_normaliser_is_in_control_point_phase(normaliser) && reg->type == VKD3DSPR_OUTPUT)
{
if (is_io_dcl)
{
/* Emit an array size for the control points for consistency with inputs. */
reg->idx[0].offset = normaliser->output_control_point_count;
}
else
{
/* The control point id param. */
assert(reg->idx[0].rel_addr);
}
id_idx = 1;
}
vkd3d-shader/spirv: Use register counts from the signature and shader desc.
2023-10-19 19:29:30 -07:00
if ((e->register_count > 1 || vsir_sysval_semantic_is_tess_factor(e->sysval_semantic)))
vkd3d-shader/ir: Normalise signatures and input/output registers to the Shader Model 6 pattern. In Shader Model 6 each signature element can span a range of register indices, or 'rows', and system values do not share a register index with non-system values. Inputs and outputs are referenced by element index instead of register index. This patch merges multiple signature elements into a single element under the following conditions: - The register index in a load or store is specified dynamically by including a relative address parameter with a base register index. The dcl_index_range instruction is used to identify these. - A register declaration is split across multiple elements which declare different components of the register. - A patch constant function writes tessellation factors. These are an array in SPIR-V, but in SM 5.x each factor is declared as a separate register, and these are dynamically indexed by the fork/join instance id. Elimination of multiple fork/join phases converts the indices to constants, but merging the signature elements into a single arrayed element matches the SPIR-V output. All references to input/output register indices are converted to element indices. If a relative address is present, the element index is moved up a slot so it cannot be confused with a constant offset. Existing code only handles register index relative addressing for tessellation factors. This patch adds generic support for it.
2023-04-25 22:27:08 -07:00
{
if (is_io_dcl)
{
/* For control point I/O, idx 0 contains the control point count.
* Ensure it is moved up to the next slot. */
reg->idx[id_idx].offset = reg->idx[0].offset;
reg->idx[0].offset = e->register_count;
++id_idx;
}
else
{
id_idx = shader_register_normalise_arrayed_addressing(reg, id_idx, e->register_index);
}
}
/* Replace the register index with the signature element index */
reg->idx[id_idx].offset = element_idx;
reg->idx_count = id_idx + 1;
return true;
}
static void shader_src_param_io_normalise(struct vkd3d_shader_src_param *src_param,
struct io_normaliser *normaliser)
{
unsigned int i, id_idx, reg_idx, write_mask, element_idx, component_idx;
struct vkd3d_shader_register *reg = &src_param->reg;
const struct shader_signature *signature;
const struct signature_element *e;
/* Input/output registers from one phase can be used as inputs in
* subsequent phases. Specifically:
*
* - Control phase inputs are available as "vicp" in fork and join
* phases.
* - Control phase outputs are available as "vocp" in fork and join
* phases.
* - Fork phase patch constants are available as "vpc" in join
* phases.
*
* We handle "vicp" here by converting INCONTROLPOINT src registers to
* type INPUT so they match the control phase declarations. We handle
* "vocp" by converting OUTCONTROLPOINT registers to type OUTPUT.
* Merging fork and join phases handles "vpc". */
switch (reg->type)
{
case VKD3DSPR_PATCHCONST:
vkd3d-shader: Lower shader model 1/2 inter-stage I/O to a flat array. An alternative is that we stash the reg_type in the signature, but this seems far simpler for the backend to deal with.
2023-10-27 10:44:08 -07:00
reg_idx = reg->idx[reg->idx_count - 1].offset;
vkd3d-shader/ir: Normalise signatures and input/output registers to the Shader Model 6 pattern. In Shader Model 6 each signature element can span a range of register indices, or 'rows', and system values do not share a register index with non-system values. Inputs and outputs are referenced by element index instead of register index. This patch merges multiple signature elements into a single element under the following conditions: - The register index in a load or store is specified dynamically by including a relative address parameter with a base register index. The dcl_index_range instruction is used to identify these. - A register declaration is split across multiple elements which declare different components of the register. - A patch constant function writes tessellation factors. These are an array in SPIR-V, but in SM 5.x each factor is declared as a separate register, and these are dynamically indexed by the fork/join instance id. Elimination of multiple fork/join phases converts the indices to constants, but merging the signature elements into a single arrayed element matches the SPIR-V output. All references to input/output register indices are converted to element indices. If a relative address is present, the element index is moved up a slot so it cannot be confused with a constant offset. Existing code only handles register index relative addressing for tessellation factors. This patch adds generic support for it.
2023-04-25 22:27:08 -07:00
signature = normaliser->patch_constant_signature;
break;
vkd3d-shader: Lower shader model 1/2 inter-stage I/O to a flat array. An alternative is that we stash the reg_type in the signature, but this seems far simpler for the backend to deal with.
2023-10-27 10:44:08 -07:00
vkd3d-shader/ir: Normalise signatures and input/output registers to the Shader Model 6 pattern. In Shader Model 6 each signature element can span a range of register indices, or 'rows', and system values do not share a register index with non-system values. Inputs and outputs are referenced by element index instead of register index. This patch merges multiple signature elements into a single element under the following conditions: - The register index in a load or store is specified dynamically by including a relative address parameter with a base register index. The dcl_index_range instruction is used to identify these. - A register declaration is split across multiple elements which declare different components of the register. - A patch constant function writes tessellation factors. These are an array in SPIR-V, but in SM 5.x each factor is declared as a separate register, and these are dynamically indexed by the fork/join instance id. Elimination of multiple fork/join phases converts the indices to constants, but merging the signature elements into a single arrayed element matches the SPIR-V output. All references to input/output register indices are converted to element indices. If a relative address is present, the element index is moved up a slot so it cannot be confused with a constant offset. Existing code only handles register index relative addressing for tessellation factors. This patch adds generic support for it.
2023-04-25 22:27:08 -07:00
case VKD3DSPR_INCONTROLPOINT:
vkd3d-shader/ir: Normalize all I/O registers to INPUT/OUTPUT/PATCHCONST. Specifically, map COLOROUT to OUTPUT, and map INCONTROLPOINT to INPUT for domain shaders as well as hull shaders. Obscure the non-existent differences from the view of the backend.
2023-07-16 21:56:22 -07:00
reg->type = VKD3DSPR_INPUT;
vkd3d-shader/ir: Normalise signatures and input/output registers to the Shader Model 6 pattern. In Shader Model 6 each signature element can span a range of register indices, or 'rows', and system values do not share a register index with non-system values. Inputs and outputs are referenced by element index instead of register index. This patch merges multiple signature elements into a single element under the following conditions: - The register index in a load or store is specified dynamically by including a relative address parameter with a base register index. The dcl_index_range instruction is used to identify these. - A register declaration is split across multiple elements which declare different components of the register. - A patch constant function writes tessellation factors. These are an array in SPIR-V, but in SM 5.x each factor is declared as a separate register, and these are dynamically indexed by the fork/join instance id. Elimination of multiple fork/join phases converts the indices to constants, but merging the signature elements into a single arrayed element matches the SPIR-V output. All references to input/output register indices are converted to element indices. If a relative address is present, the element index is moved up a slot so it cannot be confused with a constant offset. Existing code only handles register index relative addressing for tessellation factors. This patch adds generic support for it.
2023-04-25 22:27:08 -07:00
/* fall through */
case VKD3DSPR_INPUT:
vkd3d-shader: Lower shader model 1/2 inter-stage I/O to a flat array. An alternative is that we stash the reg_type in the signature, but this seems far simpler for the backend to deal with.
2023-10-27 10:44:08 -07:00
if (normaliser->major < 3 && normaliser->shader_type == VKD3D_SHADER_TYPE_PIXEL)
reg_idx = SM1_COLOR_REGISTER_OFFSET + reg->idx[0].offset;
else
reg_idx = reg->idx[reg->idx_count - 1].offset;
vkd3d-shader/ir: Normalise signatures and input/output registers to the Shader Model 6 pattern. In Shader Model 6 each signature element can span a range of register indices, or 'rows', and system values do not share a register index with non-system values. Inputs and outputs are referenced by element index instead of register index. This patch merges multiple signature elements into a single element under the following conditions: - The register index in a load or store is specified dynamically by including a relative address parameter with a base register index. The dcl_index_range instruction is used to identify these. - A register declaration is split across multiple elements which declare different components of the register. - A patch constant function writes tessellation factors. These are an array in SPIR-V, but in SM 5.x each factor is declared as a separate register, and these are dynamically indexed by the fork/join instance id. Elimination of multiple fork/join phases converts the indices to constants, but merging the signature elements into a single arrayed element matches the SPIR-V output. All references to input/output register indices are converted to element indices. If a relative address is present, the element index is moved up a slot so it cannot be confused with a constant offset. Existing code only handles register index relative addressing for tessellation factors. This patch adds generic support for it.
2023-04-25 22:27:08 -07:00
signature = normaliser->input_signature;
break;
vkd3d-shader: Lower shader model 1/2 inter-stage I/O to a flat array. An alternative is that we stash the reg_type in the signature, but this seems far simpler for the backend to deal with.
2023-10-27 10:44:08 -07:00
vkd3d-shader/ir: Normalise signatures and input/output registers to the Shader Model 6 pattern. In Shader Model 6 each signature element can span a range of register indices, or 'rows', and system values do not share a register index with non-system values. Inputs and outputs are referenced by element index instead of register index. This patch merges multiple signature elements into a single element under the following conditions: - The register index in a load or store is specified dynamically by including a relative address parameter with a base register index. The dcl_index_range instruction is used to identify these. - A register declaration is split across multiple elements which declare different components of the register. - A patch constant function writes tessellation factors. These are an array in SPIR-V, but in SM 5.x each factor is declared as a separate register, and these are dynamically indexed by the fork/join instance id. Elimination of multiple fork/join phases converts the indices to constants, but merging the signature elements into a single arrayed element matches the SPIR-V output. All references to input/output register indices are converted to element indices. If a relative address is present, the element index is moved up a slot so it cannot be confused with a constant offset. Existing code only handles register index relative addressing for tessellation factors. This patch adds generic support for it.
2023-04-25 22:27:08 -07:00
case VKD3DSPR_OUTCONTROLPOINT:
vkd3d-shader/ir: Normalize all I/O registers to INPUT/OUTPUT/PATCHCONST. Specifically, map COLOROUT to OUTPUT, and map INCONTROLPOINT to INPUT for domain shaders as well as hull shaders. Obscure the non-existent differences from the view of the backend.
2023-07-16 21:56:22 -07:00
reg->type = VKD3DSPR_OUTPUT;
vkd3d-shader/ir: Normalise signatures and input/output registers to the Shader Model 6 pattern. In Shader Model 6 each signature element can span a range of register indices, or 'rows', and system values do not share a register index with non-system values. Inputs and outputs are referenced by element index instead of register index. This patch merges multiple signature elements into a single element under the following conditions: - The register index in a load or store is specified dynamically by including a relative address parameter with a base register index. The dcl_index_range instruction is used to identify these. - A register declaration is split across multiple elements which declare different components of the register. - A patch constant function writes tessellation factors. These are an array in SPIR-V, but in SM 5.x each factor is declared as a separate register, and these are dynamically indexed by the fork/join instance id. Elimination of multiple fork/join phases converts the indices to constants, but merging the signature elements into a single arrayed element matches the SPIR-V output. All references to input/output register indices are converted to element indices. If a relative address is present, the element index is moved up a slot so it cannot be confused with a constant offset. Existing code only handles register index relative addressing for tessellation factors. This patch adds generic support for it.
2023-04-25 22:27:08 -07:00
/* fall through */
case VKD3DSPR_OUTPUT:
vkd3d-shader: Lower shader model 1/2 inter-stage I/O to a flat array. An alternative is that we stash the reg_type in the signature, but this seems far simpler for the backend to deal with.
2023-10-27 10:44:08 -07:00
reg_idx = reg->idx[reg->idx_count - 1].offset;
vkd3d-shader/ir: Normalise signatures and input/output registers to the Shader Model 6 pattern. In Shader Model 6 each signature element can span a range of register indices, or 'rows', and system values do not share a register index with non-system values. Inputs and outputs are referenced by element index instead of register index. This patch merges multiple signature elements into a single element under the following conditions: - The register index in a load or store is specified dynamically by including a relative address parameter with a base register index. The dcl_index_range instruction is used to identify these. - A register declaration is split across multiple elements which declare different components of the register. - A patch constant function writes tessellation factors. These are an array in SPIR-V, but in SM 5.x each factor is declared as a separate register, and these are dynamically indexed by the fork/join instance id. Elimination of multiple fork/join phases converts the indices to constants, but merging the signature elements into a single arrayed element matches the SPIR-V output. All references to input/output register indices are converted to element indices. If a relative address is present, the element index is moved up a slot so it cannot be confused with a constant offset. Existing code only handles register index relative addressing for tessellation factors. This patch adds generic support for it.
2023-04-25 22:27:08 -07:00
signature = normaliser->output_signature;
break;
vkd3d-shader: Lower shader model 1/2 inter-stage I/O to a flat array. An alternative is that we stash the reg_type in the signature, but this seems far simpler for the backend to deal with.
2023-10-27 10:44:08 -07:00
case VKD3DSPR_TEXTURE:
if (normaliser->shader_type != VKD3D_SHADER_TYPE_PIXEL)
return;
reg->type = VKD3DSPR_INPUT;
reg_idx = reg->idx[0].offset;
signature = normaliser->input_signature;
break;
vkd3d-shader/ir: Normalise signatures and input/output registers to the Shader Model 6 pattern. In Shader Model 6 each signature element can span a range of register indices, or 'rows', and system values do not share a register index with non-system values. Inputs and outputs are referenced by element index instead of register index. This patch merges multiple signature elements into a single element under the following conditions: - The register index in a load or store is specified dynamically by including a relative address parameter with a base register index. The dcl_index_range instruction is used to identify these. - A register declaration is split across multiple elements which declare different components of the register. - A patch constant function writes tessellation factors. These are an array in SPIR-V, but in SM 5.x each factor is declared as a separate register, and these are dynamically indexed by the fork/join instance id. Elimination of multiple fork/join phases converts the indices to constants, but merging the signature elements into a single arrayed element matches the SPIR-V output. All references to input/output register indices are converted to element indices. If a relative address is present, the element index is moved up a slot so it cannot be confused with a constant offset. Existing code only handles register index relative addressing for tessellation factors. This patch adds generic support for it.
2023-04-25 22:27:08 -07:00
default:
return;
}
id_idx = reg->idx_count - 1;
vkd3d-shader/ir: Pass a uint32_t swizzle to vkd3d_swizzle_get_component().
2023-12-05 14:05:40 -08:00
write_mask = VKD3DSP_WRITEMASK_0 << vsir_swizzle_get_component(src_param->swizzle, 0);
vkd3d-shader/ir: Normalise signatures and input/output registers to the Shader Model 6 pattern. In Shader Model 6 each signature element can span a range of register indices, or 'rows', and system values do not share a register index with non-system values. Inputs and outputs are referenced by element index instead of register index. This patch merges multiple signature elements into a single element under the following conditions: - The register index in a load or store is specified dynamically by including a relative address parameter with a base register index. The dcl_index_range instruction is used to identify these. - A register declaration is split across multiple elements which declare different components of the register. - A patch constant function writes tessellation factors. These are an array in SPIR-V, but in SM 5.x each factor is declared as a separate register, and these are dynamically indexed by the fork/join instance id. Elimination of multiple fork/join phases converts the indices to constants, but merging the signature elements into a single arrayed element matches the SPIR-V output. All references to input/output register indices are converted to element indices. If a relative address is present, the element index is moved up a slot so it cannot be confused with a constant offset. Existing code only handles register index relative addressing for tessellation factors. This patch adds generic support for it.
2023-04-25 22:27:08 -07:00
element_idx = shader_signature_find_element_for_reg(signature, reg_idx, write_mask);
e = &signature->elements[element_idx];
vkd3d-shader/spirv: Use register counts from the signature and shader desc.
2023-10-19 19:29:30 -07:00
if ((e->register_count > 1 || vsir_sysval_semantic_is_tess_factor(e->sysval_semantic)))
vkd3d-shader/ir: Normalise signatures and input/output registers to the Shader Model 6 pattern. In Shader Model 6 each signature element can span a range of register indices, or 'rows', and system values do not share a register index with non-system values. Inputs and outputs are referenced by element index instead of register index. This patch merges multiple signature elements into a single element under the following conditions: - The register index in a load or store is specified dynamically by including a relative address parameter with a base register index. The dcl_index_range instruction is used to identify these. - A register declaration is split across multiple elements which declare different components of the register. - A patch constant function writes tessellation factors. These are an array in SPIR-V, but in SM 5.x each factor is declared as a separate register, and these are dynamically indexed by the fork/join instance id. Elimination of multiple fork/join phases converts the indices to constants, but merging the signature elements into a single arrayed element matches the SPIR-V output. All references to input/output register indices are converted to element indices. If a relative address is present, the element index is moved up a slot so it cannot be confused with a constant offset. Existing code only handles register index relative addressing for tessellation factors. This patch adds generic support for it.
2023-04-25 22:27:08 -07:00
id_idx = shader_register_normalise_arrayed_addressing(reg, id_idx, e->register_index);
reg->idx[id_idx].offset = element_idx;
reg->idx_count = id_idx + 1;
vkd3d-shader/ir: Pass a uint32_t write mask to vkd3d_write_mask_get_component_idx().
2023-12-05 13:19:07 -08:00
if ((component_idx = vsir_write_mask_get_component_idx(e->mask)))
vkd3d-shader/ir: Normalise signatures and input/output registers to the Shader Model 6 pattern. In Shader Model 6 each signature element can span a range of register indices, or 'rows', and system values do not share a register index with non-system values. Inputs and outputs are referenced by element index instead of register index. This patch merges multiple signature elements into a single element under the following conditions: - The register index in a load or store is specified dynamically by including a relative address parameter with a base register index. The dcl_index_range instruction is used to identify these. - A register declaration is split across multiple elements which declare different components of the register. - A patch constant function writes tessellation factors. These are an array in SPIR-V, but in SM 5.x each factor is declared as a separate register, and these are dynamically indexed by the fork/join instance id. Elimination of multiple fork/join phases converts the indices to constants, but merging the signature elements into a single arrayed element matches the SPIR-V output. All references to input/output register indices are converted to element indices. If a relative address is present, the element index is moved up a slot so it cannot be confused with a constant offset. Existing code only handles register index relative addressing for tessellation factors. This patch adds generic support for it.
2023-04-25 22:27:08 -07:00
{
for (i = 0; i < VKD3D_VEC4_SIZE; ++i)
vkd3d-shader/ir: Pass a uint32_t swizzle to vkd3d_swizzle_get_component().
2023-12-05 14:05:40 -08:00
if (vsir_swizzle_get_component(src_param->swizzle, i))
vkd3d-shader/ir: Normalise signatures and input/output registers to the Shader Model 6 pattern. In Shader Model 6 each signature element can span a range of register indices, or 'rows', and system values do not share a register index with non-system values. Inputs and outputs are referenced by element index instead of register index. This patch merges multiple signature elements into a single element under the following conditions: - The register index in a load or store is specified dynamically by including a relative address parameter with a base register index. The dcl_index_range instruction is used to identify these. - A register declaration is split across multiple elements which declare different components of the register. - A patch constant function writes tessellation factors. These are an array in SPIR-V, but in SM 5.x each factor is declared as a separate register, and these are dynamically indexed by the fork/join instance id. Elimination of multiple fork/join phases converts the indices to constants, but merging the signature elements into a single arrayed element matches the SPIR-V output. All references to input/output register indices are converted to element indices. If a relative address is present, the element index is moved up a slot so it cannot be confused with a constant offset. Existing code only handles register index relative addressing for tessellation factors. This patch adds generic support for it.
2023-04-25 22:27:08 -07:00
src_param->swizzle -= component_idx << VKD3D_SHADER_SWIZZLE_SHIFT(i);
}
}
static void shader_instruction_normalise_io_params(struct vkd3d_shader_instruction *ins,
struct io_normaliser *normaliser)
{
struct vkd3d_shader_register *reg;
unsigned int i;
switch (ins->handler_idx)
{
case VKD3DSIH_DCL_INPUT:
if (normaliser->shader_type == VKD3D_SHADER_TYPE_HULL)
{
reg = &ins->declaration.dst.reg;
vkd3d-shader/ir: Check for vocp usage during IR normalization. The hull shader barrier used for this was broken by I/O normalization, since vocp is no longer exposed to the spirv backend. Restore this barrier by checking for vocp during normalization instead.
2023-07-16 21:34:04 -07:00
if (reg->type == VKD3DSPR_OUTCONTROLPOINT)
normaliser->use_vocp = true;
vkd3d-shader/ir: Normalise signatures and input/output registers to the Shader Model 6 pattern. In Shader Model 6 each signature element can span a range of register indices, or 'rows', and system values do not share a register index with non-system values. Inputs and outputs are referenced by element index instead of register index. This patch merges multiple signature elements into a single element under the following conditions: - The register index in a load or store is specified dynamically by including a relative address parameter with a base register index. The dcl_index_range instruction is used to identify these. - A register declaration is split across multiple elements which declare different components of the register. - A patch constant function writes tessellation factors. These are an array in SPIR-V, but in SM 5.x each factor is declared as a separate register, and these are dynamically indexed by the fork/join instance id. Elimination of multiple fork/join phases converts the indices to constants, but merging the signature elements into a single arrayed element matches the SPIR-V output. All references to input/output register indices are converted to element indices. If a relative address is present, the element index is moved up a slot so it cannot be confused with a constant offset. Existing code only handles register index relative addressing for tessellation factors. This patch adds generic support for it.
2023-04-25 22:27:08 -07:00
/* We don't need to keep OUTCONTROLPOINT or PATCHCONST input declarations since their
* equivalents were declared earlier, but INCONTROLPOINT may be the first occurrence. */
if (reg->type == VKD3DSPR_OUTCONTROLPOINT || reg->type == VKD3DSPR_PATCHCONST)
vkd3d_shader_instruction_make_nop(ins);
else if (reg->type == VKD3DSPR_INCONTROLPOINT)
reg->type = VKD3DSPR_INPUT;
}
/* fall through */
case VKD3DSIH_DCL_INPUT_PS:
case VKD3DSIH_DCL_OUTPUT:
vkd3d-shader/ir: Simplify the control flow in shader_instruction_normalise_io_params().
2023-09-08 07:07:45 -07:00
if (!shader_dst_param_io_normalise(&ins->declaration.dst, true, normaliser))
vkd3d_shader_instruction_make_nop(ins);
vkd3d-shader/ir: Normalise signatures and input/output registers to the Shader Model 6 pattern. In Shader Model 6 each signature element can span a range of register indices, or 'rows', and system values do not share a register index with non-system values. Inputs and outputs are referenced by element index instead of register index. This patch merges multiple signature elements into a single element under the following conditions: - The register index in a load or store is specified dynamically by including a relative address parameter with a base register index. The dcl_index_range instruction is used to identify these. - A register declaration is split across multiple elements which declare different components of the register. - A patch constant function writes tessellation factors. These are an array in SPIR-V, but in SM 5.x each factor is declared as a separate register, and these are dynamically indexed by the fork/join instance id. Elimination of multiple fork/join phases converts the indices to constants, but merging the signature elements into a single arrayed element matches the SPIR-V output. All references to input/output register indices are converted to element indices. If a relative address is present, the element index is moved up a slot so it cannot be confused with a constant offset. Existing code only handles register index relative addressing for tessellation factors. This patch adds generic support for it.
2023-04-25 22:27:08 -07:00
break;
case VKD3DSIH_DCL_INPUT_SGV:
case VKD3DSIH_DCL_INPUT_SIV:
case VKD3DSIH_DCL_INPUT_PS_SGV:
case VKD3DSIH_DCL_INPUT_PS_SIV:
case VKD3DSIH_DCL_OUTPUT_SIV:
vkd3d-shader/ir: Simplify the control flow in shader_instruction_normalise_io_params().
2023-09-08 07:07:45 -07:00
if (!shader_dst_param_io_normalise(&ins->declaration.register_semantic.reg, true, normaliser))
vkd3d_shader_instruction_make_nop(ins);
vkd3d-shader/ir: Normalise signatures and input/output registers to the Shader Model 6 pattern. In Shader Model 6 each signature element can span a range of register indices, or 'rows', and system values do not share a register index with non-system values. Inputs and outputs are referenced by element index instead of register index. This patch merges multiple signature elements into a single element under the following conditions: - The register index in a load or store is specified dynamically by including a relative address parameter with a base register index. The dcl_index_range instruction is used to identify these. - A register declaration is split across multiple elements which declare different components of the register. - A patch constant function writes tessellation factors. These are an array in SPIR-V, but in SM 5.x each factor is declared as a separate register, and these are dynamically indexed by the fork/join instance id. Elimination of multiple fork/join phases converts the indices to constants, but merging the signature elements into a single arrayed element matches the SPIR-V output. All references to input/output register indices are converted to element indices. If a relative address is present, the element index is moved up a slot so it cannot be confused with a constant offset. Existing code only handles register index relative addressing for tessellation factors. This patch adds generic support for it.
2023-04-25 22:27:08 -07:00
break;
case VKD3DSIH_HS_CONTROL_POINT_PHASE:
case VKD3DSIH_HS_FORK_PHASE:
case VKD3DSIH_HS_JOIN_PHASE:
normaliser->phase = ins->handler_idx;
memset(normaliser->input_dcl_params, 0, sizeof(normaliser->input_dcl_params));
memset(normaliser->output_dcl_params, 0, sizeof(normaliser->output_dcl_params));
memset(normaliser->pc_dcl_params, 0, sizeof(normaliser->pc_dcl_params));
break;
default:
if (shader_instruction_is_dcl(ins))
break;
for (i = 0; i < ins->dst_count; ++i)
vkd3d-shader: Make *src and *dst mutable in vkd3d_shader_instruction. They were originally made const because no optimization/normalization pass existed. Now having to cast away const all the time is becoming more and more burdening.
2024-01-11 02:19:39 -08:00
shader_dst_param_io_normalise(&ins->dst[i], false, normaliser);
vkd3d-shader/ir: Normalise signatures and input/output registers to the Shader Model 6 pattern. In Shader Model 6 each signature element can span a range of register indices, or 'rows', and system values do not share a register index with non-system values. Inputs and outputs are referenced by element index instead of register index. This patch merges multiple signature elements into a single element under the following conditions: - The register index in a load or store is specified dynamically by including a relative address parameter with a base register index. The dcl_index_range instruction is used to identify these. - A register declaration is split across multiple elements which declare different components of the register. - A patch constant function writes tessellation factors. These are an array in SPIR-V, but in SM 5.x each factor is declared as a separate register, and these are dynamically indexed by the fork/join instance id. Elimination of multiple fork/join phases converts the indices to constants, but merging the signature elements into a single arrayed element matches the SPIR-V output. All references to input/output register indices are converted to element indices. If a relative address is present, the element index is moved up a slot so it cannot be confused with a constant offset. Existing code only handles register index relative addressing for tessellation factors. This patch adds generic support for it.
2023-04-25 22:27:08 -07:00
for (i = 0; i < ins->src_count; ++i)
vkd3d-shader: Make *src and *dst mutable in vkd3d_shader_instruction. They were originally made const because no optimization/normalization pass existed. Now having to cast away const all the time is becoming more and more burdening.
2024-01-11 02:19:39 -08:00
shader_src_param_io_normalise(&ins->src[i], normaliser);
vkd3d-shader/ir: Normalise signatures and input/output registers to the Shader Model 6 pattern. In Shader Model 6 each signature element can span a range of register indices, or 'rows', and system values do not share a register index with non-system values. Inputs and outputs are referenced by element index instead of register index. This patch merges multiple signature elements into a single element under the following conditions: - The register index in a load or store is specified dynamically by including a relative address parameter with a base register index. The dcl_index_range instruction is used to identify these. - A register declaration is split across multiple elements which declare different components of the register. - A patch constant function writes tessellation factors. These are an array in SPIR-V, but in SM 5.x each factor is declared as a separate register, and these are dynamically indexed by the fork/join instance id. Elimination of multiple fork/join phases converts the indices to constants, but merging the signature elements into a single arrayed element matches the SPIR-V output. All references to input/output register indices are converted to element indices. If a relative address is present, the element index is moved up a slot so it cannot be confused with a constant offset. Existing code only handles register index relative addressing for tessellation factors. This patch adds generic support for it.
2023-04-25 22:27:08 -07:00
break;
}
}
vkd3d-shader/ir: Pass a vkd3d_shader_parser to instruction_array_normalise_io_registers().
2023-07-16 21:27:52 -07:00
static enum vkd3d_result shader_normalise_io_registers(struct vkd3d_shader_parser *parser)
vkd3d-shader/ir: Normalise signatures and input/output registers to the Shader Model 6 pattern. In Shader Model 6 each signature element can span a range of register indices, or 'rows', and system values do not share a register index with non-system values. Inputs and outputs are referenced by element index instead of register index. This patch merges multiple signature elements into a single element under the following conditions: - The register index in a load or store is specified dynamically by including a relative address parameter with a base register index. The dcl_index_range instruction is used to identify these. - A register declaration is split across multiple elements which declare different components of the register. - A patch constant function writes tessellation factors. These are an array in SPIR-V, but in SM 5.x each factor is declared as a separate register, and these are dynamically indexed by the fork/join instance id. Elimination of multiple fork/join phases converts the indices to constants, but merging the signature elements into a single arrayed element matches the SPIR-V output. All references to input/output register indices are converted to element indices. If a relative address is present, the element index is moved up a slot so it cannot be confused with a constant offset. Existing code only handles register index relative addressing for tessellation factors. This patch adds generic support for it.
2023-04-25 22:27:08 -07:00
{
vkd3d-shader/ir: Introduce struct vsir_program.
2024-01-16 05:47:34 -08:00
struct io_normaliser normaliser = {parser->program.instructions};
vkd3d-shader/ir: Store the "use_vocp" field in struct vsir_program.
2024-01-17 11:39:55 -08:00
struct vsir_program *program = &parser->program;
vkd3d-shader/ir: Normalise signatures and input/output registers to the Shader Model 6 pattern. In Shader Model 6 each signature element can span a range of register indices, or 'rows', and system values do not share a register index with non-system values. Inputs and outputs are referenced by element index instead of register index. This patch merges multiple signature elements into a single element under the following conditions: - The register index in a load or store is specified dynamically by including a relative address parameter with a base register index. The dcl_index_range instruction is used to identify these. - A register declaration is split across multiple elements which declare different components of the register. - A patch constant function writes tessellation factors. These are an array in SPIR-V, but in SM 5.x each factor is declared as a separate register, and these are dynamically indexed by the fork/join instance id. Elimination of multiple fork/join phases converts the indices to constants, but merging the signature elements into a single arrayed element matches the SPIR-V output. All references to input/output register indices are converted to element indices. If a relative address is present, the element index is moved up a slot so it cannot be confused with a constant offset. Existing code only handles register index relative addressing for tessellation factors. This patch adds generic support for it.
2023-04-25 22:27:08 -07:00
struct vkd3d_shader_instruction *ins;
bool has_control_point_phase;
unsigned int i, j;
normaliser.phase = VKD3DSIH_INVALID;
vkd3d-shader/ir: Store the "use_vocp" field in struct vsir_program.
2024-01-17 11:39:55 -08:00
normaliser.shader_type = program->shader_version.type;
normaliser.major = program->shader_version.major;
vkd3d-shader/ir: Pass a vkd3d_shader_parser to instruction_array_normalise_io_registers().
2023-07-16 21:27:52 -07:00
normaliser.input_signature = &parser->shader_desc.input_signature;
normaliser.output_signature = &parser->shader_desc.output_signature;
normaliser.patch_constant_signature = &parser->shader_desc.patch_constant_signature;
vkd3d-shader/ir: Normalise signatures and input/output registers to the Shader Model 6 pattern. In Shader Model 6 each signature element can span a range of register indices, or 'rows', and system values do not share a register index with non-system values. Inputs and outputs are referenced by element index instead of register index. This patch merges multiple signature elements into a single element under the following conditions: - The register index in a load or store is specified dynamically by including a relative address parameter with a base register index. The dcl_index_range instruction is used to identify these. - A register declaration is split across multiple elements which declare different components of the register. - A patch constant function writes tessellation factors. These are an array in SPIR-V, but in SM 5.x each factor is declared as a separate register, and these are dynamically indexed by the fork/join instance id. Elimination of multiple fork/join phases converts the indices to constants, but merging the signature elements into a single arrayed element matches the SPIR-V output. All references to input/output register indices are converted to element indices. If a relative address is present, the element index is moved up a slot so it cannot be confused with a constant offset. Existing code only handles register index relative addressing for tessellation factors. This patch adds generic support for it.
2023-04-25 22:27:08 -07:00
vkd3d-shader/ir: Store the "use_vocp" field in struct vsir_program.
2024-01-17 11:39:55 -08:00
for (i = 0, has_control_point_phase = false; i < program->instructions.count; ++i)
vkd3d-shader/ir: Normalise signatures and input/output registers to the Shader Model 6 pattern. In Shader Model 6 each signature element can span a range of register indices, or 'rows', and system values do not share a register index with non-system values. Inputs and outputs are referenced by element index instead of register index. This patch merges multiple signature elements into a single element under the following conditions: - The register index in a load or store is specified dynamically by including a relative address parameter with a base register index. The dcl_index_range instruction is used to identify these. - A register declaration is split across multiple elements which declare different components of the register. - A patch constant function writes tessellation factors. These are an array in SPIR-V, but in SM 5.x each factor is declared as a separate register, and these are dynamically indexed by the fork/join instance id. Elimination of multiple fork/join phases converts the indices to constants, but merging the signature elements into a single arrayed element matches the SPIR-V output. All references to input/output register indices are converted to element indices. If a relative address is present, the element index is moved up a slot so it cannot be confused with a constant offset. Existing code only handles register index relative addressing for tessellation factors. This patch adds generic support for it.
2023-04-25 22:27:08 -07:00
{
vkd3d-shader/ir: Store the "use_vocp" field in struct vsir_program.
2024-01-17 11:39:55 -08:00
ins = &program->instructions.elements[i];
vkd3d-shader/ir: Normalise signatures and input/output registers to the Shader Model 6 pattern. In Shader Model 6 each signature element can span a range of register indices, or 'rows', and system values do not share a register index with non-system values. Inputs and outputs are referenced by element index instead of register index. This patch merges multiple signature elements into a single element under the following conditions: - The register index in a load or store is specified dynamically by including a relative address parameter with a base register index. The dcl_index_range instruction is used to identify these. - A register declaration is split across multiple elements which declare different components of the register. - A patch constant function writes tessellation factors. These are an array in SPIR-V, but in SM 5.x each factor is declared as a separate register, and these are dynamically indexed by the fork/join instance id. Elimination of multiple fork/join phases converts the indices to constants, but merging the signature elements into a single arrayed element matches the SPIR-V output. All references to input/output register indices are converted to element indices. If a relative address is present, the element index is moved up a slot so it cannot be confused with a constant offset. Existing code only handles register index relative addressing for tessellation factors. This patch adds generic support for it.
2023-04-25 22:27:08 -07:00
switch (ins->handler_idx)
{
case VKD3DSIH_DCL_OUTPUT_CONTROL_POINT_COUNT:
normaliser.output_control_point_count = ins->declaration.count;
break;
case VKD3DSIH_DCL_INDEX_RANGE:
io_normaliser_add_index_range(&normaliser, ins);
vkd3d_shader_instruction_make_nop(ins);
break;
case VKD3DSIH_HS_CONTROL_POINT_PHASE:
has_control_point_phase = true;
/* fall through */
case VKD3DSIH_HS_FORK_PHASE:
case VKD3DSIH_HS_JOIN_PHASE:
normaliser.phase = ins->handler_idx;
break;
default:
break;
}
}
if (normaliser.shader_type == VKD3D_SHADER_TYPE_HULL && !has_control_point_phase)
{
/* Inputs and outputs must match for the default phase, so merge ranges must match too. */
for (i = 0; i < MAX_REG_OUTPUT; ++i)
{
for (j = 0; j < VKD3D_VEC4_SIZE; ++j)
{
if (!normaliser.input_range_map[i][j] && normaliser.output_range_map[i][j])
normaliser.input_range_map[i][j] = normaliser.output_range_map[i][j];
else if (normaliser.input_range_map[i][j] && !normaliser.output_range_map[i][j])
normaliser.output_range_map[i][j] = normaliser.input_range_map[i][j];
else assert(normaliser.input_range_map[i][j] == normaliser.output_range_map[i][j]);
}
}
}
vkd3d-shader/ir: Pass a vkd3d_shader_parser to instruction_array_normalise_io_registers().
2023-07-16 21:27:52 -07:00
if (!shader_signature_merge(&parser->shader_desc.input_signature, normaliser.input_range_map, false)
|| !shader_signature_merge(&parser->shader_desc.output_signature, normaliser.output_range_map, false)
|| !shader_signature_merge(&parser->shader_desc.patch_constant_signature, normaliser.pc_range_map, true))
vkd3d-shader/ir: Normalise signatures and input/output registers to the Shader Model 6 pattern. In Shader Model 6 each signature element can span a range of register indices, or 'rows', and system values do not share a register index with non-system values. Inputs and outputs are referenced by element index instead of register index. This patch merges multiple signature elements into a single element under the following conditions: - The register index in a load or store is specified dynamically by including a relative address parameter with a base register index. The dcl_index_range instruction is used to identify these. - A register declaration is split across multiple elements which declare different components of the register. - A patch constant function writes tessellation factors. These are an array in SPIR-V, but in SM 5.x each factor is declared as a separate register, and these are dynamically indexed by the fork/join instance id. Elimination of multiple fork/join phases converts the indices to constants, but merging the signature elements into a single arrayed element matches the SPIR-V output. All references to input/output register indices are converted to element indices. If a relative address is present, the element index is moved up a slot so it cannot be confused with a constant offset. Existing code only handles register index relative addressing for tessellation factors. This patch adds generic support for it.
2023-04-25 22:27:08 -07:00
{
vkd3d-shader/ir: Store the "use_vocp" field in struct vsir_program.
2024-01-17 11:39:55 -08:00
program->instructions = normaliser.instructions;
vkd3d-shader/ir: Normalise signatures and input/output registers to the Shader Model 6 pattern. In Shader Model 6 each signature element can span a range of register indices, or 'rows', and system values do not share a register index with non-system values. Inputs and outputs are referenced by element index instead of register index. This patch merges multiple signature elements into a single element under the following conditions: - The register index in a load or store is specified dynamically by including a relative address parameter with a base register index. The dcl_index_range instruction is used to identify these. - A register declaration is split across multiple elements which declare different components of the register. - A patch constant function writes tessellation factors. These are an array in SPIR-V, but in SM 5.x each factor is declared as a separate register, and these are dynamically indexed by the fork/join instance id. Elimination of multiple fork/join phases converts the indices to constants, but merging the signature elements into a single arrayed element matches the SPIR-V output. All references to input/output register indices are converted to element indices. If a relative address is present, the element index is moved up a slot so it cannot be confused with a constant offset. Existing code only handles register index relative addressing for tessellation factors. This patch adds generic support for it.
2023-04-25 22:27:08 -07:00
return VKD3D_ERROR_OUT_OF_MEMORY;
}
normaliser.phase = VKD3DSIH_INVALID;
for (i = 0; i < normaliser.instructions.count; ++i)
shader_instruction_normalise_io_params(&normaliser.instructions.elements[i], &normaliser);
vkd3d-shader/ir: Store the "use_vocp" field in struct vsir_program.
2024-01-17 11:39:55 -08:00
program->instructions = normaliser.instructions;
program->use_vocp = normaliser.use_vocp;
vkd3d-shader/ir: Normalise signatures and input/output registers to the Shader Model 6 pattern. In Shader Model 6 each signature element can span a range of register indices, or 'rows', and system values do not share a register index with non-system values. Inputs and outputs are referenced by element index instead of register index. This patch merges multiple signature elements into a single element under the following conditions: - The register index in a load or store is specified dynamically by including a relative address parameter with a base register index. The dcl_index_range instruction is used to identify these. - A register declaration is split across multiple elements which declare different components of the register. - A patch constant function writes tessellation factors. These are an array in SPIR-V, but in SM 5.x each factor is declared as a separate register, and these are dynamically indexed by the fork/join instance id. Elimination of multiple fork/join phases converts the indices to constants, but merging the signature elements into a single arrayed element matches the SPIR-V output. All references to input/output register indices are converted to element indices. If a relative address is present, the element index is moved up a slot so it cannot be confused with a constant offset. Existing code only handles register index relative addressing for tessellation factors. This patch adds generic support for it.
2023-04-25 22:27:08 -07:00
return VKD3D_OK;
}
vkd3d-shader/ir: Move normalization code from spirv.c to ir.c. It is not spirv-specific and will (presumably) be used for GLSL as well.
2023-07-02 18:23:07 -07:00
vkd3d-shader/ir: Normalise sm1-style constants.
2023-07-09 15:46:04 -07:00
struct flat_constant_def
{
enum vkd3d_shader_d3dbc_constant_register set;
uint32_t index;
uint32_t value[4];
};
struct flat_constants_normaliser
{
struct flat_constant_def *defs;
size_t def_count, defs_capacity;
};
static bool get_flat_constant_register_type(const struct vkd3d_shader_register *reg,
enum vkd3d_shader_d3dbc_constant_register *set, uint32_t *index)
{
static const struct
{
enum vkd3d_shader_register_type type;
enum vkd3d_shader_d3dbc_constant_register set;
uint32_t offset;
}
regs[] =
{
{VKD3DSPR_CONST, VKD3D_SHADER_D3DBC_FLOAT_CONSTANT_REGISTER, 0},
{VKD3DSPR_CONST2, VKD3D_SHADER_D3DBC_FLOAT_CONSTANT_REGISTER, 2048},
{VKD3DSPR_CONST3, VKD3D_SHADER_D3DBC_FLOAT_CONSTANT_REGISTER, 4096},
{VKD3DSPR_CONST4, VKD3D_SHADER_D3DBC_FLOAT_CONSTANT_REGISTER, 6144},
{VKD3DSPR_CONSTINT, VKD3D_SHADER_D3DBC_INT_CONSTANT_REGISTER, 0},
{VKD3DSPR_CONSTBOOL, VKD3D_SHADER_D3DBC_BOOL_CONSTANT_REGISTER, 0},
};
unsigned int i;
for (i = 0; i < ARRAY_SIZE(regs); ++i)
{
if (reg->type == regs[i].type)
{
if (reg->idx[0].rel_addr)
{
FIXME("Unhandled relative address.\n");
return false;
}
*set = regs[i].set;
*index = regs[i].offset + reg->idx[0].offset;
return true;
}
}
return false;
}
static void shader_register_normalise_flat_constants(struct vkd3d_shader_src_param *param,
const struct flat_constants_normaliser *normaliser)
{
enum vkd3d_shader_d3dbc_constant_register set;
uint32_t index;
size_t i, j;
if (!get_flat_constant_register_type(&param->reg, &set, &index))
return;
for (i = 0; i < normaliser->def_count; ++i)
{
if (normaliser->defs[i].set == set && normaliser->defs[i].index == index)
{
param->reg.type = VKD3DSPR_IMMCONST;
param->reg.idx_count = 0;
vkd3d-shader: Turn vkd3d_shader_register.immconst_type into vkd3d_shader_register.dimension.
2023-08-14 10:21:41 -07:00
param->reg.dimension = VSIR_DIMENSION_VEC4;
vkd3d-shader/ir: Normalise sm1-style constants.
2023-07-09 15:46:04 -07:00
for (j = 0; j < 4; ++j)
vkd3d-shader/ir: Rename the "immconst_uint" field of struct vkd3d_shader_register to "immconst_u32". For consistency with the rest of vkd3d-shader; e.g. put_u32() and read_u32().
2023-12-05 14:24:36 -08:00
param->reg.u.immconst_u32[j] = normaliser->defs[i].value[j];
vkd3d-shader/ir: Normalise sm1-style constants.
2023-07-09 15:46:04 -07:00
return;
}
}
param->reg.type = VKD3DSPR_CONSTBUFFER;
param->reg.idx[0].offset = set; /* register ID */
param->reg.idx[1].offset = set; /* register index */
param->reg.idx[2].offset = index; /* buffer index */
param->reg.idx_count = 3;
}
vkd3d-shader/ir: Introduce struct vsir_program.
2024-01-16 05:47:34 -08:00
static enum vkd3d_result instruction_array_normalise_flat_constants(struct vsir_program *program)
vkd3d-shader/ir: Normalise sm1-style constants.
2023-07-09 15:46:04 -07:00
{
vkd3d-shader/ir: Introduce struct vsir_program.
2024-01-16 05:47:34 -08:00
struct flat_constants_normaliser normaliser = {0};
vkd3d-shader/ir: Normalise sm1-style constants.
2023-07-09 15:46:04 -07:00
unsigned int i, j;
vkd3d-shader/ir: Introduce struct vsir_program.
2024-01-16 05:47:34 -08:00
for (i = 0; i < program->instructions.count; ++i)
vkd3d-shader/ir: Normalise sm1-style constants.
2023-07-09 15:46:04 -07:00
{
vkd3d-shader/ir: Introduce struct vsir_program.
2024-01-16 05:47:34 -08:00
struct vkd3d_shader_instruction *ins = &program->instructions.elements[i];
vkd3d-shader/ir: Normalise sm1-style constants.
2023-07-09 15:46:04 -07:00
if (ins->handler_idx == VKD3DSIH_DEF || ins->handler_idx == VKD3DSIH_DEFI || ins->handler_idx == VKD3DSIH_DEFB)
{
struct flat_constant_def *def;
if (!vkd3d_array_reserve((void **)&normaliser.defs, &normaliser.defs_capacity,
normaliser.def_count + 1, sizeof(*normaliser.defs)))
{
vkd3d_free(normaliser.defs);
return VKD3D_ERROR_OUT_OF_MEMORY;
}
def = &normaliser.defs[normaliser.def_count++];
get_flat_constant_register_type((struct vkd3d_shader_register *)&ins->dst[0].reg, &def->set, &def->index);
for (j = 0; j < 4; ++j)
vkd3d-shader/ir: Rename the "immconst_uint" field of struct vkd3d_shader_register to "immconst_u32". For consistency with the rest of vkd3d-shader; e.g. put_u32() and read_u32().
2023-12-05 14:24:36 -08:00
def->value[j] = ins->src[0].reg.u.immconst_u32[j];
vkd3d-shader/ir: Normalise sm1-style constants.
2023-07-09 15:46:04 -07:00
vkd3d_shader_instruction_make_nop(ins);
}
else
{
for (j = 0; j < ins->src_count; ++j)
vkd3d-shader: Make *src and *dst mutable in vkd3d_shader_instruction. They were originally made const because no optimization/normalization pass existed. Now having to cast away const all the time is becoming more and more burdening.
2024-01-11 02:19:39 -08:00
shader_register_normalise_flat_constants(&ins->src[j], &normaliser);
vkd3d-shader/ir: Normalise sm1-style constants.
2023-07-09 15:46:04 -07:00
}
}
vkd3d_free(normaliser.defs);
return VKD3D_OK;
}
vkd3d-shader/ir: Introduce struct vsir_program.
2024-01-16 05:47:34 -08:00
static void remove_dead_code(struct vsir_program *program)
vkd3d-shader/ir: Remove dead code during normalisation. The SPIR-V backend generates invalid SPIR-V code when VSIR has dead code (except for NOPs).
2023-09-20 13:10:39 -07:00
{
size_t i, depth = 0;
bool dead = false;
vkd3d-shader/ir: Introduce struct vsir_program.
2024-01-16 05:47:34 -08:00
for (i = 0; i < program->instructions.count; ++i)
vkd3d-shader/ir: Remove dead code during normalisation. The SPIR-V backend generates invalid SPIR-V code when VSIR has dead code (except for NOPs).
2023-09-20 13:10:39 -07:00
{
vkd3d-shader/ir: Introduce struct vsir_program.
2024-01-16 05:47:34 -08:00
struct vkd3d_shader_instruction *ins = &program->instructions.elements[i];
vkd3d-shader/ir: Remove dead code during normalisation. The SPIR-V backend generates invalid SPIR-V code when VSIR has dead code (except for NOPs).
2023-09-20 13:10:39 -07:00
switch (ins->handler_idx)
{
case VKD3DSIH_IF:
case VKD3DSIH_LOOP:
case VKD3DSIH_SWITCH:
if (dead)
{
vkd3d_shader_instruction_make_nop(ins);
++depth;
}
break;
case VKD3DSIH_ENDIF:
case VKD3DSIH_ENDLOOP:
case VKD3DSIH_ENDSWITCH:
case VKD3DSIH_ELSE:
if (dead)
{
if (depth > 0)
{
if (ins->handler_idx != VKD3DSIH_ELSE)
--depth;
vkd3d-shader/ir: Check the handler before changing it to NOP in remove_dead_code().
2023-11-08 20:07:03 -08:00
vkd3d_shader_instruction_make_nop(ins);
vkd3d-shader/ir: Remove dead code during normalisation. The SPIR-V backend generates invalid SPIR-V code when VSIR has dead code (except for NOPs).
2023-09-20 13:10:39 -07:00
}
else
{
dead = false;
}
}
break;
/* `depth' is counted with respect to where the dead code
* segment began. So it starts at zero and it signals the
* termination of the dead code segment when it would
* become negative. */
case VKD3DSIH_BREAK:
case VKD3DSIH_RET:
case VKD3DSIH_CONTINUE:
if (dead)
{
vkd3d_shader_instruction_make_nop(ins);
}
else
{
dead = true;
depth = 0;
}
break;
/* If `case' or `default' appears at zero depth, it means
* that they are a possible target for the corresponding
* switch, so the code is live again. */
case VKD3DSIH_CASE:
case VKD3DSIH_DEFAULT:
if (dead)
{
if (depth == 0)
dead = false;
else
vkd3d_shader_instruction_make_nop(ins);
}
break;
/* Phase instructions can only appear in hull shaders and
* outside of any block. When a phase returns, control is
* moved to the following phase, so they make code live
* again. */
case VKD3DSIH_HS_CONTROL_POINT_PHASE:
case VKD3DSIH_HS_FORK_PHASE:
case VKD3DSIH_HS_JOIN_PHASE:
dead = false;
break;
default:
if (dead)
vkd3d_shader_instruction_make_nop(ins);
break;
}
}
}
vkd3d-shader/ir: Translate TEX instructions to SAMPLE.
2023-08-11 14:46:03 -07:00
static enum vkd3d_result normalise_combined_samplers(struct vkd3d_shader_parser *parser)
{
unsigned int i;
vkd3d-shader/ir: Introduce struct vsir_program.
2024-01-16 05:47:34 -08:00
for (i = 0; i < parser->program.instructions.count; ++i)
vkd3d-shader/ir: Translate TEX instructions to SAMPLE.
2023-08-11 14:46:03 -07:00
{
vkd3d-shader/ir: Introduce struct vsir_program.
2024-01-16 05:47:34 -08:00
struct vkd3d_shader_instruction *ins = &parser->program.instructions.elements[i];
vkd3d-shader/ir: Translate TEX instructions to SAMPLE.
2023-08-11 14:46:03 -07:00
struct vkd3d_shader_src_param *srcs;
switch (ins->handler_idx)
{
case VKD3DSIH_TEX:
vkd3d-shader/ir: Introduce struct vsir_program.
2024-01-16 05:47:34 -08:00
if (!(srcs = shader_src_param_allocator_get(&parser->program.instructions.src_params, 3)))
vkd3d-shader/ir: Translate TEX instructions to SAMPLE.
2023-08-11 14:46:03 -07:00
return VKD3D_ERROR_OUT_OF_MEMORY;
memset(srcs, 0, sizeof(*srcs) * 3);
ins->handler_idx = VKD3DSIH_SAMPLE;
srcs[0] = ins->src[0];
srcs[1].reg.type = VKD3DSPR_RESOURCE;
srcs[1].reg.idx[0] = ins->src[1].reg.idx[0];
srcs[1].reg.idx[1] = ins->src[1].reg.idx[0];
srcs[1].reg.idx_count = 2;
srcs[1].reg.data_type = VKD3D_DATA_RESOURCE;
srcs[1].swizzle = VKD3D_SHADER_NO_SWIZZLE;
srcs[2].reg.type = VKD3DSPR_SAMPLER;
srcs[2].reg.idx[0] = ins->src[1].reg.idx[0];
srcs[2].reg.idx[1] = ins->src[1].reg.idx[0];
srcs[2].reg.idx_count = 2;
srcs[2].reg.data_type = VKD3D_DATA_SAMPLER;
ins->src = srcs;
ins->src_count = 3;
break;
case VKD3DSIH_TEXBEM:
case VKD3DSIH_TEXBEML:
case VKD3DSIH_TEXCOORD:
case VKD3DSIH_TEXDEPTH:
case VKD3DSIH_TEXDP3:
case VKD3DSIH_TEXDP3TEX:
case VKD3DSIH_TEXLDD:
case VKD3DSIH_TEXLDL:
case VKD3DSIH_TEXM3x2PAD:
case VKD3DSIH_TEXM3x2TEX:
case VKD3DSIH_TEXM3x3DIFF:
case VKD3DSIH_TEXM3x3PAD:
case VKD3DSIH_TEXM3x3SPEC:
case VKD3DSIH_TEXM3x3TEX:
case VKD3DSIH_TEXM3x3VSPEC:
case VKD3DSIH_TEXREG2AR:
case VKD3DSIH_TEXREG2GB:
case VKD3DSIH_TEXREG2RGB:
vkd3d_shader_parser_error(parser, VKD3D_SHADER_ERROR_VSIR_NOT_IMPLEMENTED,
"Aborting due to not yet implemented feature: "
"Combined sampler instruction %#x.", ins->handler_idx);
return VKD3D_ERROR_NOT_IMPLEMENTED;
default:
break;
}
}
return VKD3D_OK;
}
vkd3d-shader/ir: Flatten IF/ELSE/ENDIF control flow instructions.
2024-01-04 06:55:51 -08:00
struct cf_flattener_if_info
{
struct vkd3d_shader_src_param *false_param;
vkd3d-shader/ir: Store code block names in struct vkd3d_shader_desc.
2023-11-07 19:14:01 -08:00
unsigned int id;
vkd3d-shader/ir: Flatten IF/ELSE/ENDIF control flow instructions.
2024-01-04 06:55:51 -08:00
uint32_t merge_block_id;
unsigned int else_block_id;
};
vkd3d-shader/ir: Flatten LOOP/BREAK/CONTINUE/ENDLOOP control flow instructions.
2023-12-11 21:34:51 -08:00
struct cf_flattener_loop_info
{
unsigned int header_block_id;
unsigned int continue_block_id;
uint32_t merge_block_id;
};
vkd3d-shader/ir: Flatten SWITCH/CASE/DEFAULT/ENDSWITCH control flow instructions.
2023-12-11 21:58:08 -08:00
struct cf_flattener_switch_case
{
unsigned int value;
unsigned int block_id;
};
struct cf_flattener_switch_info
{
size_t ins_location;
const struct vkd3d_shader_src_param *condition;
vkd3d-shader/ir: Store code block names in struct vkd3d_shader_desc.
2023-11-07 19:14:01 -08:00
unsigned int id;
vkd3d-shader/ir: Flatten SWITCH/CASE/DEFAULT/ENDSWITCH control flow instructions.
2023-12-11 21:58:08 -08:00
unsigned int merge_block_id;
unsigned int default_block_id;
struct cf_flattener_switch_case *cases;
size_t cases_size;
unsigned int cases_count;
};
vkd3d-shader/ir: Flatten IF/ELSE/ENDIF control flow instructions.
2024-01-04 06:55:51 -08:00
struct cf_flattener_info
{
union
{
struct cf_flattener_if_info if_;
vkd3d-shader/ir: Flatten LOOP/BREAK/CONTINUE/ENDLOOP control flow instructions.
2023-12-11 21:34:51 -08:00
struct cf_flattener_loop_info loop;
vkd3d-shader/ir: Flatten SWITCH/CASE/DEFAULT/ENDSWITCH control flow instructions.
2023-12-11 21:58:08 -08:00
struct cf_flattener_switch_info switch_;
vkd3d-shader/ir: Flatten IF/ELSE/ENDIF control flow instructions.
2024-01-04 06:55:51 -08:00
} u;
enum
{
VKD3D_BLOCK_IF,
vkd3d-shader/ir: Flatten LOOP/BREAK/CONTINUE/ENDLOOP control flow instructions.
2023-12-11 21:34:51 -08:00
VKD3D_BLOCK_LOOP,
VKD3D_BLOCK_SWITCH,
vkd3d-shader/ir: Flatten IF/ELSE/ENDIF control flow instructions.
2024-01-04 06:55:51 -08:00
} current_block;
bool inside_block;
};
struct cf_flattener
{
struct vkd3d_shader_parser *parser;
struct vkd3d_shader_location location;
bool allocation_failed;
struct vkd3d_shader_instruction *instructions;
size_t instruction_capacity;
size_t instruction_count;
unsigned int block_id;
vkd3d-shader/ir: Store code block names in struct vkd3d_shader_desc.
2023-11-07 19:14:01 -08:00
const char **block_names;
size_t block_name_capacity;
size_t block_name_count;
unsigned int branch_id;
unsigned int loop_id;
unsigned int switch_id;
vkd3d-shader/ir: Flatten IF/ELSE/ENDIF control flow instructions.
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unsigned int control_flow_depth;
struct cf_flattener_info *control_flow_info;
size_t control_flow_info_size;
};
static struct vkd3d_shader_instruction *cf_flattener_require_space(struct cf_flattener *flattener, size_t count)
{
if (!vkd3d_array_reserve((void **)&flattener->instructions, &flattener->instruction_capacity,
flattener->instruction_count + count, sizeof(*flattener->instructions)))
{
ERR("Failed to allocate instructions.\n");
flattener->allocation_failed = true;
return NULL;
}
return &flattener->instructions[flattener->instruction_count];
}
static bool cf_flattener_copy_instruction(struct cf_flattener *flattener,
const struct vkd3d_shader_instruction *instruction)
{
struct vkd3d_shader_instruction *dst_ins;
if (instruction->handler_idx == VKD3DSIH_NOP)
return true;
if (!(dst_ins = cf_flattener_require_space(flattener, 1)))
return false;
*dst_ins = *instruction;
++flattener->instruction_count;
return true;
}
static unsigned int cf_flattener_alloc_block_id(struct cf_flattener *flattener)
{
return ++flattener->block_id;
}
static struct vkd3d_shader_src_param *instruction_src_params_alloc(struct vkd3d_shader_instruction *ins,
unsigned int count, struct cf_flattener *flattener)
{
struct vkd3d_shader_src_param *params = shader_parser_get_src_params(flattener->parser, count);
if (!params)
{
flattener->allocation_failed = true;
return NULL;
}
ins->src = params;
ins->src_count = count;
return params;
}
static void cf_flattener_emit_label(struct cf_flattener *flattener, unsigned int label_id)
{
struct vkd3d_shader_instruction *ins;
if (!(ins = cf_flattener_require_space(flattener, 1)))
return;
if (vsir_instruction_init_label(ins, &flattener->location, label_id, flattener->parser))
++flattener->instruction_count;
else
flattener->allocation_failed = true;
}
/* For conditional branches, this returns the false target branch parameter. */
static struct vkd3d_shader_src_param *cf_flattener_emit_branch(struct cf_flattener *flattener,
vkd3d-shader/ir: Flatten LOOP/BREAK/CONTINUE/ENDLOOP control flow instructions.
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unsigned int merge_block_id, unsigned int continue_block_id,
const struct vkd3d_shader_src_param *condition, unsigned int true_id, unsigned int false_id,
vkd3d-shader/ir: Flatten IF/ELSE/ENDIF control flow instructions.
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unsigned int flags)
{
struct vkd3d_shader_src_param *src_params, *false_branch_param;
struct vkd3d_shader_instruction *ins;
if (!(ins = cf_flattener_require_space(flattener, 1)))
return NULL;
vsir_instruction_init(ins, &flattener->location, VKD3DSIH_BRANCH);
if (condition)
{
vkd3d-shader/ir: Flatten LOOP/BREAK/CONTINUE/ENDLOOP control flow instructions.
2023-12-11 21:34:51 -08:00
if (!(src_params = instruction_src_params_alloc(ins, 4 + !!continue_block_id, flattener)))
vkd3d-shader/ir: Flatten IF/ELSE/ENDIF control flow instructions.
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return NULL;
src_params[0] = *condition;
if (flags == VKD3D_SHADER_CONDITIONAL_OP_Z)
{
vsir_src_param_init_label(&src_params[1], false_id);
vsir_src_param_init_label(&src_params[2], true_id);
false_branch_param = &src_params[1];
}
else
{
vsir_src_param_init_label(&src_params[1], true_id);
vsir_src_param_init_label(&src_params[2], false_id);
false_branch_param = &src_params[2];
}
vsir_src_param_init_label(&src_params[3], merge_block_id);
vkd3d-shader/ir: Flatten LOOP/BREAK/CONTINUE/ENDLOOP control flow instructions.
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if (continue_block_id)
vsir_src_param_init_label(&src_params[4], continue_block_id);
vkd3d-shader/ir: Flatten IF/ELSE/ENDIF control flow instructions.
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}
else
{
vkd3d-shader/ir: Flatten LOOP/BREAK/CONTINUE/ENDLOOP control flow instructions.
2023-12-11 21:34:51 -08:00
if (!(src_params = instruction_src_params_alloc(ins, merge_block_id ? 3 : 1, flattener)))
vkd3d-shader/ir: Flatten IF/ELSE/ENDIF control flow instructions.
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return NULL;
vsir_src_param_init_label(&src_params[0], true_id);
vkd3d-shader/ir: Flatten LOOP/BREAK/CONTINUE/ENDLOOP control flow instructions.
2023-12-11 21:34:51 -08:00
if (merge_block_id)
{
/* An unconditional branch may only have merge information for a loop, which
* must have both a merge block and continue block. */
vsir_src_param_init_label(&src_params[1], merge_block_id);
vsir_src_param_init_label(&src_params[2], continue_block_id);
}
vkd3d-shader/ir: Flatten IF/ELSE/ENDIF control flow instructions.
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false_branch_param = NULL;
}
++flattener->instruction_count;
return false_branch_param;
}
vkd3d-shader/ir: Flatten LOOP/BREAK/CONTINUE/ENDLOOP control flow instructions.
2023-12-11 21:34:51 -08:00
static void cf_flattener_emit_conditional_branch_and_merge(struct cf_flattener *flattener,
const struct vkd3d_shader_src_param *condition, unsigned int true_id, unsigned int flags)
{
unsigned int merge_block_id;
merge_block_id = cf_flattener_alloc_block_id(flattener);
cf_flattener_emit_branch(flattener, merge_block_id, 0, condition, true_id, merge_block_id, flags);
cf_flattener_emit_label(flattener, merge_block_id);
}
vkd3d-shader/ir: Flatten IF/ELSE/ENDIF control flow instructions.
2024-01-04 06:55:51 -08:00
static void cf_flattener_emit_unconditional_branch(struct cf_flattener *flattener, unsigned int target_block_id)
{
vkd3d-shader/ir: Flatten LOOP/BREAK/CONTINUE/ENDLOOP control flow instructions.
2023-12-11 21:34:51 -08:00
cf_flattener_emit_branch(flattener, 0, 0, NULL, target_block_id, 0, 0);
vkd3d-shader/ir: Flatten IF/ELSE/ENDIF control flow instructions.
2024-01-04 06:55:51 -08:00
}
static struct cf_flattener_info *cf_flattener_push_control_flow_level(struct cf_flattener *flattener)
{
if (!vkd3d_array_reserve((void **)&flattener->control_flow_info, &flattener->control_flow_info_size,
flattener->control_flow_depth + 1, sizeof(*flattener->control_flow_info)))
{
ERR("Failed to allocate control flow info structure.\n");
flattener->allocation_failed = true;
return NULL;
}
return &flattener->control_flow_info[flattener->control_flow_depth++];
}
static void cf_flattener_pop_control_flow_level(struct cf_flattener *flattener)
{
struct cf_flattener_info *cf_info;
cf_info = &flattener->control_flow_info[--flattener->control_flow_depth];
memset(cf_info, 0, sizeof(*cf_info));
}
vkd3d-shader/ir: Flatten LOOP/BREAK/CONTINUE/ENDLOOP control flow instructions.
2023-12-11 21:34:51 -08:00
static struct cf_flattener_info *cf_flattener_find_innermost_loop(struct cf_flattener *flattener)
{
int depth;
for (depth = flattener->control_flow_depth - 1; depth >= 0; --depth)
{
if (flattener->control_flow_info[depth].current_block == VKD3D_BLOCK_LOOP)
return &flattener->control_flow_info[depth];
}
return NULL;
}
static struct cf_flattener_info *cf_flattener_find_innermost_breakable_cf_construct(struct cf_flattener *flattener)
{
int depth;
for (depth = flattener->control_flow_depth - 1; depth >= 0; --depth)
{
if (flattener->control_flow_info[depth].current_block == VKD3D_BLOCK_LOOP
|| flattener->control_flow_info[depth].current_block == VKD3D_BLOCK_SWITCH)
return &flattener->control_flow_info[depth];
}
return NULL;
}
vkd3d-shader/ir: Store code block names in struct vkd3d_shader_desc.
2023-11-07 19:14:01 -08:00
static void VKD3D_PRINTF_FUNC(3, 4) cf_flattener_create_block_name(struct cf_flattener *flattener,
unsigned int block_id, const char *fmt, ...)
{
struct vkd3d_string_buffer buffer;
size_t block_name_count;
va_list args;
--block_id;
block_name_count = max(flattener->block_name_count, block_id + 1);
if (!vkd3d_array_reserve((void **)&flattener->block_names, &flattener->block_name_capacity,
block_name_count, sizeof(*flattener->block_names)))
return;
memset(&flattener->block_names[flattener->block_name_count], 0,
(block_name_count - flattener->block_name_count) * sizeof(*flattener->block_names));
flattener->block_name_count = block_name_count;
vkd3d_string_buffer_init(&buffer);
va_start(args, fmt);
vkd3d_string_buffer_vprintf(&buffer, fmt, args);
va_end(args);
flattener->block_names[block_id] = buffer.buffer;
}
vkd3d-shader/ir: Include an initial label instruction in the first control flow block.
2024-01-11 19:20:32 -08:00
static bool vsir_instruction_is_dcl(const struct vkd3d_shader_instruction *instruction)
{
enum vkd3d_shader_opcode handler_idx = instruction->handler_idx;
return (VKD3DSIH_DCL <= handler_idx && handler_idx <= VKD3DSIH_DCL_VERTICES_OUT)
|| handler_idx == VKD3DSIH_HS_DECLS;
}
vkd3d-shader/ir: Flatten IF/ELSE/ENDIF control flow instructions.
2024-01-04 06:55:51 -08:00
static enum vkd3d_result cf_flattener_iterate_instruction_array(struct cf_flattener *flattener)
{
vkd3d-shader/ir: Include an initial label instruction in the first control flow block.
2024-01-11 19:20:32 -08:00
bool main_block_open, is_hull_shader, after_declarations_section;
vkd3d-shader/ir: Flatten IF/ELSE/ENDIF control flow instructions.
2024-01-04 06:55:51 -08:00
struct vkd3d_shader_parser *parser = flattener->parser;
struct vkd3d_shader_instruction_array *instructions;
vkd3d-shader/ir: Store the shader version in struct vsir_program.
2024-01-16 07:40:30 -08:00
struct vsir_program *program = &parser->program;
vkd3d-shader/ir: Flatten IF/ELSE/ENDIF control flow instructions.
2024-01-04 06:55:51 -08:00
struct vkd3d_shader_instruction *dst_ins;
size_t i;
vkd3d-shader/ir: Store the shader version in struct vsir_program.
2024-01-16 07:40:30 -08:00
instructions = &program->instructions;
is_hull_shader = program->shader_version.type == VKD3D_SHADER_TYPE_HULL;
vkd3d-shader/ir: Include an initial label instruction in the first control flow block.
2024-01-11 19:20:32 -08:00
main_block_open = !is_hull_shader;
after_declarations_section = is_hull_shader;
vkd3d-shader/ir: Flatten IF/ELSE/ENDIF control flow instructions.
2024-01-04 06:55:51 -08:00
vkd3d-shader/ir: Include an initial label instruction in the first control flow block.
2024-01-11 19:20:32 -08:00
if (!cf_flattener_require_space(flattener, instructions->count + 1))
vkd3d-shader/ir: Flatten IF/ELSE/ENDIF control flow instructions.
2024-01-04 06:55:51 -08:00
return VKD3D_ERROR_OUT_OF_MEMORY;
for (i = 0; i < instructions->count; ++i)
{
vkd3d-shader/ir: Flatten LOOP/BREAK/CONTINUE/ENDLOOP control flow instructions.
2023-12-11 21:34:51 -08:00
unsigned int loop_header_block_id, loop_body_block_id, continue_block_id, merge_block_id, true_block_id;
vkd3d-shader/ir: Flatten IF/ELSE/ENDIF control flow instructions.
2024-01-04 06:55:51 -08:00
const struct vkd3d_shader_instruction *instruction = &instructions->elements[i];
const struct vkd3d_shader_src_param *src = instruction->src;
struct cf_flattener_info *cf_info;
flattener->location = instruction->location;
vkd3d-shader/ir: Include an initial label instruction in the first control flow block.
2024-01-11 19:20:32 -08:00
/* Declarations should occur before the first code block, which in hull shaders is marked by the first
* phase instruction, and in all other shader types begins with the first label instruction. */
if (!after_declarations_section && !vsir_instruction_is_dcl(instruction)
&& instruction->handler_idx != VKD3DSIH_NOP)
{
after_declarations_section = true;
cf_flattener_emit_label(flattener, cf_flattener_alloc_block_id(flattener));
}
vkd3d-shader/ir: Flatten IF/ELSE/ENDIF control flow instructions.
2024-01-04 06:55:51 -08:00
cf_info = flattener->control_flow_depth
? &flattener->control_flow_info[flattener->control_flow_depth - 1] : NULL;
switch (instruction->handler_idx)
{
vkd3d-shader/ir: Include an initial label instruction in the first control flow block.
2024-01-11 19:20:32 -08:00
case VKD3DSIH_HS_CONTROL_POINT_PHASE:
case VKD3DSIH_HS_FORK_PHASE:
case VKD3DSIH_HS_JOIN_PHASE:
if (!cf_flattener_copy_instruction(flattener, instruction))
return VKD3D_ERROR_OUT_OF_MEMORY;
if (instruction->handler_idx != VKD3DSIH_HS_CONTROL_POINT_PHASE || !instruction->flags)
after_declarations_section = false;
break;
vkd3d-shader/ir: Flatten IF/ELSE/ENDIF control flow instructions.
2024-01-04 06:55:51 -08:00
case VKD3DSIH_LABEL:
vkd3d_shader_parser_error(parser, VKD3D_SHADER_ERROR_VSIR_NOT_IMPLEMENTED,
"Aborting due to not yet implemented feature: Label instruction.");
return VKD3D_ERROR_NOT_IMPLEMENTED;
case VKD3DSIH_IF:
if (!(cf_info = cf_flattener_push_control_flow_level(flattener)))
return VKD3D_ERROR_OUT_OF_MEMORY;
true_block_id = cf_flattener_alloc_block_id(flattener);
merge_block_id = cf_flattener_alloc_block_id(flattener);
vkd3d-shader/ir: Flatten LOOP/BREAK/CONTINUE/ENDLOOP control flow instructions.
2023-12-11 21:34:51 -08:00
cf_info->u.if_.false_param = cf_flattener_emit_branch(flattener, merge_block_id, 0,
vkd3d-shader/ir: Flatten IF/ELSE/ENDIF control flow instructions.
2024-01-04 06:55:51 -08:00
src, true_block_id, merge_block_id, instruction->flags);
if (!cf_info->u.if_.false_param)
return VKD3D_ERROR_OUT_OF_MEMORY;
cf_flattener_emit_label(flattener, true_block_id);
vkd3d-shader/ir: Store code block names in struct vkd3d_shader_desc.
2023-11-07 19:14:01 -08:00
cf_info->u.if_.id = flattener->branch_id;
vkd3d-shader/ir: Flatten IF/ELSE/ENDIF control flow instructions.
2024-01-04 06:55:51 -08:00
cf_info->u.if_.merge_block_id = merge_block_id;
cf_info->u.if_.else_block_id = 0;
cf_info->inside_block = true;
cf_info->current_block = VKD3D_BLOCK_IF;
vkd3d-shader/ir: Store code block names in struct vkd3d_shader_desc.
2023-11-07 19:14:01 -08:00
cf_flattener_create_block_name(flattener, merge_block_id, "branch%u_merge", flattener->branch_id);
cf_flattener_create_block_name(flattener, true_block_id, "branch%u_true", flattener->branch_id);
++flattener->branch_id;
vkd3d-shader/ir: Flatten IF/ELSE/ENDIF control flow instructions.
2024-01-04 06:55:51 -08:00
break;
case VKD3DSIH_ELSE:
if (cf_info->inside_block)
cf_flattener_emit_unconditional_branch(flattener, cf_info->u.if_.merge_block_id);
cf_info->u.if_.else_block_id = cf_flattener_alloc_block_id(flattener);
cf_info->u.if_.false_param->reg.idx[0].offset = cf_info->u.if_.else_block_id;
vkd3d-shader/ir: Store code block names in struct vkd3d_shader_desc.
2023-11-07 19:14:01 -08:00
cf_flattener_create_block_name(flattener,
cf_info->u.if_.else_block_id, "branch%u_false", cf_info->u.if_.id);
vkd3d-shader/ir: Flatten IF/ELSE/ENDIF control flow instructions.
2024-01-04 06:55:51 -08:00
cf_flattener_emit_label(flattener, cf_info->u.if_.else_block_id);
cf_info->inside_block = true;
break;
case VKD3DSIH_ENDIF:
if (cf_info->inside_block)
cf_flattener_emit_unconditional_branch(flattener, cf_info->u.if_.merge_block_id);
cf_flattener_emit_label(flattener, cf_info->u.if_.merge_block_id);
cf_flattener_pop_control_flow_level(flattener);
break;
case VKD3DSIH_LOOP:
vkd3d-shader/ir: Flatten LOOP/BREAK/CONTINUE/ENDLOOP control flow instructions.
2023-12-11 21:34:51 -08:00
if (!(cf_info = cf_flattener_push_control_flow_level(flattener)))
return VKD3D_ERROR_OUT_OF_MEMORY;
loop_header_block_id = cf_flattener_alloc_block_id(flattener);
loop_body_block_id = cf_flattener_alloc_block_id(flattener);
continue_block_id = cf_flattener_alloc_block_id(flattener);
merge_block_id = cf_flattener_alloc_block_id(flattener);
cf_flattener_emit_unconditional_branch(flattener, loop_header_block_id);
cf_flattener_emit_label(flattener, loop_header_block_id);
cf_flattener_emit_branch(flattener, merge_block_id, continue_block_id,
NULL, loop_body_block_id, 0, 0);
cf_flattener_emit_label(flattener, loop_body_block_id);
cf_info->u.loop.header_block_id = loop_header_block_id;
cf_info->u.loop.continue_block_id = continue_block_id;
cf_info->u.loop.merge_block_id = merge_block_id;
cf_info->current_block = VKD3D_BLOCK_LOOP;
cf_info->inside_block = true;
vkd3d-shader/ir: Store code block names in struct vkd3d_shader_desc.
2023-11-07 19:14:01 -08:00
cf_flattener_create_block_name(flattener, loop_header_block_id, "loop%u_header", flattener->loop_id);
cf_flattener_create_block_name(flattener, loop_body_block_id, "loop%u_body", flattener->loop_id);
cf_flattener_create_block_name(flattener, continue_block_id, "loop%u_continue", flattener->loop_id);
cf_flattener_create_block_name(flattener, merge_block_id, "loop%u_merge", flattener->loop_id);
++flattener->loop_id;
vkd3d-shader/ir: Flatten LOOP/BREAK/CONTINUE/ENDLOOP control flow instructions.
2023-12-11 21:34:51 -08:00
break;
case VKD3DSIH_ENDLOOP:
if (cf_info->inside_block)
cf_flattener_emit_unconditional_branch(flattener, cf_info->u.loop.continue_block_id);
cf_flattener_emit_label(flattener, cf_info->u.loop.continue_block_id);
cf_flattener_emit_unconditional_branch(flattener, cf_info->u.loop.header_block_id);
cf_flattener_emit_label(flattener, cf_info->u.loop.merge_block_id);
cf_flattener_pop_control_flow_level(flattener);
break;
vkd3d-shader/ir: Flatten IF/ELSE/ENDIF control flow instructions.
2024-01-04 06:55:51 -08:00
case VKD3DSIH_SWITCH:
vkd3d-shader/ir: Flatten LOOP/BREAK/CONTINUE/ENDLOOP control flow instructions.
2023-12-11 21:34:51 -08:00
if (!(cf_info = cf_flattener_push_control_flow_level(flattener)))
return VKD3D_ERROR_OUT_OF_MEMORY;
vkd3d-shader/ir: Flatten SWITCH/CASE/DEFAULT/ENDSWITCH control flow instructions.
2023-12-11 21:58:08 -08:00
merge_block_id = cf_flattener_alloc_block_id(flattener);
cf_info->u.switch_.ins_location = flattener->instruction_count;
cf_info->u.switch_.condition = src;
vkd3d-shader/ir: Flatten LOOP/BREAK/CONTINUE/ENDLOOP control flow instructions.
2023-12-11 21:34:51 -08:00
vkd3d-shader/ir: Flatten SWITCH/CASE/DEFAULT/ENDSWITCH control flow instructions.
2023-12-11 21:58:08 -08:00
if (!(dst_ins = cf_flattener_require_space(flattener, 1)))
return VKD3D_ERROR_OUT_OF_MEMORY;
vsir_instruction_init(dst_ins, &instruction->location, VKD3DSIH_SWITCH_MONOLITHIC);
++flattener->instruction_count;
vkd3d-shader/ir: Store code block names in struct vkd3d_shader_desc.
2023-11-07 19:14:01 -08:00
cf_info->u.switch_.id = flattener->switch_id;
vkd3d-shader/ir: Flatten SWITCH/CASE/DEFAULT/ENDSWITCH control flow instructions.
2023-12-11 21:58:08 -08:00
cf_info->u.switch_.merge_block_id = merge_block_id;
cf_info->u.switch_.cases = NULL;
cf_info->u.switch_.cases_size = 0;
cf_info->u.switch_.cases_count = 0;
cf_info->u.switch_.default_block_id = 0;
cf_info->inside_block = false;
vkd3d-shader/ir: Flatten LOOP/BREAK/CONTINUE/ENDLOOP control flow instructions.
2023-12-11 21:34:51 -08:00
cf_info->current_block = VKD3D_BLOCK_SWITCH;
vkd3d-shader/ir: Store code block names in struct vkd3d_shader_desc.
2023-11-07 19:14:01 -08:00
cf_flattener_create_block_name(flattener, merge_block_id, "switch%u_merge", flattener->switch_id);
++flattener->switch_id;
vkd3d-shader/ir: Flatten SWITCH/CASE/DEFAULT/ENDSWITCH control flow instructions.
2023-12-11 21:58:08 -08:00
if (!vkd3d_array_reserve((void **)&cf_info->u.switch_.cases, &cf_info->u.switch_.cases_size,
10, sizeof(*cf_info->u.switch_.cases)))
return VKD3D_ERROR_OUT_OF_MEMORY;
vkd3d-shader/ir: Flatten IF/ELSE/ENDIF control flow instructions.
2024-01-04 06:55:51 -08:00
break;
case VKD3DSIH_ENDSWITCH:
vkd3d-shader/ir: Flatten SWITCH/CASE/DEFAULT/ENDSWITCH control flow instructions.
2023-12-11 21:58:08 -08:00
{
struct vkd3d_shader_src_param *src_params;
unsigned int j;
if (!cf_info->u.switch_.default_block_id)
cf_info->u.switch_.default_block_id = cf_info->u.switch_.merge_block_id;
cf_flattener_emit_label(flattener, cf_info->u.switch_.merge_block_id);
/* The SWITCH instruction is completed when the endswitch
* instruction is processed because we do not know the number
* of case statements or the default block id in advance.*/
dst_ins = &flattener->instructions[cf_info->u.switch_.ins_location];
if (!(src_params = instruction_src_params_alloc(dst_ins, cf_info->u.switch_.cases_count * 2 + 3, flattener)))
{
vkd3d_free(cf_info->u.switch_.cases);
return VKD3D_ERROR_OUT_OF_MEMORY;
}
src_params[0] = *cf_info->u.switch_.condition;
vsir_src_param_init_label(&src_params[1], cf_info->u.switch_.default_block_id);
vsir_src_param_init_label(&src_params[2], cf_info->u.switch_.merge_block_id);
for (j = 0; j < cf_info->u.switch_.cases_count; ++j)
{
unsigned int index = j * 2 + 3;
vsir_src_param_init(&src_params[index], VKD3DSPR_IMMCONST, VKD3D_DATA_UINT, 0);
src_params[index].reg.u.immconst_u32[0] = cf_info->u.switch_.cases[j].value;
vsir_src_param_init_label(&src_params[index + 1], cf_info->u.switch_.cases[j].block_id);
}
vkd3d_free(cf_info->u.switch_.cases);
vkd3d-shader/ir: Flatten LOOP/BREAK/CONTINUE/ENDLOOP control flow instructions.
2023-12-11 21:34:51 -08:00
cf_flattener_pop_control_flow_level(flattener);
vkd3d-shader/ir: Flatten SWITCH/CASE/DEFAULT/ENDSWITCH control flow instructions.
2023-12-11 21:58:08 -08:00
break;
}
case VKD3DSIH_CASE:
{
unsigned int label_id, value;
if (src->swizzle != VKD3D_SHADER_SWIZZLE(X, X, X, X))
{
WARN("Unexpected src swizzle %#x.\n", src->swizzle);
vkd3d_shader_parser_error(parser, VKD3D_SHADER_ERROR_VSIR_INVALID_SWIZZLE,
"The swizzle for a switch case value is not scalar X.");
}
value = *src->reg.u.immconst_u32;
vkd3d-shader/ir: Flatten LOOP/BREAK/CONTINUE/ENDLOOP control flow instructions.
2023-12-11 21:34:51 -08:00
vkd3d-shader/ir: Flatten SWITCH/CASE/DEFAULT/ENDSWITCH control flow instructions.
2023-12-11 21:58:08 -08:00
if (!vkd3d_array_reserve((void **)&cf_info->u.switch_.cases, &cf_info->u.switch_.cases_size,
cf_info->u.switch_.cases_count + 1, sizeof(*cf_info->u.switch_.cases)))
vkd3d-shader/ir: Flatten IF/ELSE/ENDIF control flow instructions.
2024-01-04 06:55:51 -08:00
return VKD3D_ERROR_OUT_OF_MEMORY;
vkd3d-shader/ir: Flatten SWITCH/CASE/DEFAULT/ENDSWITCH control flow instructions.
2023-12-11 21:58:08 -08:00
label_id = cf_flattener_alloc_block_id(flattener);
if (cf_info->inside_block) /* fall-through */
cf_flattener_emit_unconditional_branch(flattener, label_id);
cf_info->u.switch_.cases[cf_info->u.switch_.cases_count].value = value;
cf_info->u.switch_.cases[cf_info->u.switch_.cases_count].block_id = label_id;
++cf_info->u.switch_.cases_count;
cf_flattener_emit_label(flattener, label_id);
vkd3d-shader/ir: Store code block names in struct vkd3d_shader_desc.
2023-11-07 19:14:01 -08:00
cf_flattener_create_block_name(flattener, label_id, "switch%u_case%u", cf_info->u.switch_.id, value);
vkd3d-shader/ir: Flatten SWITCH/CASE/DEFAULT/ENDSWITCH control flow instructions.
2023-12-11 21:58:08 -08:00
cf_info->inside_block = true;
break;
}
case VKD3DSIH_DEFAULT:
cf_info->u.switch_.default_block_id = cf_flattener_alloc_block_id(flattener);
if (cf_info->inside_block) /* fall-through */
cf_flattener_emit_unconditional_branch(flattener, cf_info->u.switch_.default_block_id);
cf_flattener_emit_label(flattener, cf_info->u.switch_.default_block_id);
vkd3d-shader/ir: Store code block names in struct vkd3d_shader_desc.
2023-11-07 19:14:01 -08:00
cf_flattener_create_block_name(flattener, cf_info->u.switch_.default_block_id,
"switch%u_default", cf_info->u.switch_.id);
vkd3d-shader/ir: Flatten SWITCH/CASE/DEFAULT/ENDSWITCH control flow instructions.
2023-12-11 21:58:08 -08:00
cf_info->inside_block = true;
vkd3d-shader/ir: Flatten IF/ELSE/ENDIF control flow instructions.
2024-01-04 06:55:51 -08:00
break;
vkd3d-shader/ir: Flatten LOOP/BREAK/CONTINUE/ENDLOOP control flow instructions.
2023-12-11 21:34:51 -08:00
case VKD3DSIH_BREAK:
{
struct cf_flattener_info *breakable_cf_info;
if (!(breakable_cf_info = cf_flattener_find_innermost_breakable_cf_construct(flattener)))
{
FIXME("Unhandled break instruction.\n");
return VKD3D_ERROR_INVALID_SHADER;
}
if (breakable_cf_info->current_block == VKD3D_BLOCK_LOOP)
{
cf_flattener_emit_unconditional_branch(flattener, breakable_cf_info->u.loop.merge_block_id);
}
else if (breakable_cf_info->current_block == VKD3D_BLOCK_SWITCH)
{
vkd3d-shader/ir: Flatten SWITCH/CASE/DEFAULT/ENDSWITCH control flow instructions.
2023-12-11 21:58:08 -08:00
cf_flattener_emit_unconditional_branch(flattener, breakable_cf_info->u.switch_.merge_block_id);
vkd3d-shader/ir: Flatten LOOP/BREAK/CONTINUE/ENDLOOP control flow instructions.
2023-12-11 21:34:51 -08:00
}
cf_info->inside_block = false;
break;
}
case VKD3DSIH_BREAKP:
{
struct cf_flattener_info *loop_cf_info;
if (!(loop_cf_info = cf_flattener_find_innermost_loop(flattener)))
{
ERR("Invalid 'breakc' instruction outside loop.\n");
return VKD3D_ERROR_INVALID_SHADER;
}
cf_flattener_emit_conditional_branch_and_merge(flattener,
src, loop_cf_info->u.loop.merge_block_id, instruction->flags);
break;
}
case VKD3DSIH_CONTINUE:
{
struct cf_flattener_info *loop_cf_info;
if (!(loop_cf_info = cf_flattener_find_innermost_loop(flattener)))
{
ERR("Invalid 'continue' instruction outside loop.\n");
return VKD3D_ERROR_INVALID_SHADER;
}
cf_flattener_emit_unconditional_branch(flattener, loop_cf_info->u.loop.continue_block_id);
cf_info->inside_block = false;
break;
}
case VKD3DSIH_CONTINUEP:
{
struct cf_flattener_info *loop_cf_info;
if (!(loop_cf_info = cf_flattener_find_innermost_loop(flattener)))
{
ERR("Invalid 'continuec' instruction outside loop.\n");
return VKD3D_ERROR_INVALID_SHADER;
}
cf_flattener_emit_conditional_branch_and_merge(flattener,
src, loop_cf_info->u.loop.continue_block_id, instruction->flags);
break;
}
vkd3d-shader/ir: Flatten IF/ELSE/ENDIF control flow instructions.
2024-01-04 06:55:51 -08:00
case VKD3DSIH_RET:
if (!cf_flattener_copy_instruction(flattener, instruction))
return VKD3D_ERROR_OUT_OF_MEMORY;
if (cf_info)
cf_info->inside_block = false;
vkd3d-shader/ir: Flatten LOOP/BREAK/CONTINUE/ENDLOOP control flow instructions.
2023-12-11 21:34:51 -08:00
else
vkd3d-shader/ir: Flatten IF/ELSE/ENDIF control flow instructions.
2024-01-04 06:55:51 -08:00
main_block_open = false;
break;
default:
if (!cf_flattener_copy_instruction(flattener, instruction))
return VKD3D_ERROR_OUT_OF_MEMORY;
break;
}
}
if (main_block_open)
{
if (!(dst_ins = cf_flattener_require_space(flattener, 1)))
return VKD3D_ERROR_OUT_OF_MEMORY;
vsir_instruction_init(dst_ins, &flattener->location, VKD3DSIH_RET);
++flattener->instruction_count;
}
return flattener->allocation_failed ? VKD3D_ERROR_OUT_OF_MEMORY : VKD3D_OK;
}
static enum vkd3d_result flatten_control_flow_constructs(struct vkd3d_shader_parser *parser)
{
struct cf_flattener flattener = {0};
enum vkd3d_result result;
flattener.parser = parser;
result = cf_flattener_iterate_instruction_array(&flattener);
if (result >= 0)
{
vkd3d-shader/ir: Introduce struct vsir_program.
2024-01-16 05:47:34 -08:00
vkd3d_free(parser->program.instructions.elements);
parser->program.instructions.elements = flattener.instructions;
parser->program.instructions.capacity = flattener.instruction_capacity;
parser->program.instructions.count = flattener.instruction_count;
vkd3d-shader/ir: Flatten IF/ELSE/ENDIF control flow instructions.
2024-01-04 06:55:51 -08:00
parser->shader_desc.block_count = flattener.block_id;
}
else
{
vkd3d_free(flattener.instructions);
}
vkd3d_free(flattener.control_flow_info);
vkd3d-shader/ir: Store code block names in struct vkd3d_shader_desc.
2023-11-07 19:14:01 -08:00
/* Simpler to always free these in free_shader_desc(). */
parser->shader_desc.block_names = flattener.block_names;
parser->shader_desc.block_name_count = flattener.block_name_count;
vkd3d-shader/ir: Flatten IF/ELSE/ENDIF control flow instructions.
2024-01-04 06:55:51 -08:00
return result;
}
vkd3d-shader: Implement remapping shader output registers to match the next shader's semantics.
2023-07-20 19:52:25 -07:00
enum vkd3d_result vkd3d_shader_normalise(struct vkd3d_shader_parser *parser,
const struct vkd3d_shader_compile_info *compile_info)
vkd3d-shader/ir: Move normalization code from spirv.c to ir.c. It is not spirv-specific and will (presumably) be used for GLSL as well.
2023-07-02 18:23:07 -07:00
{
vkd3d-shader/ir: Introduce struct vsir_program.
2024-01-16 05:47:34 -08:00
struct vkd3d_shader_instruction_array *instructions = &parser->program.instructions;
vkd3d-shader/ir: Move normalization code from spirv.c to ir.c. It is not spirv-specific and will (presumably) be used for GLSL as well.
2023-07-02 18:23:07 -07:00
enum vkd3d_result result = VKD3D_OK;
vkd3d-shader/spirv: Do not normalise Shader Model 6 shaders.
2023-06-02 07:23:49 -07:00
if (parser->shader_desc.is_dxil)
return result;
vkd3d-shader/ir: Store the shader version in struct vsir_program.
2024-01-16 07:40:30 -08:00
if (parser->program.shader_version.type != VKD3D_SHADER_TYPE_PIXEL
vkd3d-shader: Implement remapping shader output registers to match the next shader's semantics.
2023-07-20 19:52:25 -07:00
&& (result = remap_output_signature(parser, compile_info)) < 0)
return result;
vkd3d-shader/ir: Store the shader version in struct vsir_program.
2024-01-16 07:40:30 -08:00
if (parser->program.shader_version.type == VKD3D_SHADER_TYPE_HULL
vkd3d-shader/ir: Move normalization code from spirv.c to ir.c. It is not spirv-specific and will (presumably) be used for GLSL as well.
2023-07-02 18:23:07 -07:00
&& (result = instruction_array_flatten_hull_shader_phases(instructions)) >= 0)
{
result = instruction_array_normalise_hull_shader_control_point_io(instructions,
&parser->shader_desc.input_signature);
}
if (result >= 0)
vkd3d-shader/ir: Pass a vkd3d_shader_parser to instruction_array_normalise_io_registers().
2023-07-16 21:27:52 -07:00
result = shader_normalise_io_registers(parser);
vkd3d-shader/ir: Move normalization code from spirv.c to ir.c. It is not spirv-specific and will (presumably) be used for GLSL as well.
2023-07-02 18:23:07 -07:00
vkd3d-shader/ir: Normalise sm1-style constants.
2023-07-09 15:46:04 -07:00
if (result >= 0)
vkd3d-shader/ir: Introduce struct vsir_program.
2024-01-16 05:47:34 -08:00
result = instruction_array_normalise_flat_constants(&parser->program);
vkd3d-shader/ir: Normalise sm1-style constants.
2023-07-09 15:46:04 -07:00
vkd3d-shader/ir: Remove dead code during normalisation. The SPIR-V backend generates invalid SPIR-V code when VSIR has dead code (except for NOPs).
2023-09-20 13:10:39 -07:00
if (result >= 0)
vkd3d-shader/ir: Introduce struct vsir_program.
2024-01-16 05:47:34 -08:00
remove_dead_code(&parser->program);
vkd3d-shader/ir: Remove dead code during normalisation. The SPIR-V backend generates invalid SPIR-V code when VSIR has dead code (except for NOPs).
2023-09-20 13:10:39 -07:00
vkd3d-shader/ir: Flatten IF/ELSE/ENDIF control flow instructions.
2024-01-04 06:55:51 -08:00
if (result >= 0)
result = flatten_control_flow_constructs(parser);
vkd3d-shader/ir: Translate TEX instructions to SAMPLE.
2023-08-11 14:46:03 -07:00
if (result >= 0)
result = normalise_combined_samplers(parser);
vkd3d-shader/ir: Move normalization code from spirv.c to ir.c. It is not spirv-specific and will (presumably) be used for GLSL as well.
2023-07-02 18:23:07 -07:00
if (result >= 0 && TRACE_ON())
vkd3d-shader/ir: Store the shader version in struct vsir_program.
2024-01-16 07:40:30 -08:00
vkd3d_shader_trace(&parser->program);
vkd3d-shader/ir: Move normalization code from spirv.c to ir.c. It is not spirv-specific and will (presumably) be used for GLSL as well.
2023-07-02 18:23:07 -07:00
vkd3d-shader/ir: Introduce a boilerplate to validate the generated IR. For the moment the validator is trivial, it never fails. Checks will be added incrementally.
2023-08-29 12:20:35 -07:00
if (result >= 0 && !parser->failed)
vkd3d-shader/ir: Check that TEMP registers have consistent dimensions.
2024-01-10 02:27:03 -08:00
result = vsir_validate(parser);
vkd3d-shader/ir: Introduce a boilerplate to validate the generated IR. For the moment the validator is trivial, it never fails. Checks will be added incrementally.
2023-08-29 12:20:35 -07:00
if (result >= 0 && parser->failed)
result = VKD3D_ERROR_INVALID_SHADER;
vkd3d-shader/ir: Move normalization code from spirv.c to ir.c. It is not spirv-specific and will (presumably) be used for GLSL as well.
2023-07-02 18:23:07 -07:00
return result;
}
vkd3d-shader/ir: Introduce a boilerplate to validate the generated IR. For the moment the validator is trivial, it never fails. Checks will be added incrementally.
2023-08-29 12:20:35 -07:00
struct validation_context
{
struct vkd3d_shader_parser *parser;
vkd3d-shader/ir: Store the shader version in struct vsir_program.
2024-01-16 07:40:30 -08:00
const struct vsir_program *program;
vkd3d-shader/ir: Validate instruction handlers.
2023-08-29 12:35:01 -07:00
size_t instruction_idx;
vkd3d-shader/ir: Check that SSA registers are used validly. Specifically, they are assigned only once and only assigned components are used. Right now we don't check that the assignment dominates all usages.
2024-01-10 02:58:44 -08:00
bool invalid_instruction_idx;
vkd3d-shader/ir: Validate the index of a TEMP register.
2023-10-24 17:55:37 -07:00
bool dcl_temps_found;
vkd3d-shader/ir: Validate the TEMP register indices in each HS phase.
2023-11-07 14:21:11 -08:00
unsigned int temp_count;
vkd3d-shader/ir: Keep track of hull shader phases.
2023-11-06 14:11:03 -08:00
enum vkd3d_shader_opcode phase;
vkd3d-shader/ir: Validate that structured CF does not appear in block-based shaders.
2024-01-12 00:28:14 -08:00
enum cf_type
{
CF_TYPE_UNKNOWN = 0,
CF_TYPE_STRUCTURED,
CF_TYPE_BLOCKS,
} cf_type;
vkd3d-shader/ir: Check that IF blocks are correctly nested.
2023-11-06 04:47:34 -08:00
vkd3d-shader/ir: Check that TEMP registers have consistent dimensions.
2024-01-10 02:27:03 -08:00
struct validation_context_temp_data
{
enum vsir_dimension dimension;
size_t first_seen;
} *temps;
vkd3d-shader/ir: Check that SSA registers have consistent dimensions.
2024-01-10 02:31:40 -08:00
struct validation_context_ssa_data
{
enum vsir_dimension dimension;
size_t first_seen;
vkd3d-shader/ir: Check that SSA registers are used validly. Specifically, they are assigned only once and only assigned components are used. Right now we don't check that the assignment dominates all usages.
2024-01-10 02:58:44 -08:00
uint32_t write_mask;
uint32_t read_mask;
size_t first_assigned;
vkd3d-shader/ir: Check that SSA registers have consistent dimensions.
2024-01-10 02:31:40 -08:00
} *ssas;
vkd3d-shader/ir: Check that IF blocks are correctly nested.
2023-11-06 04:47:34 -08:00
enum vkd3d_shader_opcode *blocks;
size_t depth;
size_t blocks_capacity;
vkd3d-shader/ir: Introduce a boilerplate to validate the generated IR. For the moment the validator is trivial, it never fails. Checks will be added incrementally.
2023-08-29 12:20:35 -07:00
};
vkd3d-shader/ir: Validate instruction handlers.
2023-08-29 12:35:01 -07:00
static void VKD3D_PRINTF_FUNC(3, 4) validator_error(struct validation_context *ctx,
enum vkd3d_shader_error error, const char *format, ...)
{
struct vkd3d_string_buffer buf;
va_list args;
vkd3d_string_buffer_init(&buf);
va_start(args, format);
vkd3d_string_buffer_vprintf(&buf, format, args);
va_end(args);
vkd3d-shader/ir: Check that SSA registers are used validly. Specifically, they are assigned only once and only assigned components are used. Right now we don't check that the assignment dominates all usages.
2024-01-10 02:58:44 -08:00
if (ctx->invalid_instruction_idx)
{
vkd3d_shader_parser_error(ctx->parser, error, "%s", buf.buffer);
ERR("VSIR validation error: %s\n", buf.buffer);
}
else
{
vkd3d_shader_parser_error(ctx->parser, error, "instruction %zu: %s", ctx->instruction_idx + 1, buf.buffer);
ERR("VSIR validation error: instruction %zu: %s\n", ctx->instruction_idx + 1, buf.buffer);
}
vkd3d-shader/ir: Validate instruction handlers.
2023-08-29 12:35:01 -07:00
vkd3d_string_buffer_cleanup(&buf);
}
vkd3d-shader/ir: Validate register indices.
2023-11-08 14:10:06 -08:00
static void vsir_validate_src_param(struct validation_context *ctx,
const struct vkd3d_shader_src_param *src);
vkd3d-shader/ir: Validate register types.
2023-08-29 12:58:31 -07:00
static void vsir_validate_register(struct validation_context *ctx,
const struct vkd3d_shader_register *reg)
{
vkd3d-shader/ir: Validate register indices.
2023-11-08 14:10:06 -08:00
unsigned int i, temp_count = ctx->temp_count;
vkd3d-shader/ir: Validate the TEMP register indices in each HS phase.
2023-11-07 14:21:11 -08:00
/* SM1-3 shaders do not include a DCL_TEMPS instruction. */
vkd3d-shader/ir: Store the shader version in struct vsir_program.
2024-01-16 07:40:30 -08:00
if (ctx->program->shader_version.major <= 3)
vkd3d-shader/ir: Validate the TEMP register indices in each HS phase.
2023-11-07 14:21:11 -08:00
temp_count = ctx->parser->shader_desc.temp_count;
vkd3d-shader/ir: Validate register types.
2023-08-29 12:58:31 -07:00
if (reg->type >= VKD3DSPR_COUNT)
validator_error(ctx, VKD3D_SHADER_ERROR_VSIR_INVALID_REGISTER_TYPE, "Invalid register type %#x.",
reg->type);
vkd3d-shader/ir: Validate the register precision.
2023-10-24 17:37:40 -07:00
if (reg->precision >= VKD3D_SHADER_REGISTER_PRECISION_COUNT)
validator_error(ctx, VKD3D_SHADER_ERROR_VSIR_INVALID_PRECISION, "Invalid register precision %#x.",
reg->precision);
vkd3d-shader/ir: Validate the register data type.
2023-10-24 17:41:09 -07:00
if (reg->data_type >= VKD3D_DATA_COUNT)
validator_error(ctx, VKD3D_SHADER_ERROR_VSIR_INVALID_DATA_TYPE, "Invalid register data type %#x.",
reg->data_type);
vkd3d-shader/ir: Validate the register dimension.
2023-10-24 17:43:31 -07:00
if (reg->dimension >= VSIR_DIMENSION_COUNT)
validator_error(ctx, VKD3D_SHADER_ERROR_VSIR_INVALID_DIMENSION, "Invalid register dimension %#x.",
reg->dimension);
vkd3d-shader/ir: Validate the register index count.
2023-10-24 17:46:07 -07:00
if (reg->idx_count > ARRAY_SIZE(reg->idx))
validator_error(ctx, VKD3D_SHADER_ERROR_VSIR_INVALID_INDEX_COUNT, "Invalid register index count %u.",
reg->idx_count);
vkd3d-shader/ir: Validate the index of a TEMP register.
2023-10-24 17:55:37 -07:00
vkd3d-shader/ir: Validate register indices.
2023-11-08 14:10:06 -08:00
for (i = 0; i < min(reg->idx_count, ARRAY_SIZE(reg->idx)); ++i)
{
const struct vkd3d_shader_src_param *param = reg->idx[i].rel_addr;
if (reg->idx[i].rel_addr)
vsir_validate_src_param(ctx, param);
}
vkd3d-shader/ir: Validate the index of a TEMP register.
2023-10-24 17:55:37 -07:00
switch (reg->type)
{
case VKD3DSPR_TEMP:
vkd3d-shader/ir: Check that TEMP registers have consistent dimensions.
2024-01-10 02:27:03 -08:00
{
struct validation_context_temp_data *data;
vkd3d-shader/ir: Validate the index of a TEMP register.
2023-10-24 17:55:37 -07:00
if (reg->idx_count != 1)
vkd3d-shader/ir: Simplify control flow in vsir_validate_register().
2024-01-10 02:02:56 -08:00
{
vkd3d-shader/ir: Validate the index of a TEMP register.
2023-10-24 17:55:37 -07:00
validator_error(ctx, VKD3D_SHADER_ERROR_VSIR_INVALID_INDEX_COUNT, "Invalid index count %u for a TEMP register.",
reg->idx_count);
vkd3d-shader/ir: Simplify control flow in vsir_validate_register().
2024-01-10 02:02:56 -08:00
break;
}
vkd3d-shader/ir: Validate the index of a TEMP register.
2023-10-24 17:55:37 -07:00
vkd3d-shader/ir: Simplify control flow in vsir_validate_register().
2024-01-10 02:02:56 -08:00
if (reg->idx[0].rel_addr)
vkd3d-shader/ir: Validate the index of a TEMP register.
2023-10-24 17:55:37 -07:00
validator_error(ctx, VKD3D_SHADER_ERROR_VSIR_INVALID_INDEX, "Non-NULL relative address for a TEMP register.");
vkd3d-shader/ir: Simplify control flow in vsir_validate_register().
2024-01-10 02:02:56 -08:00
if (reg->idx[0].offset >= temp_count)
vkd3d-shader/ir: Check that TEMP registers have consistent dimensions.
2024-01-10 02:27:03 -08:00
{
vkd3d-shader/ir: Validate the TEMP register indices in each HS phase.
2023-11-07 14:21:11 -08:00
validator_error(ctx, VKD3D_SHADER_ERROR_VSIR_INVALID_INDEX, "TEMP register index %u exceeds the maximum count %u.",
reg->idx[0].offset, temp_count);
vkd3d-shader/ir: Check that TEMP registers have consistent dimensions.
2024-01-10 02:27:03 -08:00
break;
}
/* parser->shader_desc.temp_count might be smaller then
* temp_count if the parser made a mistake; we still don't
* want to overflow the array. */
if (reg->idx[0].offset >= ctx->parser->shader_desc.temp_count)
break;
data = &ctx->temps[reg->idx[0].offset];
if (reg->dimension == VSIR_DIMENSION_NONE)
{
validator_error(ctx, VKD3D_SHADER_ERROR_VSIR_INVALID_DIMENSION, "Invalid dimension NONE for a TEMP register.");
break;
}
/* TEMP registers can be scalar or vec4, provided that
* each individual register always appears with the same
* dimension. */
if (data->dimension == VSIR_DIMENSION_NONE)
{
data->dimension = reg->dimension;
data->first_seen = ctx->instruction_idx;
}
else if (data->dimension != reg->dimension)
{
validator_error(ctx, VKD3D_SHADER_ERROR_VSIR_INVALID_DIMENSION, "Invalid dimension %#x for a TEMP register: "
"it has already been seen with dimension %#x at instruction %zu.",
reg->dimension, data->dimension, data->first_seen);
}
vkd3d-shader/ir: Validate the index of a TEMP register.
2023-10-24 17:55:37 -07:00
break;
vkd3d-shader/ir: Check that TEMP registers have consistent dimensions.
2024-01-10 02:27:03 -08:00
}
vkd3d-shader/ir: Validate the index of a TEMP register.
2023-10-24 17:55:37 -07:00
vkd3d-shader/ir: Validate SSA registers.
2023-12-21 06:54:13 -08:00
case VKD3DSPR_SSA:
vkd3d-shader/ir: Check that SSA registers have consistent dimensions.
2024-01-10 02:31:40 -08:00
{
struct validation_context_ssa_data *data;
vkd3d-shader/ir: Validate SSA registers.
2023-12-21 06:54:13 -08:00
if (reg->idx_count != 1)
vkd3d-shader/ir: Simplify control flow in vsir_validate_register().
2024-01-10 02:02:56 -08:00
{
vkd3d-shader/ir: Validate SSA registers.
2023-12-21 06:54:13 -08:00
validator_error(ctx, VKD3D_SHADER_ERROR_VSIR_INVALID_INDEX_COUNT, "Invalid index count %u for a SSA register.",
reg->idx_count);
vkd3d-shader/ir: Simplify control flow in vsir_validate_register().
2024-01-10 02:02:56 -08:00
break;
}
vkd3d-shader/ir: Validate SSA registers.
2023-12-21 06:54:13 -08:00
vkd3d-shader/ir: Simplify control flow in vsir_validate_register().
2024-01-10 02:02:56 -08:00
if (reg->idx[0].rel_addr)
vkd3d-shader/ir: Validate SSA registers.
2023-12-21 06:54:13 -08:00
validator_error(ctx, VKD3D_SHADER_ERROR_VSIR_INVALID_INDEX, "Non-NULL relative address for a SSA register.");
vkd3d-shader/ir: Simplify control flow in vsir_validate_register().
2024-01-10 02:02:56 -08:00
if (reg->idx[0].offset >= ctx->parser->shader_desc.ssa_count)
vkd3d-shader/ir: Check that SSA registers have consistent dimensions.
2024-01-10 02:31:40 -08:00
{
vkd3d-shader/ir: Validate SSA registers.
2023-12-21 06:54:13 -08:00
validator_error(ctx, VKD3D_SHADER_ERROR_VSIR_INVALID_INDEX, "SSA register index %u exceeds the maximum count %u.",
reg->idx[0].offset, ctx->parser->shader_desc.ssa_count);
vkd3d-shader/ir: Check that SSA registers have consistent dimensions.
2024-01-10 02:31:40 -08:00
break;
}
data = &ctx->ssas[reg->idx[0].offset];
if (reg->dimension == VSIR_DIMENSION_NONE)
{
validator_error(ctx, VKD3D_SHADER_ERROR_VSIR_INVALID_DIMENSION, "Invalid dimension NONE for a SSA register.");
break;
}
/* SSA registers can be scalar or vec4, provided that each
* individual register always appears with the same
* dimension. */
if (data->dimension == VSIR_DIMENSION_NONE)
{
data->dimension = reg->dimension;
data->first_seen = ctx->instruction_idx;
}
else if (data->dimension != reg->dimension)
{
validator_error(ctx, VKD3D_SHADER_ERROR_VSIR_INVALID_DIMENSION, "Invalid dimension %#x for a SSA register: "
"it has already been seen with dimension %#x at instruction %zu.",
reg->dimension, data->dimension, data->first_seen);
}
vkd3d-shader/ir: Validate SSA registers.
2023-12-21 06:54:13 -08:00
break;
vkd3d-shader/ir: Check that SSA registers have consistent dimensions.
2024-01-10 02:31:40 -08:00
}
vkd3d-shader/ir: Validate SSA registers.
2023-12-21 06:54:13 -08:00
vkd3d-shader/ir: Validate LABEL registers.
2023-12-22 05:36:30 -08:00
case VKD3DSPR_LABEL:
if (reg->precision != VKD3D_SHADER_REGISTER_PRECISION_DEFAULT)
validator_error(ctx, VKD3D_SHADER_ERROR_VSIR_INVALID_PRECISION, "Invalid precision %#x for a LABEL register.",
reg->precision);
if (reg->data_type != VKD3D_DATA_UINT)
validator_error(ctx, VKD3D_SHADER_ERROR_VSIR_INVALID_DATA_TYPE, "Invalid data type %#x for a LABEL register.",
reg->data_type);
if (reg->dimension != VSIR_DIMENSION_NONE)
validator_error(ctx, VKD3D_SHADER_ERROR_VSIR_INVALID_DIMENSION, "Invalid dimension %#x for a LABEL register.",
reg->dimension);
if (reg->idx_count != 1)
{
validator_error(ctx, VKD3D_SHADER_ERROR_VSIR_INVALID_INDEX_COUNT, "Invalid index count %u for a LABEL register.",
reg->idx_count);
break;
}
if (reg->idx[0].rel_addr)
validator_error(ctx, VKD3D_SHADER_ERROR_VSIR_INVALID_INDEX, "Non-NULL relative address for a LABEL register.");
/* Index == 0 is invalid, but it is temporarily allowed
* for intermediate stages. Once we support validation
* dialects we can selectively check for that. */
if (reg->idx[0].offset > ctx->parser->shader_desc.block_count)
validator_error(ctx, VKD3D_SHADER_ERROR_VSIR_INVALID_INDEX, "LABEL register index %u exceeds the maximum count %u.",
reg->idx[0].offset, ctx->parser->shader_desc.block_count);
break;
vkd3d-shader/ir: Validate index count for NULL registers.
2023-11-08 14:12:30 -08:00
case VKD3DSPR_NULL:
if (reg->idx_count != 0)
validator_error(ctx, VKD3D_SHADER_ERROR_VSIR_INVALID_INDEX_COUNT, "Invalid index count %u for a NULL register.",
reg->idx_count);
break;
vkd3d-shader/ir: Validate index count for IMMCONST registers.
2023-11-08 14:17:05 -08:00
case VKD3DSPR_IMMCONST:
if (reg->idx_count != 0)
validator_error(ctx, VKD3D_SHADER_ERROR_VSIR_INVALID_INDEX_COUNT, "Invalid index count %u for a IMMCONST register.",
reg->idx_count);
break;
vkd3d-shader/ir: Validate index count for IMMCONST64 registers.
2023-11-08 14:17:39 -08:00
case VKD3DSPR_IMMCONST64:
if (reg->idx_count != 0)
validator_error(ctx, VKD3D_SHADER_ERROR_VSIR_INVALID_INDEX_COUNT, "Invalid index count %u for a IMMCONST64 register.",
reg->idx_count);
break;
vkd3d-shader/ir: Validate the index of a TEMP register.
2023-10-24 17:55:37 -07:00
default:
break;
}
vkd3d-shader/ir: Validate register types.
2023-08-29 12:58:31 -07:00
}
static void vsir_validate_dst_param(struct validation_context *ctx,
const struct vkd3d_shader_dst_param *dst)
{
vsir_validate_register(ctx, &dst->reg);
vkd3d-shader/ir: Validate destination parameters.
2023-08-29 13:17:28 -07:00
if (dst->write_mask & ~VKD3DSP_WRITEMASK_ALL)
validator_error(ctx, VKD3D_SHADER_ERROR_VSIR_INVALID_WRITE_MASK, "Destination has invalid write mask %#x.",
dst->write_mask);
vkd3d-shader/ir: Validate destination write masks depending on the dimension.
2023-12-21 07:04:10 -08:00
switch (dst->reg.dimension)
{
case VSIR_DIMENSION_SCALAR:
if (dst->write_mask != VKD3DSP_WRITEMASK_0)
validator_error(ctx, VKD3D_SHADER_ERROR_VSIR_INVALID_WRITE_MASK, "Scalar destination has invalid write mask %#x.",
dst->write_mask);
break;
case VSIR_DIMENSION_VEC4:
if (dst->write_mask == 0)
validator_error(ctx, VKD3D_SHADER_ERROR_VSIR_INVALID_WRITE_MASK, "Vec4 destination has empty write mask.");
break;
default:
if (dst->write_mask != 0)
validator_error(ctx, VKD3D_SHADER_ERROR_VSIR_INVALID_WRITE_MASK, "Destination of dimension %u has invalid write mask %#x.",
dst->reg.dimension, dst->write_mask);
break;
}
vkd3d-shader/ir: Validate destination parameters.
2023-08-29 13:17:28 -07:00
if (dst->modifiers & ~VKD3DSPDM_MASK)
validator_error(ctx, VKD3D_SHADER_ERROR_VSIR_INVALID_MODIFIERS, "Destination has invalid modifiers %#x.",
dst->modifiers);
switch (dst->shift)
{
case 0:
case 1:
case 2:
case 3:
case 13:
case 14:
case 15:
break;
default:
validator_error(ctx, VKD3D_SHADER_ERROR_VSIR_INVALID_SHIFT, "Destination has invalid shift %#x.",
dst->shift);
}
vkd3d-shader/ir: Check that SSA registers are used validly. Specifically, they are assigned only once and only assigned components are used. Right now we don't check that the assignment dominates all usages.
2024-01-10 02:58:44 -08:00
if (dst->reg.type == VKD3DSPR_SSA && dst->reg.idx[0].offset < ctx->parser->shader_desc.ssa_count)
{
struct validation_context_ssa_data *data = &ctx->ssas[dst->reg.idx[0].offset];
if (data->write_mask == 0)
{
data->write_mask = dst->write_mask;
data->first_assigned = ctx->instruction_idx;
}
else
{
validator_error(ctx, VKD3D_SHADER_ERROR_VSIR_INVALID_SSA_USAGE,
"SSA register is already assigned at instruction %zu.",
data->first_assigned);
}
}
vkd3d-shader/ir: Validate register types.
2023-08-29 12:58:31 -07:00
}
static void vsir_validate_src_param(struct validation_context *ctx,
const struct vkd3d_shader_src_param *src)
{
vsir_validate_register(ctx, &src->reg);
vkd3d-shader/ir: Validate source parameters.
2023-08-29 13:23:02 -07:00
if (src->swizzle & ~0x03030303u)
validator_error(ctx, VKD3D_SHADER_ERROR_VSIR_INVALID_SWIZZLE, "Source has invalid swizzle %#x.",
src->swizzle);
vkd3d-shader/ir: Validate source swizzles depending on the dimension.
2023-12-21 06:58:46 -08:00
if (src->reg.dimension != VSIR_DIMENSION_VEC4 && src->swizzle != 0)
validator_error(ctx, VKD3D_SHADER_ERROR_VSIR_INVALID_SWIZZLE, "Source of dimension %u has invalid swizzle %#x.",
src->reg.dimension, src->swizzle);
vkd3d-shader/ir: Validate source parameters.
2023-08-29 13:23:02 -07:00
if (src->modifiers >= VKD3DSPSM_COUNT)
validator_error(ctx, VKD3D_SHADER_ERROR_VSIR_INVALID_MODIFIERS, "Source has invalid modifiers %#x.",
src->modifiers);
vkd3d-shader/ir: Check that SSA registers are used validly. Specifically, they are assigned only once and only assigned components are used. Right now we don't check that the assignment dominates all usages.
2024-01-10 02:58:44 -08:00
if (src->reg.type == VKD3DSPR_SSA && src->reg.idx[0].offset < ctx->parser->shader_desc.ssa_count)
{
struct validation_context_ssa_data *data = &ctx->ssas[src->reg.idx[0].offset];
unsigned int i;
for (i = 0; i < VKD3D_VEC4_SIZE; ++i)
data->read_mask |= (1u << vsir_swizzle_get_component(src->swizzle, i));
}
vkd3d-shader/ir: Validate register types.
2023-08-29 12:58:31 -07:00
}
vkd3d-shader/ir: Validate the DCL_TEMPS instruction.
2023-10-24 18:08:00 -07:00
static void vsir_validate_dst_count(struct validation_context *ctx,
const struct vkd3d_shader_instruction *instruction, unsigned int count)
{
if (instruction->dst_count != count)
validator_error(ctx, VKD3D_SHADER_ERROR_VSIR_INVALID_DEST_COUNT,
"Invalid destination count %u for an instruction of type %#x, expected %u.",
instruction->dst_count, instruction->handler_idx, count);
}
static void vsir_validate_src_count(struct validation_context *ctx,
const struct vkd3d_shader_instruction *instruction, unsigned int count)
{
if (instruction->src_count != count)
validator_error(ctx, VKD3D_SHADER_ERROR_VSIR_INVALID_SOURCE_COUNT,
"Invalid source count %u for an instruction of type %#x, expected %u.",
instruction->src_count, instruction->handler_idx, count);
}
vkd3d-shader/ir: Validate BRANCH instructions.
2023-12-22 08:11:41 -08:00
static bool vsir_validate_src_min_count(struct validation_context *ctx,
const struct vkd3d_shader_instruction *instruction, unsigned int count)
{
if (instruction->src_count < count)
{
validator_error(ctx, VKD3D_SHADER_ERROR_VSIR_INVALID_SOURCE_COUNT,
"Invalid source count %u for an instruction of type %#x, expected at least %u.",
instruction->src_count, instruction->handler_idx, count);
return false;
}
return true;
}
static bool vsir_validate_src_max_count(struct validation_context *ctx,
const struct vkd3d_shader_instruction *instruction, unsigned int count)
{
if (instruction->src_count > count)
{
validator_error(ctx, VKD3D_SHADER_ERROR_VSIR_INVALID_SOURCE_COUNT,
"Invalid source count %u for an instruction of type %#x, expected at most %u.",
instruction->src_count, instruction->handler_idx, count);
return false;
}
return true;
}
vkd3d-shader/ir: Validate that structured CF does not appear in block-based shaders.
2024-01-12 00:28:14 -08:00
static const char *name_from_cf_type(enum cf_type type)
{
switch (type)
{
case CF_TYPE_STRUCTURED:
return "structured";
case CF_TYPE_BLOCKS:
return "block-based";
default:
vkd3d_unreachable();
}
}
static void vsir_validate_cf_type(struct validation_context *ctx,
const struct vkd3d_shader_instruction *instruction, enum cf_type expected_type)
{
assert(ctx->cf_type != CF_TYPE_UNKNOWN);
assert(expected_type != CF_TYPE_UNKNOWN);
if (ctx->cf_type != expected_type)
validator_error(ctx, VKD3D_SHADER_ERROR_VSIR_INVALID_CONTROL_FLOW, "Invalid instruction %#x in %s shader.",
instruction->handler_idx, name_from_cf_type(ctx->cf_type));
}
vkd3d-shader/ir: Validate instruction handlers.
2023-08-29 12:35:01 -07:00
static void vsir_validate_instruction(struct validation_context *ctx)
{
vkd3d-shader/ir: Store the shader version in struct vsir_program.
2024-01-16 07:40:30 -08:00
const struct vkd3d_shader_version *version = &ctx->program->shader_version;
vkd3d-shader/ir: Introduce struct vsir_program.
2024-01-16 05:47:34 -08:00
const struct vkd3d_shader_instruction *instruction;
vkd3d-shader/ir: Validate register types.
2023-08-29 12:58:31 -07:00
size_t i;
vkd3d-shader/ir: Validate instruction handlers.
2023-08-29 12:35:01 -07:00
vkd3d-shader/ir: Store the shader version in struct vsir_program.
2024-01-16 07:40:30 -08:00
instruction = &ctx->program->instructions.elements[ctx->instruction_idx];
vkd3d-shader/ir: Validate instruction handlers.
2023-08-29 12:35:01 -07:00
ctx->parser->location = instruction->location;
vkd3d-shader/ir: Validate register types.
2023-08-29 12:58:31 -07:00
for (i = 0; i < instruction->dst_count; ++i)
vsir_validate_dst_param(ctx, &instruction->dst[i]);
for (i = 0; i < instruction->src_count; ++i)
vsir_validate_src_param(ctx, &instruction->src[i]);
vkd3d-shader/ir: Validate instruction handlers.
2023-08-29 12:35:01 -07:00
if (instruction->handler_idx >= VKD3DSIH_INVALID)
{
validator_error(ctx, VKD3D_SHADER_ERROR_VSIR_INVALID_HANDLER, "Invalid instruction handler %#x.",
instruction->handler_idx);
}
vkd3d-shader/ir: Validate the DCL_TEMPS instruction.
2023-10-24 18:08:00 -07:00
vkd3d-shader/ir: Keep track of hull shader phases.
2023-11-06 14:11:03 -08:00
switch (instruction->handler_idx)
{
case VKD3DSIH_HS_DECLS:
case VKD3DSIH_HS_CONTROL_POINT_PHASE:
case VKD3DSIH_HS_FORK_PHASE:
case VKD3DSIH_HS_JOIN_PHASE:
vsir_validate_dst_count(ctx, instruction, 0);
vsir_validate_src_count(ctx, instruction, 0);
vkd3d-shader/ir: Store the shader version in struct vsir_program.
2024-01-16 07:40:30 -08:00
if (version->type != VKD3D_SHADER_TYPE_HULL)
vkd3d-shader/ir: Keep track of hull shader phases.
2023-11-06 14:11:03 -08:00
validator_error(ctx, VKD3D_SHADER_ERROR_VSIR_INVALID_HANDLER, "Phase instruction %#x is only valid in a hull shader.",
instruction->handler_idx);
if (ctx->depth != 0)
vkd3d-shader/ir: Validate that structured CF does not appear in block-based shaders.
2024-01-12 00:28:14 -08:00
validator_error(ctx, VKD3D_SHADER_ERROR_VSIR_INVALID_CONTROL_FLOW, "Phase instruction %#x must appear to top level.",
vkd3d-shader/ir: Keep track of hull shader phases.
2023-11-06 14:11:03 -08:00
instruction->handler_idx);
ctx->phase = instruction->handler_idx;
vkd3d-shader/ir: Validate the TEMP register indices in each HS phase.
2023-11-07 14:21:11 -08:00
ctx->dcl_temps_found = false;
ctx->temp_count = 0;
vkd3d-shader/ir: Keep track of hull shader phases.
2023-11-06 14:11:03 -08:00
return;
default:
break;
}
vkd3d-shader/ir: Store the shader version in struct vsir_program.
2024-01-16 07:40:30 -08:00
if (version->type == VKD3D_SHADER_TYPE_HULL && ctx->phase == VKD3DSIH_INVALID)
validator_error(ctx, VKD3D_SHADER_ERROR_VSIR_INVALID_HANDLER,
"Instruction %#x appear before any phase instruction in a hull shader.",
vkd3d-shader/ir: Keep track of hull shader phases.
2023-11-06 14:11:03 -08:00
instruction->handler_idx);
vkd3d-shader/ir: Validate that structured CF does not appear in block-based shaders.
2024-01-12 00:28:14 -08:00
/* We support two different control flow types in shaders:
* block-based, like DXIL and SPIR-V, and structured, like D3DBC
* and TPF. The shader is detected as block-based when its first
* instruction, except for DCL_* and phases, is a LABEL. Currently
* we mandate that each shader is either purely block-based or
* purely structured. In principle we could allow structured
* constructs in a block, provided they are confined in a single
* block, but need for that hasn't arisen yet, so we don't. */
if (ctx->cf_type == CF_TYPE_UNKNOWN && !(instruction->handler_idx >= VKD3DSIH_DCL
&& instruction->handler_idx <= VKD3DSIH_DCL_VERTICES_OUT))
{
if (instruction->handler_idx == VKD3DSIH_LABEL)
ctx->cf_type = CF_TYPE_BLOCKS;
else
ctx->cf_type = CF_TYPE_STRUCTURED;
}
vkd3d-shader/ir: Validate the DCL_TEMPS instruction.
2023-10-24 18:08:00 -07:00
switch (instruction->handler_idx)
{
case VKD3DSIH_DCL_TEMPS:
vsir_validate_dst_count(ctx, instruction, 0);
vsir_validate_src_count(ctx, instruction, 0);
vkd3d-shader/ir: Validate the TEMP register indices in each HS phase.
2023-11-07 14:21:11 -08:00
if (ctx->dcl_temps_found)
vkd3d-shader/ir: Validate the index of a TEMP register.
2023-10-24 17:55:37 -07:00
validator_error(ctx, VKD3D_SHADER_ERROR_VSIR_DUPLICATE_DCL_TEMPS, "Duplicate DCL_TEMPS instruction.");
vkd3d-shader/ir: Validate the TEMP register indices in each HS phase.
2023-11-07 14:21:11 -08:00
if (instruction->declaration.count > ctx->parser->shader_desc.temp_count)
validator_error(ctx, VKD3D_SHADER_ERROR_VSIR_INVALID_DCL_TEMPS, "Invalid DCL_TEMPS count %u, expected at most %u.",
vkd3d-shader/ir: Validate the index of a TEMP register.
2023-10-24 17:55:37 -07:00
instruction->declaration.count, ctx->parser->shader_desc.temp_count);
vkd3d-shader/ir: Validate the TEMP register indices in each HS phase.
2023-11-07 14:21:11 -08:00
ctx->dcl_temps_found = true;
ctx->temp_count = instruction->declaration.count;
vkd3d-shader/ir: Validate the DCL_TEMPS instruction.
2023-10-24 18:08:00 -07:00
break;
vkd3d-shader/ir: Check that IF blocks are correctly nested.
2023-11-06 04:47:34 -08:00
case VKD3DSIH_IF:
vkd3d-shader/ir: Validate that structured CF does not appear in block-based shaders.
2024-01-12 00:28:14 -08:00
vsir_validate_cf_type(ctx, instruction, CF_TYPE_STRUCTURED);
vkd3d-shader/ir: Check that IF blocks are correctly nested.
2023-11-06 04:47:34 -08:00
vsir_validate_dst_count(ctx, instruction, 0);
vsir_validate_src_count(ctx, instruction, 1);
if (!vkd3d_array_reserve((void **)&ctx->blocks, &ctx->blocks_capacity, ctx->depth + 1, sizeof(*ctx->blocks)))
return;
ctx->blocks[ctx->depth++] = instruction->handler_idx;
break;
vkd3d-shader/ir: Validate IFC instructions.
2023-11-16 13:32:13 -08:00
case VKD3DSIH_IFC:
vkd3d-shader/ir: Validate that structured CF does not appear in block-based shaders.
2024-01-12 00:28:14 -08:00
vsir_validate_cf_type(ctx, instruction, CF_TYPE_STRUCTURED);
vkd3d-shader/ir: Validate IFC instructions.
2023-11-16 13:32:13 -08:00
vsir_validate_dst_count(ctx, instruction, 0);
vsir_validate_src_count(ctx, instruction, 2);
if (!vkd3d_array_reserve((void **)&ctx->blocks, &ctx->blocks_capacity, ctx->depth + 1, sizeof(*ctx->blocks)))
return;
ctx->blocks[ctx->depth++] = VKD3DSIH_IF;
break;
vkd3d-shader/ir: Check that IF blocks are correctly nested.
2023-11-06 04:47:34 -08:00
case VKD3DSIH_ELSE:
vkd3d-shader/ir: Validate that structured CF does not appear in block-based shaders.
2024-01-12 00:28:14 -08:00
vsir_validate_cf_type(ctx, instruction, CF_TYPE_STRUCTURED);
vkd3d-shader/ir: Check that IF blocks are correctly nested.
2023-11-06 04:47:34 -08:00
vsir_validate_dst_count(ctx, instruction, 0);
vsir_validate_src_count(ctx, instruction, 0);
if (ctx->depth == 0 || ctx->blocks[ctx->depth - 1] != VKD3DSIH_IF)
vkd3d-shader/ir: Validate that structured CF does not appear in block-based shaders.
2024-01-12 00:28:14 -08:00
validator_error(ctx, VKD3D_SHADER_ERROR_VSIR_INVALID_CONTROL_FLOW, "ELSE instruction doesn't terminate IF block.");
vkd3d-shader/ir: Check that IF blocks are correctly nested.
2023-11-06 04:47:34 -08:00
else
ctx->blocks[ctx->depth - 1] = instruction->handler_idx;
break;
case VKD3DSIH_ENDIF:
vkd3d-shader/ir: Validate that structured CF does not appear in block-based shaders.
2024-01-12 00:28:14 -08:00
vsir_validate_cf_type(ctx, instruction, CF_TYPE_STRUCTURED);
vkd3d-shader/ir: Check that IF blocks are correctly nested.
2023-11-06 04:47:34 -08:00
vsir_validate_dst_count(ctx, instruction, 0);
vsir_validate_src_count(ctx, instruction, 0);
if (ctx->depth == 0 || (ctx->blocks[ctx->depth - 1] != VKD3DSIH_IF && ctx->blocks[ctx->depth - 1] != VKD3DSIH_ELSE))
vkd3d-shader/ir: Validate that structured CF does not appear in block-based shaders.
2024-01-12 00:28:14 -08:00
validator_error(ctx, VKD3D_SHADER_ERROR_VSIR_INVALID_CONTROL_FLOW, "ENDIF instruction doesn't terminate IF/ELSE block.");
vkd3d-shader/ir: Check that IF blocks are correctly nested.
2023-11-06 04:47:34 -08:00
else
--ctx->depth;
break;
vkd3d-shader/ir: Check that LOOP blocks are correctly nested.
2023-11-06 04:54:07 -08:00
case VKD3DSIH_LOOP:
vkd3d-shader/ir: Validate that structured CF does not appear in block-based shaders.
2024-01-12 00:28:14 -08:00
vsir_validate_cf_type(ctx, instruction, CF_TYPE_STRUCTURED);
vkd3d-shader/ir: Check that LOOP blocks are correctly nested.
2023-11-06 04:54:07 -08:00
vsir_validate_dst_count(ctx, instruction, 0);
vkd3d-shader/ir: Store the shader version in struct vsir_program.
2024-01-16 07:40:30 -08:00
vsir_validate_src_count(ctx, instruction, version->major <= 3 ? 2 : 0);
vkd3d-shader/ir: Check that LOOP blocks are correctly nested.
2023-11-06 04:54:07 -08:00
if (!vkd3d_array_reserve((void **)&ctx->blocks, &ctx->blocks_capacity, ctx->depth + 1, sizeof(*ctx->blocks)))
return;
ctx->blocks[ctx->depth++] = instruction->handler_idx;
break;
case VKD3DSIH_ENDLOOP:
vkd3d-shader/ir: Validate that structured CF does not appear in block-based shaders.
2024-01-12 00:28:14 -08:00
vsir_validate_cf_type(ctx, instruction, CF_TYPE_STRUCTURED);
vkd3d-shader/ir: Check that LOOP blocks are correctly nested.
2023-11-06 04:54:07 -08:00
vsir_validate_dst_count(ctx, instruction, 0);
vsir_validate_src_count(ctx, instruction, 0);
if (ctx->depth == 0 || ctx->blocks[ctx->depth - 1] != VKD3DSIH_LOOP)
vkd3d-shader/ir: Validate that structured CF does not appear in block-based shaders.
2024-01-12 00:28:14 -08:00
validator_error(ctx, VKD3D_SHADER_ERROR_VSIR_INVALID_CONTROL_FLOW, "ENDLOOP instruction doesn't terminate LOOP block.");
vkd3d-shader/ir: Check that LOOP blocks are correctly nested.
2023-11-06 04:54:07 -08:00
else
--ctx->depth;
break;
vkd3d-shader/ir: Check that REP blocks are correctly nested.
2023-11-06 04:56:38 -08:00
case VKD3DSIH_REP:
vkd3d-shader/ir: Validate that structured CF does not appear in block-based shaders.
2024-01-12 00:28:14 -08:00
vsir_validate_cf_type(ctx, instruction, CF_TYPE_STRUCTURED);
vkd3d-shader/ir: Check that REP blocks are correctly nested.
2023-11-06 04:56:38 -08:00
vsir_validate_dst_count(ctx, instruction, 0);
vsir_validate_src_count(ctx, instruction, 1);
if (!vkd3d_array_reserve((void **)&ctx->blocks, &ctx->blocks_capacity, ctx->depth + 1, sizeof(*ctx->blocks)))
return;
ctx->blocks[ctx->depth++] = instruction->handler_idx;
break;
case VKD3DSIH_ENDREP:
vkd3d-shader/ir: Validate that structured CF does not appear in block-based shaders.
2024-01-12 00:28:14 -08:00
vsir_validate_cf_type(ctx, instruction, CF_TYPE_STRUCTURED);
vkd3d-shader/ir: Check that REP blocks are correctly nested.
2023-11-06 04:56:38 -08:00
vsir_validate_dst_count(ctx, instruction, 0);
vsir_validate_src_count(ctx, instruction, 0);
if (ctx->depth == 0 || ctx->blocks[ctx->depth - 1] != VKD3DSIH_REP)
vkd3d-shader/ir: Validate that structured CF does not appear in block-based shaders.
2024-01-12 00:28:14 -08:00
validator_error(ctx, VKD3D_SHADER_ERROR_VSIR_INVALID_CONTROL_FLOW, "ENDREP instruction doesn't terminate REP block.");
vkd3d-shader/ir: Check that REP blocks are correctly nested.
2023-11-06 04:56:38 -08:00
else
--ctx->depth;
break;
vkd3d-shader/ir: Check that SWITCH blocks are correctly nested.
2023-11-06 04:57:25 -08:00
case VKD3DSIH_SWITCH:
vkd3d-shader/ir: Validate that structured CF does not appear in block-based shaders.
2024-01-12 00:28:14 -08:00
vsir_validate_cf_type(ctx, instruction, CF_TYPE_STRUCTURED);
vkd3d-shader/ir: Check that SWITCH blocks are correctly nested.
2023-11-06 04:57:25 -08:00
vsir_validate_dst_count(ctx, instruction, 0);
vsir_validate_src_count(ctx, instruction, 1);
if (!vkd3d_array_reserve((void **)&ctx->blocks, &ctx->blocks_capacity, ctx->depth + 1, sizeof(*ctx->blocks)))
return;
ctx->blocks[ctx->depth++] = instruction->handler_idx;
break;
case VKD3DSIH_ENDSWITCH:
vkd3d-shader/ir: Validate that structured CF does not appear in block-based shaders.
2024-01-12 00:28:14 -08:00
vsir_validate_cf_type(ctx, instruction, CF_TYPE_STRUCTURED);
vkd3d-shader/ir: Check that SWITCH blocks are correctly nested.
2023-11-06 04:57:25 -08:00
vsir_validate_dst_count(ctx, instruction, 0);
vsir_validate_src_count(ctx, instruction, 0);
if (ctx->depth == 0 || ctx->blocks[ctx->depth - 1] != VKD3DSIH_SWITCH)
vkd3d-shader/ir: Validate that structured CF does not appear in block-based shaders.
2024-01-12 00:28:14 -08:00
validator_error(ctx, VKD3D_SHADER_ERROR_VSIR_INVALID_CONTROL_FLOW, "ENDSWITCH instruction doesn't terminate SWITCH block.");
vkd3d-shader/ir: Check that SWITCH blocks are correctly nested.
2023-11-06 04:57:25 -08:00
else
--ctx->depth;
break;
vkd3d-shader/ir: Validate RET instructions.
2024-01-12 02:10:22 -08:00
case VKD3DSIH_RET:
vsir_validate_dst_count(ctx, instruction, 0);
vsir_validate_src_count(ctx, instruction, 0);
break;
vkd3d-shader/ir: Validate LABEL instructions.
2023-12-22 06:58:55 -08:00
case VKD3DSIH_LABEL:
vsir_validate_cf_type(ctx, instruction, CF_TYPE_BLOCKS);
vsir_validate_dst_count(ctx, instruction, 0);
vsir_validate_src_count(ctx, instruction, 1);
if (instruction->src_count >= 1 && !vsir_register_is_label(&instruction->src[0].reg))
validator_error(ctx, VKD3D_SHADER_ERROR_VSIR_INVALID_REGISTER_TYPE,
"Invalid register of type %#x in a LABEL instruction, expected LABEL.",
instruction->src[0].reg.type);
break;
vkd3d-shader/ir: Validate BRANCH instructions.
2023-12-22 08:11:41 -08:00
case VKD3DSIH_BRANCH:
vsir_validate_cf_type(ctx, instruction, CF_TYPE_BLOCKS);
vsir_validate_dst_count(ctx, instruction, 0);
if (!vsir_validate_src_min_count(ctx, instruction, 1))
break;
if (vsir_register_is_label(&instruction->src[0].reg))
{
/* Unconditional branch: parameters are jump label,
* optional merge label, optional continue label. */
vsir_validate_src_max_count(ctx, instruction, 3);
for (i = 0; i < instruction->src_count; ++i)
{
if (!vsir_register_is_label(&instruction->src[i].reg))
validator_error(ctx, VKD3D_SHADER_ERROR_VSIR_INVALID_REGISTER_TYPE,
"Invalid register of type %#x in unconditional BRANCH instruction, expected LABEL.",
instruction->src[i].reg.type);
}
}
else
{
/* Conditional branch: parameters are condition, true
* jump label, false jump label, optional merge label,
* optional continue label. */
vsir_validate_src_min_count(ctx, instruction, 3);
vsir_validate_src_max_count(ctx, instruction, 5);
for (i = 1; i < instruction->src_count; ++i)
{
if (!vsir_register_is_label(&instruction->src[i].reg))
validator_error(ctx, VKD3D_SHADER_ERROR_VSIR_INVALID_REGISTER_TYPE,
"Invalid register of type %#x in conditional BRANCH instruction, expected LABEL.",
instruction->src[i].reg.type);
}
}
break;
vkd3d-shader/ir: Validate SWITCH_MONOLITHIC instructions.
2024-01-12 01:50:30 -08:00
case VKD3DSIH_SWITCH_MONOLITHIC:
{
unsigned int case_count;
vsir_validate_cf_type(ctx, instruction, CF_TYPE_BLOCKS);
vsir_validate_dst_count(ctx, instruction, 0);
/* Parameters are source, default label, merge label and
* then pairs of constant value and case label. */
if (!vsir_validate_src_min_count(ctx, instruction, 3))
break;
if (instruction->src_count % 2 != 1)
validator_error(ctx, VKD3D_SHADER_ERROR_VSIR_INVALID_SOURCE_COUNT,
"Invalid source count %u for a monolithic SWITCH instruction, it must be an odd number.",
instruction->src_count);
if (!vsir_register_is_label(&instruction->src[1].reg))
validator_error(ctx, VKD3D_SHADER_ERROR_VSIR_INVALID_REGISTER_TYPE,
"Invalid default label register of type %#x in monolithic SWITCH instruction, expected LABEL.",
instruction->src[1].reg.type);
if (!vsir_register_is_label(&instruction->src[2].reg))
validator_error(ctx, VKD3D_SHADER_ERROR_VSIR_INVALID_REGISTER_TYPE,
"Invalid merge label register of type %#x in monolithic SWITCH instruction, expected LABEL.",
instruction->src[2].reg.type);
case_count = (instruction->src_count - 3) / 2;
for (i = 0; i < case_count; ++i)
{
unsigned int value_idx = 3 + 2 * i;
unsigned int label_idx = 3 + 2 * i + 1;
if (!register_is_constant(&instruction->src[value_idx].reg))
validator_error(ctx, VKD3D_SHADER_ERROR_VSIR_INVALID_REGISTER_TYPE,
"Invalid value register for case %zu of type %#x in monolithic SWITCH instruction, "
"expected IMMCONST or IMMCONST64.", i, instruction->src[value_idx].reg.type);
if (!vsir_register_is_label(&instruction->src[label_idx].reg))
validator_error(ctx, VKD3D_SHADER_ERROR_VSIR_INVALID_REGISTER_TYPE,
"Invalid label register for case %zu of type %#x in monolithic SWITCH instruction, "
"expected LABEL.", i, instruction->src[value_idx].reg.type);
}
break;
}
vkd3d-shader/ir: Validate the DCL_TEMPS instruction.
2023-10-24 18:08:00 -07:00
default:
break;
}
vkd3d-shader/ir: Validate instruction handlers.
2023-08-29 12:35:01 -07:00
}
vkd3d-shader/ir: Check that TEMP registers have consistent dimensions.
2024-01-10 02:27:03 -08:00
enum vkd3d_result vsir_validate(struct vkd3d_shader_parser *parser)
vkd3d-shader/ir: Introduce a boilerplate to validate the generated IR. For the moment the validator is trivial, it never fails. Checks will be added incrementally.
2023-08-29 12:20:35 -07:00
{
vkd3d-shader/ir: Keep track of hull shader phases.
2023-11-06 14:11:03 -08:00
struct validation_context ctx =
{
.parser = parser,
vkd3d-shader/ir: Store the shader version in struct vsir_program.
2024-01-16 07:40:30 -08:00
.program = &parser->program,
vkd3d-shader/ir: Keep track of hull shader phases.
2023-11-06 14:11:03 -08:00
.phase = VKD3DSIH_INVALID,
};
vkd3d-shader/ir: Check that SSA registers are used validly. Specifically, they are assigned only once and only assigned components are used. Right now we don't check that the assignment dominates all usages.
2024-01-10 02:58:44 -08:00
unsigned int i;
vkd3d-shader/ir: Validate instruction handlers.
2023-08-29 12:35:01 -07:00
vkd3d-shader/ir: Introduce a boilerplate to validate the generated IR. For the moment the validator is trivial, it never fails. Checks will be added incrementally.
2023-08-29 12:20:35 -07:00
if (!(parser->config_flags & VKD3D_SHADER_CONFIG_FLAG_FORCE_VALIDATION))
vkd3d-shader/ir: Check that TEMP registers have consistent dimensions.
2024-01-10 02:27:03 -08:00
return VKD3D_OK;
if (!(ctx.temps = vkd3d_calloc(parser->shader_desc.temp_count, sizeof(*ctx.temps))))
goto fail;
vkd3d-shader/ir: Validate instruction handlers.
2023-08-29 12:35:01 -07:00
vkd3d-shader/ir: Check that SSA registers have consistent dimensions.
2024-01-10 02:31:40 -08:00
if (!(ctx.ssas = vkd3d_calloc(parser->shader_desc.ssa_count, sizeof(*ctx.ssas))))
goto fail;
vkd3d-shader/ir: Introduce struct vsir_program.
2024-01-16 05:47:34 -08:00
for (ctx.instruction_idx = 0; ctx.instruction_idx < parser->program.instructions.count; ++ctx.instruction_idx)
vkd3d-shader/ir: Validate instruction handlers.
2023-08-29 12:35:01 -07:00
vsir_validate_instruction(&ctx);
vkd3d-shader/ir: Check that IF blocks are correctly nested.
2023-11-06 04:47:34 -08:00
vkd3d-shader/ir: Check that SSA registers are used validly. Specifically, they are assigned only once and only assigned components are used. Right now we don't check that the assignment dominates all usages.
2024-01-10 02:58:44 -08:00
ctx.invalid_instruction_idx = true;
vkd3d-shader/ir: Check that IF blocks are correctly nested.
2023-11-06 04:47:34 -08:00
if (ctx.depth != 0)
vkd3d-shader/ir: Validate that structured CF does not appear in block-based shaders.
2024-01-12 00:28:14 -08:00
validator_error(&ctx, VKD3D_SHADER_ERROR_VSIR_INVALID_CONTROL_FLOW, "%zu nested blocks were not closed.", ctx.depth);
vkd3d-shader/ir: Check that IF blocks are correctly nested.
2023-11-06 04:47:34 -08:00
vkd3d-shader/ir: Check that SSA registers are used validly. Specifically, they are assigned only once and only assigned components are used. Right now we don't check that the assignment dominates all usages.
2024-01-10 02:58:44 -08:00
for (i = 0; i < parser->shader_desc.ssa_count; ++i)
{
struct validation_context_ssa_data *data = &ctx.ssas[i];
if ((data->write_mask | data->read_mask) != data->write_mask)
validator_error(&ctx, VKD3D_SHADER_ERROR_VSIR_INVALID_SSA_USAGE,
"SSA register %u has invalid read mask %#x, which is not a subset of the write mask %#x "
"at the point of definition.", i, data->read_mask, data->write_mask);
}
vkd3d-shader/ir: Use vkd3d_free() instead of free().
2024-01-10 02:14:39 -08:00
vkd3d_free(ctx.blocks);
vkd3d-shader/ir: Check that TEMP registers have consistent dimensions.
2024-01-10 02:27:03 -08:00
vkd3d_free(ctx.temps);
vkd3d-shader/ir: Check that SSA registers have consistent dimensions.
2024-01-10 02:31:40 -08:00
vkd3d_free(ctx.ssas);
vkd3d-shader/ir: Check that TEMP registers have consistent dimensions.
2024-01-10 02:27:03 -08:00
return VKD3D_OK;
fail:
vkd3d_free(ctx.blocks);
vkd3d_free(ctx.temps);
vkd3d-shader/ir: Check that SSA registers have consistent dimensions.
2024-01-10 02:31:40 -08:00
vkd3d_free(ctx.ssas);
vkd3d-shader/ir: Check that TEMP registers have consistent dimensions.
2024-01-10 02:27:03 -08:00
return VKD3D_ERROR_OUT_OF_MEMORY;
vkd3d-shader/ir: Introduce a boilerplate to validate the generated IR. For the moment the validator is trivial, it never fails. Checks will be added incrementally.
2023-08-29 12:20:35 -07:00
}
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