2021-03-02 13:34:46 -08:00
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/*
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* HLSL optimization and code generation
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*
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* Copyright 2019-2020 Zebediah Figura for CodeWeavers
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2.1 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA
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*/
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#include "hlsl.h"
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2021-03-28 12:46:55 -07:00
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#include <stdio.h>
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2021-04-15 17:03:46 -07:00
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#include "vkd3d_d3dx9shader.h"
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2021-03-28 12:46:55 -07:00
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/* Split uniforms into two variables representing the constant and temp
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* registers, and copy the former to the latter, so that writes to uniforms
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* work. */
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2021-04-15 17:03:45 -07:00
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static void prepend_uniform_copy(struct hlsl_ctx *ctx, struct list *instrs, struct hlsl_ir_var *temp)
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2021-03-28 12:46:55 -07:00
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{
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struct vkd3d_string_buffer *name;
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2021-04-15 17:03:45 -07:00
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struct hlsl_ir_var *uniform;
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2021-04-08 21:38:22 -07:00
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struct hlsl_ir_store *store;
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2021-03-28 12:46:55 -07:00
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struct hlsl_ir_load *load;
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2021-04-15 17:03:45 -07:00
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/* Use the synthetic name for the temp, rather than the uniform, so that we
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* can write the uniform name into the shader reflection data. */
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2021-05-20 22:32:20 -07:00
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if (!(uniform = hlsl_new_var(ctx, temp->name, temp->data_type, temp->loc, NULL, 0, temp->reg_reservation)))
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2021-03-28 12:46:55 -07:00
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return;
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2021-04-15 17:03:45 -07:00
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list_add_before(&temp->scope_entry, &uniform->scope_entry);
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list_add_tail(&ctx->extern_vars, &uniform->extern_entry);
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uniform->is_uniform = 1;
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2021-04-15 17:03:46 -07:00
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uniform->is_param = temp->is_param;
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2021-04-15 17:03:45 -07:00
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2021-05-20 22:32:21 -07:00
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if (!(name = hlsl_get_string_buffer(ctx)))
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2021-03-28 12:46:55 -07:00
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return;
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2021-04-15 17:03:45 -07:00
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vkd3d_string_buffer_printf(name, "<temp-%s>", temp->name);
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2021-05-20 22:32:20 -07:00
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temp->name = hlsl_strdup(ctx, name->buffer);
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2021-05-20 22:32:21 -07:00
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hlsl_release_string_buffer(ctx, name);
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2021-03-28 12:46:55 -07:00
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2021-05-20 22:32:20 -07:00
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if (!(load = hlsl_new_var_load(ctx, uniform, temp->loc)))
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2021-03-28 12:46:55 -07:00
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return;
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list_add_head(instrs, &load->node.entry);
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2021-05-20 22:32:20 -07:00
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if (!(store = hlsl_new_simple_store(ctx, temp, &load->node)))
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2021-03-28 12:46:55 -07:00
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return;
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list_add_after(&load->node.entry, &store->node.entry);
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}
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2021-03-02 13:34:46 -08:00
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2021-03-28 12:46:57 -07:00
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static void prepend_input_copy(struct hlsl_ctx *ctx, struct list *instrs, struct hlsl_ir_var *var,
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struct hlsl_type *type, unsigned int field_offset, const struct hlsl_semantic *semantic)
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2021-03-28 12:46:57 -07:00
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{
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struct vkd3d_string_buffer *name;
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2021-04-27 10:14:19 -07:00
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struct hlsl_semantic new_semantic;
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2021-03-28 12:46:57 -07:00
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struct hlsl_ir_constant *offset;
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2021-04-08 21:38:22 -07:00
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struct hlsl_ir_store *store;
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2021-03-28 12:46:57 -07:00
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struct hlsl_ir_load *load;
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2021-04-27 10:14:20 -07:00
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struct hlsl_ir_var *input;
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2021-03-28 12:46:57 -07:00
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2021-05-20 22:32:21 -07:00
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if (!(name = hlsl_get_string_buffer(ctx)))
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2021-03-28 12:46:57 -07:00
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return;
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2021-04-27 10:14:19 -07:00
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vkd3d_string_buffer_printf(name, "<input-%s%u>", semantic->name, semantic->index);
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2021-05-20 22:32:20 -07:00
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if (!(new_semantic.name = hlsl_strdup(ctx, semantic->name)))
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2021-03-28 12:46:57 -07:00
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{
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2021-05-20 22:32:21 -07:00
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hlsl_release_string_buffer(ctx, name);
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2021-03-28 12:46:57 -07:00
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return;
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}
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2021-04-27 10:14:19 -07:00
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new_semantic.index = semantic->index;
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2021-05-20 22:32:20 -07:00
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if (!(input = hlsl_new_var(ctx, hlsl_strdup(ctx, name->buffer), type, var->loc, &new_semantic, 0, NULL)))
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2021-04-27 10:14:19 -07:00
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{
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2021-05-20 22:32:21 -07:00
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hlsl_release_string_buffer(ctx, name);
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2021-04-27 10:14:19 -07:00
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vkd3d_free((void *)new_semantic.name);
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return;
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}
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2021-05-20 22:32:21 -07:00
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hlsl_release_string_buffer(ctx, name);
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2021-04-27 10:14:20 -07:00
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input->is_input_semantic = 1;
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input->is_param = var->is_param;
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list_add_before(&var->scope_entry, &input->scope_entry);
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list_add_tail(&ctx->extern_vars, &input->extern_entry);
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2021-03-28 12:46:57 -07:00
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2021-05-20 22:32:20 -07:00
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if (!(load = hlsl_new_var_load(ctx, input, var->loc)))
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2021-03-28 12:46:57 -07:00
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return;
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list_add_head(instrs, &load->node.entry);
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if (!(offset = hlsl_new_uint_constant(ctx, field_offset * 4, var->loc)))
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return;
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list_add_after(&load->node.entry, &offset->node.entry);
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2021-05-20 22:32:20 -07:00
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if (!(store = hlsl_new_store(ctx, var, &offset->node, &load->node, 0, var->loc)))
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2021-03-28 12:46:57 -07:00
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return;
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list_add_after(&offset->node.entry, &store->node.entry);
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}
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static void prepend_input_struct_copy(struct hlsl_ctx *ctx, struct list *instrs, struct hlsl_ir_var *var,
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struct hlsl_type *type, unsigned int field_offset)
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{
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struct hlsl_struct_field *field;
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LIST_FOR_EACH_ENTRY(field, type->e.elements, struct hlsl_struct_field, entry)
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{
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if (field->type->type == HLSL_CLASS_STRUCT)
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prepend_input_struct_copy(ctx, instrs, var, field->type, field_offset + field->reg_offset);
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2021-04-27 10:14:19 -07:00
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else if (field->semantic.name)
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prepend_input_copy(ctx, instrs, var, field->type, field_offset + field->reg_offset, &field->semantic);
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2021-03-28 12:46:57 -07:00
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else
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hlsl_error(ctx, field->loc, VKD3D_SHADER_ERROR_HLSL_MISSING_SEMANTIC,
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"Field '%s' is missing a semantic.", field->name);
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}
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}
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2021-04-27 10:14:20 -07:00
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/* Split inputs into two variables representing the semantic and temp registers,
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* and copy the former to the latter, so that writes to input variables work. */
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2021-03-28 12:46:57 -07:00
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static void prepend_input_var_copy(struct hlsl_ctx *ctx, struct list *instrs, struct hlsl_ir_var *var)
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{
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if (var->data_type->type == HLSL_CLASS_STRUCT)
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prepend_input_struct_copy(ctx, instrs, var, var->data_type, 0);
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2021-04-27 10:14:19 -07:00
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else if (var->semantic.name)
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prepend_input_copy(ctx, instrs, var, var->data_type, 0, &var->semantic);
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2021-03-28 12:46:57 -07:00
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}
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2021-03-28 12:46:59 -07:00
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static void append_output_copy(struct hlsl_ctx *ctx, struct list *instrs, struct hlsl_ir_var *var,
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2021-04-27 10:14:19 -07:00
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struct hlsl_type *type, unsigned int field_offset, const struct hlsl_semantic *semantic)
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2021-03-28 12:46:59 -07:00
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{
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struct vkd3d_string_buffer *name;
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2021-04-27 10:14:19 -07:00
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struct hlsl_semantic new_semantic;
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2021-03-28 12:46:59 -07:00
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struct hlsl_ir_constant *offset;
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2021-04-08 21:38:22 -07:00
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struct hlsl_ir_store *store;
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2021-04-27 10:14:20 -07:00
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struct hlsl_ir_var *output;
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2021-03-28 12:46:59 -07:00
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struct hlsl_ir_load *load;
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2021-05-20 22:32:21 -07:00
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if (!(name = hlsl_get_string_buffer(ctx)))
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2021-03-28 12:46:59 -07:00
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return;
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2021-04-27 10:14:19 -07:00
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vkd3d_string_buffer_printf(name, "<output-%s%u>", semantic->name, semantic->index);
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2021-05-20 22:32:20 -07:00
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if (!(new_semantic.name = hlsl_strdup(ctx, semantic->name)))
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2021-04-27 10:14:19 -07:00
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{
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2021-05-20 22:32:21 -07:00
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hlsl_release_string_buffer(ctx, name);
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2021-04-27 10:14:19 -07:00
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return;
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}
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new_semantic.index = semantic->index;
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2021-05-20 22:32:20 -07:00
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if (!(output = hlsl_new_var(ctx, hlsl_strdup(ctx, name->buffer), type, var->loc, &new_semantic, 0, NULL)))
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2021-03-28 12:46:59 -07:00
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{
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2021-04-27 10:14:19 -07:00
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vkd3d_free((void *)new_semantic.name);
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2021-05-20 22:32:21 -07:00
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hlsl_release_string_buffer(ctx, name);
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2021-03-28 12:46:59 -07:00
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return;
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}
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2021-05-20 22:32:21 -07:00
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hlsl_release_string_buffer(ctx, name);
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2021-04-27 10:14:20 -07:00
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output->is_output_semantic = 1;
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output->is_param = var->is_param;
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list_add_before(&var->scope_entry, &output->scope_entry);
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list_add_tail(&ctx->extern_vars, &output->extern_entry);
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2021-03-28 12:46:59 -07:00
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if (!(offset = hlsl_new_uint_constant(ctx, field_offset * 4, var->loc)))
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return;
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list_add_tail(instrs, &offset->node.entry);
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2021-05-20 22:32:20 -07:00
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if (!(load = hlsl_new_load(ctx, var, &offset->node, type, var->loc)))
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2021-03-28 12:46:59 -07:00
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return;
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list_add_after(&offset->node.entry, &load->node.entry);
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2021-05-20 22:32:20 -07:00
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if (!(store = hlsl_new_store(ctx, output, NULL, &load->node, 0, var->loc)))
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2021-03-28 12:46:59 -07:00
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return;
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list_add_after(&load->node.entry, &store->node.entry);
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}
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static void append_output_struct_copy(struct hlsl_ctx *ctx, struct list *instrs, struct hlsl_ir_var *var,
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struct hlsl_type *type, unsigned int field_offset)
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{
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struct hlsl_struct_field *field;
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LIST_FOR_EACH_ENTRY(field, type->e.elements, struct hlsl_struct_field, entry)
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{
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if (field->type->type == HLSL_CLASS_STRUCT)
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append_output_struct_copy(ctx, instrs, var, field->type, field_offset + field->reg_offset);
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2021-04-27 10:14:19 -07:00
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else if (field->semantic.name)
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append_output_copy(ctx, instrs, var, field->type, field_offset + field->reg_offset, &field->semantic);
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2021-03-28 12:46:59 -07:00
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else
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hlsl_error(ctx, field->loc, VKD3D_SHADER_ERROR_HLSL_MISSING_SEMANTIC,
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"Field '%s' is missing a semantic.", field->name);
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}
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}
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2021-04-27 10:14:20 -07:00
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/* Split outputs into two variables representing the temp and semantic
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2021-03-28 12:46:59 -07:00
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* registers, and copy the former to the latter, so that reads from output
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2021-04-27 10:14:20 -07:00
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* variables work. */
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2021-03-28 12:46:59 -07:00
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static void append_output_var_copy(struct hlsl_ctx *ctx, struct list *instrs, struct hlsl_ir_var *var)
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{
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if (var->data_type->type == HLSL_CLASS_STRUCT)
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append_output_struct_copy(ctx, instrs, var, var->data_type, 0);
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2021-04-27 10:14:19 -07:00
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else if (var->semantic.name)
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append_output_copy(ctx, instrs, var, var->data_type, 0, &var->semantic);
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2021-03-28 12:46:59 -07:00
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}
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2021-03-16 14:31:53 -07:00
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static bool transform_ir(struct hlsl_ctx *ctx, bool (*func)(struct hlsl_ctx *ctx, struct hlsl_ir_node *, void *),
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struct list *instrs, void *context)
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{
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struct hlsl_ir_node *instr, *next;
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bool progress = 0;
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LIST_FOR_EACH_ENTRY_SAFE(instr, next, instrs, struct hlsl_ir_node, entry)
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{
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if (instr->type == HLSL_IR_IF)
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{
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struct hlsl_ir_if *iff = hlsl_ir_if(instr);
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progress |= transform_ir(ctx, func, &iff->then_instrs, context);
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progress |= transform_ir(ctx, func, &iff->else_instrs, context);
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}
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else if (instr->type == HLSL_IR_LOOP)
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progress |= transform_ir(ctx, func, &hlsl_ir_loop(instr)->body, context);
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progress |= func(ctx, instr, context);
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}
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return progress;
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}
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static void replace_node(struct hlsl_ir_node *old, struct hlsl_ir_node *new)
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{
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struct hlsl_src *src, *next;
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LIST_FOR_EACH_ENTRY_SAFE(src, next, &old->uses, struct hlsl_src, entry)
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{
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hlsl_src_remove(src);
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hlsl_src_from_node(src, new);
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}
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list_remove(&old->entry);
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hlsl_free_instr(old);
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}
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2021-03-16 14:31:56 -07:00
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static bool is_vec1(const struct hlsl_type *type)
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{
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return (type->type == HLSL_CLASS_SCALAR) || (type->type == HLSL_CLASS_VECTOR && type->dimx == 1);
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}
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2021-03-16 14:31:55 -07:00
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static bool fold_redundant_casts(struct hlsl_ctx *ctx, struct hlsl_ir_node *instr, void *context)
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{
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if (instr->type == HLSL_IR_EXPR)
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{
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struct hlsl_ir_expr *expr = hlsl_ir_expr(instr);
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2021-03-16 14:31:56 -07:00
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const struct hlsl_type *src_type = expr->operands[0].node->data_type;
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const struct hlsl_type *dst_type = expr->node.data_type;
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if (expr->op != HLSL_IR_UNOP_CAST)
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return false;
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2021-03-16 14:31:55 -07:00
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2021-03-17 22:22:19 -07:00
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|
|
if (hlsl_types_are_equal(src_type, dst_type)
|
2021-03-16 14:31:56 -07:00
|
|
|
|| (src_type->base_type == dst_type->base_type && is_vec1(src_type) && is_vec1(dst_type)))
|
2021-03-16 14:31:55 -07:00
|
|
|
{
|
|
|
|
replace_node(&expr->node, expr->operands[0].node);
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
2021-03-17 22:22:21 -07:00
|
|
|
static bool split_struct_copies(struct hlsl_ctx *ctx, struct hlsl_ir_node *instr, void *context)
|
|
|
|
{
|
|
|
|
const struct hlsl_struct_field *field;
|
|
|
|
const struct hlsl_ir_load *rhs_load;
|
|
|
|
const struct hlsl_ir_node *rhs;
|
|
|
|
const struct hlsl_type *type;
|
2021-04-08 21:38:22 -07:00
|
|
|
struct hlsl_ir_store *store;
|
2021-03-17 22:22:21 -07:00
|
|
|
|
2021-04-08 21:38:22 -07:00
|
|
|
if (instr->type != HLSL_IR_STORE)
|
2021-03-17 22:22:21 -07:00
|
|
|
return false;
|
|
|
|
|
2021-04-08 21:38:22 -07:00
|
|
|
store = hlsl_ir_store(instr);
|
|
|
|
rhs = store->rhs.node;
|
2021-03-17 22:22:21 -07:00
|
|
|
type = rhs->data_type;
|
|
|
|
if (type->type != HLSL_CLASS_STRUCT)
|
|
|
|
return false;
|
|
|
|
|
|
|
|
rhs_load = hlsl_ir_load(rhs);
|
|
|
|
|
|
|
|
LIST_FOR_EACH_ENTRY(field, type->e.elements, struct hlsl_struct_field, entry)
|
|
|
|
{
|
2021-04-08 21:38:22 -07:00
|
|
|
struct hlsl_ir_store *field_store;
|
2021-03-17 22:22:21 -07:00
|
|
|
struct hlsl_ir_node *offset, *add;
|
|
|
|
struct hlsl_ir_load *field_load;
|
|
|
|
struct hlsl_ir_constant *c;
|
|
|
|
|
|
|
|
if (!(c = hlsl_new_uint_constant(ctx, field->reg_offset * 4, instr->loc)))
|
|
|
|
return false;
|
|
|
|
list_add_before(&instr->entry, &c->node.entry);
|
|
|
|
|
|
|
|
offset = &c->node;
|
|
|
|
if (rhs_load->src.offset.node)
|
|
|
|
{
|
2021-05-20 22:32:20 -07:00
|
|
|
if (!(add = hlsl_new_binary_expr(ctx, HLSL_IR_BINOP_ADD, rhs_load->src.offset.node, &c->node)))
|
2021-03-17 22:22:21 -07:00
|
|
|
return false;
|
|
|
|
list_add_before(&instr->entry, &add->entry);
|
|
|
|
offset = add;
|
|
|
|
}
|
2021-05-20 22:32:20 -07:00
|
|
|
if (!(field_load = hlsl_new_load(ctx, rhs_load->src.var, offset, field->type, instr->loc)))
|
2021-03-17 22:22:21 -07:00
|
|
|
return false;
|
|
|
|
list_add_before(&instr->entry, &field_load->node.entry);
|
|
|
|
|
|
|
|
offset = &c->node;
|
2021-04-08 21:38:22 -07:00
|
|
|
if (store->lhs.offset.node)
|
2021-03-17 22:22:21 -07:00
|
|
|
{
|
2021-05-20 22:32:20 -07:00
|
|
|
if (!(add = hlsl_new_binary_expr(ctx, HLSL_IR_BINOP_ADD, store->lhs.offset.node, &c->node)))
|
2021-03-17 22:22:21 -07:00
|
|
|
return false;
|
|
|
|
list_add_before(&instr->entry, &add->entry);
|
|
|
|
offset = add;
|
|
|
|
}
|
|
|
|
|
2021-05-20 22:32:20 -07:00
|
|
|
if (!(field_store = hlsl_new_store(ctx, store->lhs.var, offset, &field_load->node, 0, instr->loc)))
|
2021-03-17 22:22:21 -07:00
|
|
|
return false;
|
2021-04-08 21:38:22 -07:00
|
|
|
list_add_before(&instr->entry, &field_store->node.entry);
|
2021-03-17 22:22:21 -07:00
|
|
|
}
|
|
|
|
|
2021-04-08 21:38:22 -07:00
|
|
|
/* Remove the store instruction, so that we can split structs which contain
|
|
|
|
* other structs. Although assignments produce a value, we don't allow
|
|
|
|
* HLSL_IR_STORE to be used as a source. */
|
|
|
|
list_remove(&store->node.entry);
|
|
|
|
hlsl_free_instr(&store->node);
|
2021-03-17 22:22:21 -07:00
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
2021-03-16 14:31:53 -07:00
|
|
|
static bool fold_constants(struct hlsl_ctx *ctx, struct hlsl_ir_node *instr, void *context)
|
|
|
|
{
|
|
|
|
struct hlsl_ir_constant *arg1, *arg2 = NULL, *res;
|
|
|
|
struct hlsl_ir_expr *expr;
|
|
|
|
unsigned int i;
|
|
|
|
|
|
|
|
if (instr->type != HLSL_IR_EXPR)
|
|
|
|
return false;
|
|
|
|
expr = hlsl_ir_expr(instr);
|
|
|
|
|
|
|
|
for (i = 0; i < ARRAY_SIZE(expr->operands); ++i)
|
|
|
|
{
|
|
|
|
if (expr->operands[i].node && expr->operands[i].node->type != HLSL_IR_CONSTANT)
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
arg1 = hlsl_ir_constant(expr->operands[0].node);
|
|
|
|
if (expr->operands[1].node)
|
|
|
|
arg2 = hlsl_ir_constant(expr->operands[1].node);
|
|
|
|
|
2021-05-20 22:32:20 -07:00
|
|
|
if (!(res = hlsl_alloc(ctx, sizeof(*res))))
|
2021-03-16 14:31:53 -07:00
|
|
|
return false;
|
|
|
|
init_node(&res->node, HLSL_IR_CONSTANT, instr->data_type, instr->loc);
|
|
|
|
|
|
|
|
switch (instr->data_type->base_type)
|
|
|
|
{
|
|
|
|
case HLSL_TYPE_UINT:
|
|
|
|
{
|
|
|
|
unsigned int i;
|
|
|
|
|
|
|
|
switch (expr->op)
|
|
|
|
{
|
|
|
|
case HLSL_IR_BINOP_ADD:
|
|
|
|
for (i = 0; i < instr->data_type->dimx; ++i)
|
|
|
|
res->value.u[i] = arg1->value.u[i] + arg2->value.u[i];
|
|
|
|
break;
|
|
|
|
|
|
|
|
case HLSL_IR_BINOP_MUL:
|
|
|
|
for (i = 0; i < instr->data_type->dimx; ++i)
|
|
|
|
res->value.u[i] = arg1->value.u[i] * arg2->value.u[i];
|
|
|
|
break;
|
|
|
|
|
|
|
|
default:
|
|
|
|
FIXME("Fold uint op %#x.\n", expr->op);
|
|
|
|
vkd3d_free(res);
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
default:
|
|
|
|
FIXME("Fold type %#x op %#x.\n", instr->data_type->base_type, expr->op);
|
|
|
|
vkd3d_free(res);
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
2021-03-16 14:31:55 -07:00
|
|
|
list_add_before(&expr->node.entry, &res->node.entry);
|
2021-03-16 14:31:53 -07:00
|
|
|
replace_node(&expr->node, &res->node);
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
2021-03-16 14:31:54 -07:00
|
|
|
static bool dce(struct hlsl_ctx *ctx, struct hlsl_ir_node *instr, void *context)
|
|
|
|
{
|
|
|
|
switch (instr->type)
|
|
|
|
{
|
|
|
|
case HLSL_IR_CONSTANT:
|
|
|
|
case HLSL_IR_EXPR:
|
|
|
|
case HLSL_IR_LOAD:
|
|
|
|
case HLSL_IR_SWIZZLE:
|
|
|
|
if (list_empty(&instr->uses))
|
|
|
|
{
|
|
|
|
list_remove(&instr->entry);
|
|
|
|
hlsl_free_instr(instr);
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
|
2021-04-08 21:38:22 -07:00
|
|
|
case HLSL_IR_STORE:
|
2021-03-17 22:22:22 -07:00
|
|
|
{
|
2021-04-08 21:38:22 -07:00
|
|
|
struct hlsl_ir_store *store = hlsl_ir_store(instr);
|
|
|
|
struct hlsl_ir_var *var = store->lhs.var;
|
2021-03-17 22:22:22 -07:00
|
|
|
|
|
|
|
if (var->last_read < instr->index)
|
|
|
|
{
|
|
|
|
list_remove(&instr->entry);
|
|
|
|
hlsl_free_instr(instr);
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
2021-03-16 14:31:54 -07:00
|
|
|
case HLSL_IR_IF:
|
|
|
|
case HLSL_IR_JUMP:
|
|
|
|
case HLSL_IR_LOOP:
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
2021-03-02 13:34:46 -08:00
|
|
|
/* Allocate a unique, ordered index to each instruction, which will be used for
|
|
|
|
* computing liveness ranges. */
|
|
|
|
static unsigned int index_instructions(struct list *instrs, unsigned int index)
|
|
|
|
{
|
|
|
|
struct hlsl_ir_node *instr;
|
|
|
|
|
|
|
|
LIST_FOR_EACH_ENTRY(instr, instrs, struct hlsl_ir_node, entry)
|
|
|
|
{
|
|
|
|
instr->index = index++;
|
|
|
|
|
|
|
|
if (instr->type == HLSL_IR_IF)
|
|
|
|
{
|
|
|
|
struct hlsl_ir_if *iff = hlsl_ir_if(instr);
|
|
|
|
index = index_instructions(&iff->then_instrs, index);
|
|
|
|
index = index_instructions(&iff->else_instrs, index);
|
|
|
|
}
|
|
|
|
else if (instr->type == HLSL_IR_LOOP)
|
|
|
|
{
|
|
|
|
index = index_instructions(&hlsl_ir_loop(instr)->body, index);
|
|
|
|
hlsl_ir_loop(instr)->next_index = index;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
return index;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void dump_function_decl(struct rb_entry *entry, void *context)
|
|
|
|
{
|
|
|
|
struct hlsl_ir_function_decl *func = RB_ENTRY_VALUE(entry, struct hlsl_ir_function_decl, entry);
|
|
|
|
|
|
|
|
if (func->body)
|
|
|
|
hlsl_dump_function(func);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void dump_function(struct rb_entry *entry, void *context)
|
|
|
|
{
|
|
|
|
struct hlsl_ir_function *func = RB_ENTRY_VALUE(entry, struct hlsl_ir_function, entry);
|
|
|
|
rb_for_each_entry(&func->overloads, dump_function_decl, NULL);
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Compute the earliest and latest liveness for each variable. In the case that
|
|
|
|
* a variable is accessed inside of a loop, we promote its liveness to extend
|
|
|
|
* to at least the range of the entire loop. Note that we don't need to do this
|
|
|
|
* for anonymous nodes, since there's currently no way to use a node which was
|
|
|
|
* calculated in an earlier iteration of the loop. */
|
|
|
|
static void compute_liveness_recurse(struct list *instrs, unsigned int loop_first, unsigned int loop_last)
|
|
|
|
{
|
|
|
|
struct hlsl_ir_node *instr;
|
|
|
|
struct hlsl_ir_var *var;
|
|
|
|
|
|
|
|
LIST_FOR_EACH_ENTRY(instr, instrs, struct hlsl_ir_node, entry)
|
|
|
|
{
|
|
|
|
switch (instr->type)
|
|
|
|
{
|
2021-04-08 21:38:22 -07:00
|
|
|
case HLSL_IR_STORE:
|
2021-03-02 13:34:46 -08:00
|
|
|
{
|
2021-04-08 21:38:22 -07:00
|
|
|
struct hlsl_ir_store *store = hlsl_ir_store(instr);
|
2021-03-02 13:34:46 -08:00
|
|
|
|
2021-04-08 21:38:22 -07:00
|
|
|
var = store->lhs.var;
|
2021-03-02 13:34:46 -08:00
|
|
|
if (!var->first_write)
|
|
|
|
var->first_write = loop_first ? min(instr->index, loop_first) : instr->index;
|
2021-04-08 21:38:22 -07:00
|
|
|
store->rhs.node->last_read = instr->index;
|
|
|
|
if (store->lhs.offset.node)
|
|
|
|
store->lhs.offset.node->last_read = instr->index;
|
2021-03-02 13:34:46 -08:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
case HLSL_IR_EXPR:
|
|
|
|
{
|
|
|
|
struct hlsl_ir_expr *expr = hlsl_ir_expr(instr);
|
|
|
|
unsigned int i;
|
|
|
|
|
|
|
|
for (i = 0; i < ARRAY_SIZE(expr->operands) && expr->operands[i].node; ++i)
|
|
|
|
expr->operands[i].node->last_read = instr->index;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
case HLSL_IR_IF:
|
|
|
|
{
|
|
|
|
struct hlsl_ir_if *iff = hlsl_ir_if(instr);
|
|
|
|
|
|
|
|
compute_liveness_recurse(&iff->then_instrs, loop_first, loop_last);
|
|
|
|
compute_liveness_recurse(&iff->else_instrs, loop_first, loop_last);
|
|
|
|
iff->condition.node->last_read = instr->index;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
case HLSL_IR_LOAD:
|
|
|
|
{
|
|
|
|
struct hlsl_ir_load *load = hlsl_ir_load(instr);
|
|
|
|
|
|
|
|
var = load->src.var;
|
2021-03-21 13:40:07 -07:00
|
|
|
var->last_read = max(var->last_read, loop_last ? max(instr->index, loop_last) : instr->index);
|
2021-03-02 13:34:46 -08:00
|
|
|
if (load->src.offset.node)
|
|
|
|
load->src.offset.node->last_read = instr->index;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
case HLSL_IR_LOOP:
|
|
|
|
{
|
|
|
|
struct hlsl_ir_loop *loop = hlsl_ir_loop(instr);
|
|
|
|
|
|
|
|
compute_liveness_recurse(&loop->body, loop_first ? loop_first : instr->index,
|
|
|
|
loop_last ? loop_last : loop->next_index);
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
case HLSL_IR_SWIZZLE:
|
|
|
|
{
|
|
|
|
struct hlsl_ir_swizzle *swizzle = hlsl_ir_swizzle(instr);
|
|
|
|
|
|
|
|
swizzle->val.node->last_read = instr->index;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
case HLSL_IR_CONSTANT:
|
|
|
|
case HLSL_IR_JUMP:
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static void compute_liveness(struct hlsl_ctx *ctx, struct hlsl_ir_function_decl *entry_func)
|
|
|
|
{
|
2021-03-17 22:22:22 -07:00
|
|
|
struct hlsl_scope *scope;
|
2021-03-02 13:34:46 -08:00
|
|
|
struct hlsl_ir_var *var;
|
|
|
|
|
2021-03-17 22:22:22 -07:00
|
|
|
/* Index 0 means unused; index 1 means function entry, so start at 2. */
|
|
|
|
index_instructions(entry_func->body, 2);
|
|
|
|
|
|
|
|
LIST_FOR_EACH_ENTRY(scope, &ctx->scopes, struct hlsl_scope, entry)
|
|
|
|
{
|
|
|
|
LIST_FOR_EACH_ENTRY(var, &scope->vars, struct hlsl_ir_var, scope_entry)
|
|
|
|
var->first_write = var->last_read = 0;
|
|
|
|
}
|
|
|
|
|
2021-04-15 17:03:44 -07:00
|
|
|
LIST_FOR_EACH_ENTRY(var, &ctx->extern_vars, struct hlsl_ir_var, extern_entry)
|
2021-03-02 13:34:46 -08:00
|
|
|
{
|
2021-04-27 10:14:20 -07:00
|
|
|
if (var->is_uniform || var->is_input_semantic)
|
2021-03-22 15:02:40 -07:00
|
|
|
var->first_write = 1;
|
2021-04-27 10:14:20 -07:00
|
|
|
else if (var->is_output_semantic)
|
2021-03-28 12:46:59 -07:00
|
|
|
var->last_read = UINT_MAX;
|
2021-03-02 13:34:46 -08:00
|
|
|
}
|
|
|
|
|
|
|
|
if (entry_func->return_var)
|
|
|
|
entry_func->return_var->last_read = UINT_MAX;
|
|
|
|
|
|
|
|
compute_liveness_recurse(entry_func->body, 0, 0);
|
|
|
|
}
|
|
|
|
|
2021-04-08 21:38:23 -07:00
|
|
|
struct liveness
|
|
|
|
{
|
|
|
|
size_t size;
|
|
|
|
struct
|
|
|
|
{
|
|
|
|
/* 0 if not live yet. */
|
|
|
|
unsigned int last_read;
|
|
|
|
} *regs;
|
|
|
|
};
|
|
|
|
|
|
|
|
static unsigned int get_available_writemask(struct liveness *liveness,
|
|
|
|
unsigned int first_write, unsigned int component_idx, unsigned int component_count)
|
|
|
|
{
|
|
|
|
unsigned int i, writemask = 0, count = 0;
|
|
|
|
|
|
|
|
for (i = 0; i < 4; ++i)
|
|
|
|
{
|
|
|
|
if (liveness->regs[component_idx + i].last_read <= first_write)
|
|
|
|
{
|
|
|
|
writemask |= 1u << i;
|
|
|
|
if (++count == component_count)
|
|
|
|
return writemask;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2021-05-20 22:32:20 -07:00
|
|
|
static bool resize_liveness(struct hlsl_ctx *ctx, struct liveness *liveness, size_t new_count)
|
2021-04-08 21:38:23 -07:00
|
|
|
{
|
|
|
|
size_t old_capacity = liveness->size;
|
|
|
|
|
2021-05-20 22:32:20 -07:00
|
|
|
if (!hlsl_array_reserve(ctx, (void **)&liveness->regs, &liveness->size, new_count, sizeof(*liveness->regs)))
|
2021-04-08 21:38:23 -07:00
|
|
|
return false;
|
|
|
|
|
|
|
|
if (liveness->size > old_capacity)
|
|
|
|
memset(liveness->regs + old_capacity, 0, (liveness->size - old_capacity) * sizeof(*liveness->regs));
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
2021-05-20 22:32:20 -07:00
|
|
|
static struct hlsl_reg allocate_register(struct hlsl_ctx *ctx, struct liveness *liveness,
|
2021-04-08 21:38:23 -07:00
|
|
|
unsigned int first_write, unsigned int last_read, unsigned int component_count)
|
|
|
|
{
|
|
|
|
unsigned int component_idx, writemask, i;
|
|
|
|
struct hlsl_reg ret = {0};
|
|
|
|
|
|
|
|
for (component_idx = 0; component_idx < liveness->size; component_idx += 4)
|
|
|
|
{
|
|
|
|
if ((writemask = get_available_writemask(liveness, first_write, component_idx, component_count)))
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
if (component_idx == liveness->size)
|
|
|
|
{
|
2021-05-20 22:32:20 -07:00
|
|
|
if (!resize_liveness(ctx, liveness, component_idx + 4))
|
2021-04-08 21:38:23 -07:00
|
|
|
return ret;
|
|
|
|
writemask = (1u << component_count) - 1;
|
|
|
|
}
|
|
|
|
for (i = 0; i < 4; ++i)
|
|
|
|
{
|
|
|
|
if (writemask & (1u << i))
|
|
|
|
liveness->regs[component_idx + i].last_read = last_read;
|
|
|
|
}
|
|
|
|
ret.id = component_idx / 4;
|
|
|
|
ret.writemask = writemask;
|
|
|
|
ret.allocated = true;
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
static bool is_range_available(struct liveness *liveness, unsigned int first_write,
|
|
|
|
unsigned int component_idx, unsigned int component_count)
|
|
|
|
{
|
|
|
|
unsigned int i;
|
|
|
|
|
|
|
|
for (i = 0; i < component_count; i += 4)
|
|
|
|
{
|
|
|
|
if (!get_available_writemask(liveness, first_write, component_idx + i, 4))
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
2021-05-20 22:32:20 -07:00
|
|
|
static struct hlsl_reg allocate_range(struct hlsl_ctx *ctx, struct liveness *liveness,
|
2021-04-08 21:38:23 -07:00
|
|
|
unsigned int first_write, unsigned int last_read, unsigned int reg_count)
|
|
|
|
{
|
|
|
|
const unsigned int component_count = reg_count * 4;
|
|
|
|
unsigned int i, component_idx;
|
|
|
|
struct hlsl_reg ret = {0};
|
|
|
|
|
|
|
|
for (component_idx = 0; component_idx < liveness->size; component_idx += 4)
|
|
|
|
{
|
|
|
|
if (is_range_available(liveness, first_write, component_idx,
|
|
|
|
min(component_count, liveness->size - component_idx)))
|
|
|
|
break;
|
|
|
|
}
|
2021-05-20 22:32:20 -07:00
|
|
|
if (!resize_liveness(ctx, liveness, component_idx + component_count))
|
2021-04-08 21:38:23 -07:00
|
|
|
return ret;
|
|
|
|
|
|
|
|
for (i = 0; i < component_count; ++i)
|
|
|
|
liveness->regs[component_idx + i].last_read = last_read;
|
|
|
|
ret.id = component_idx / 4;
|
|
|
|
ret.allocated = true;
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
static const char *debug_register(char class, struct hlsl_reg reg, const struct hlsl_type *type)
|
|
|
|
{
|
2021-04-15 17:03:42 -07:00
|
|
|
if (type->reg_size > 1)
|
2021-04-08 21:38:23 -07:00
|
|
|
return vkd3d_dbg_sprintf("%c%u-%c%u", class, reg.id, class,
|
|
|
|
reg.id + type->reg_size - 1);
|
|
|
|
return vkd3d_dbg_sprintf("%c%u%s", class, reg.id, debug_hlsl_writemask(reg.writemask));
|
|
|
|
}
|
|
|
|
|
2021-05-20 22:32:20 -07:00
|
|
|
static void allocate_variable_temp_register(struct hlsl_ctx *ctx, struct hlsl_ir_var *var, struct liveness *liveness)
|
2021-04-08 21:38:23 -07:00
|
|
|
{
|
2021-04-27 10:14:20 -07:00
|
|
|
if (var->is_input_semantic || var->is_output_semantic || var->is_uniform)
|
2021-04-08 21:38:23 -07:00
|
|
|
return;
|
|
|
|
|
|
|
|
if (!var->reg.allocated && var->last_read)
|
|
|
|
{
|
|
|
|
if (var->data_type->reg_size > 1)
|
2021-05-20 22:32:20 -07:00
|
|
|
var->reg = allocate_range(ctx, liveness, var->first_write,
|
2021-04-08 21:38:23 -07:00
|
|
|
var->last_read, var->data_type->reg_size);
|
|
|
|
else
|
2021-05-20 22:32:20 -07:00
|
|
|
var->reg = allocate_register(ctx, liveness, var->first_write,
|
2021-04-08 21:38:23 -07:00
|
|
|
var->last_read, var->data_type->dimx);
|
|
|
|
TRACE("Allocated %s to %s (liveness %u-%u).\n", var->name,
|
|
|
|
debug_register('r', var->reg, var->data_type), var->first_write, var->last_read);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2021-05-20 22:32:20 -07:00
|
|
|
static void allocate_temp_registers_recurse(struct hlsl_ctx *ctx, struct list *instrs, struct liveness *liveness)
|
2021-04-08 21:38:23 -07:00
|
|
|
{
|
|
|
|
struct hlsl_ir_node *instr;
|
|
|
|
|
|
|
|
LIST_FOR_EACH_ENTRY(instr, instrs, struct hlsl_ir_node, entry)
|
|
|
|
{
|
2021-04-08 21:38:24 -07:00
|
|
|
if (!instr->reg.allocated && instr->last_read)
|
|
|
|
{
|
|
|
|
if (instr->data_type->reg_size > 1)
|
2021-05-20 22:32:20 -07:00
|
|
|
instr->reg = allocate_range(ctx, liveness, instr->index,
|
2021-04-08 21:38:24 -07:00
|
|
|
instr->last_read, instr->data_type->reg_size);
|
|
|
|
else
|
2021-05-20 22:32:20 -07:00
|
|
|
instr->reg = allocate_register(ctx, liveness, instr->index,
|
2021-04-08 21:38:24 -07:00
|
|
|
instr->last_read, instr->data_type->dimx);
|
|
|
|
TRACE("Allocated anonymous expression @%u to %s (liveness %u-%u).\n", instr->index,
|
|
|
|
debug_register('r', instr->reg, instr->data_type), instr->index, instr->last_read);
|
|
|
|
}
|
|
|
|
|
2021-04-08 21:38:23 -07:00
|
|
|
switch (instr->type)
|
|
|
|
{
|
|
|
|
case HLSL_IR_IF:
|
|
|
|
{
|
|
|
|
struct hlsl_ir_if *iff = hlsl_ir_if(instr);
|
2021-05-20 22:32:20 -07:00
|
|
|
allocate_temp_registers_recurse(ctx, &iff->then_instrs, liveness);
|
|
|
|
allocate_temp_registers_recurse(ctx, &iff->else_instrs, liveness);
|
2021-04-08 21:38:23 -07:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
case HLSL_IR_LOAD:
|
|
|
|
{
|
|
|
|
struct hlsl_ir_load *load = hlsl_ir_load(instr);
|
|
|
|
/* We need to at least allocate a variable for undefs.
|
|
|
|
* FIXME: We should probably find a way to remove them instead. */
|
2021-05-20 22:32:20 -07:00
|
|
|
allocate_variable_temp_register(ctx, load->src.var, liveness);
|
2021-04-08 21:38:23 -07:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
case HLSL_IR_LOOP:
|
|
|
|
{
|
|
|
|
struct hlsl_ir_loop *loop = hlsl_ir_loop(instr);
|
2021-05-20 22:32:20 -07:00
|
|
|
allocate_temp_registers_recurse(ctx, &loop->body, liveness);
|
2021-04-08 21:38:23 -07:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
case HLSL_IR_STORE:
|
|
|
|
{
|
|
|
|
struct hlsl_ir_store *store = hlsl_ir_store(instr);
|
2021-05-20 22:32:20 -07:00
|
|
|
allocate_variable_temp_register(ctx, store->lhs.var, liveness);
|
2021-04-08 21:38:23 -07:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
default:
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2021-04-27 10:14:17 -07:00
|
|
|
static void allocate_const_registers_recurse(struct hlsl_ctx *ctx, struct list *instrs, struct liveness *liveness)
|
2021-04-08 21:38:26 -07:00
|
|
|
{
|
2021-04-27 10:14:17 -07:00
|
|
|
struct hlsl_constant_defs *defs = &ctx->constant_defs;
|
2021-04-08 21:38:26 -07:00
|
|
|
struct hlsl_ir_node *instr;
|
|
|
|
|
|
|
|
LIST_FOR_EACH_ENTRY(instr, instrs, struct hlsl_ir_node, entry)
|
|
|
|
{
|
|
|
|
switch (instr->type)
|
|
|
|
{
|
|
|
|
case HLSL_IR_CONSTANT:
|
|
|
|
{
|
|
|
|
struct hlsl_ir_constant *constant = hlsl_ir_constant(instr);
|
2021-04-27 10:14:17 -07:00
|
|
|
const struct hlsl_type *type = instr->data_type;
|
|
|
|
unsigned int reg_size = type->reg_size;
|
|
|
|
unsigned int x, y, i, writemask;
|
2021-04-08 21:38:26 -07:00
|
|
|
|
2021-04-27 10:14:17 -07:00
|
|
|
if (reg_size > 1)
|
2021-05-20 22:32:20 -07:00
|
|
|
constant->reg = allocate_range(ctx, liveness, 1, UINT_MAX, reg_size);
|
2021-04-08 21:38:26 -07:00
|
|
|
else
|
2021-05-20 22:32:20 -07:00
|
|
|
constant->reg = allocate_register(ctx, liveness, 1, UINT_MAX, type->dimx);
|
2021-04-27 10:14:17 -07:00
|
|
|
TRACE("Allocated constant @%u to %s.\n", instr->index, debug_register('c', constant->reg, type));
|
|
|
|
|
2021-05-20 22:32:20 -07:00
|
|
|
if (!hlsl_array_reserve(ctx, (void **)&defs->values, &defs->size,
|
2021-04-27 10:14:17 -07:00
|
|
|
constant->reg.id + reg_size, sizeof(*defs->values)))
|
|
|
|
return;
|
|
|
|
defs->count = max(defs->count, constant->reg.id + reg_size);
|
|
|
|
|
|
|
|
assert(type->type <= HLSL_CLASS_LAST_NUMERIC);
|
|
|
|
|
|
|
|
if (!(writemask = constant->reg.writemask))
|
|
|
|
writemask = (1u << type->dimx) - 1;
|
|
|
|
|
|
|
|
for (y = 0; y < type->dimy; ++y)
|
|
|
|
{
|
|
|
|
for (x = 0, i = 0; x < 4; ++x)
|
|
|
|
{
|
|
|
|
float f;
|
|
|
|
|
|
|
|
if (!(writemask & (1u << x)))
|
|
|
|
continue;
|
|
|
|
|
|
|
|
switch (type->base_type)
|
|
|
|
{
|
|
|
|
case HLSL_TYPE_BOOL:
|
|
|
|
f = constant->value.b[i++];
|
|
|
|
break;
|
|
|
|
|
|
|
|
case HLSL_TYPE_FLOAT:
|
|
|
|
case HLSL_TYPE_HALF:
|
|
|
|
f = constant->value.f[i++];
|
|
|
|
break;
|
|
|
|
|
|
|
|
case HLSL_TYPE_INT:
|
|
|
|
f = constant->value.i[i++];
|
|
|
|
break;
|
|
|
|
|
|
|
|
case HLSL_TYPE_UINT:
|
|
|
|
f = constant->value.u[i++];
|
|
|
|
break;
|
|
|
|
|
|
|
|
case HLSL_TYPE_DOUBLE:
|
|
|
|
FIXME("Double constant.\n");
|
|
|
|
return;
|
|
|
|
|
|
|
|
default:
|
|
|
|
assert(0);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
defs->values[constant->reg.id + y].f[x] = f;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2021-04-08 21:38:26 -07:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
case HLSL_IR_IF:
|
|
|
|
{
|
|
|
|
struct hlsl_ir_if *iff = hlsl_ir_if(instr);
|
2021-04-27 10:14:17 -07:00
|
|
|
allocate_const_registers_recurse(ctx, &iff->then_instrs, liveness);
|
|
|
|
allocate_const_registers_recurse(ctx, &iff->else_instrs, liveness);
|
2021-04-08 21:38:26 -07:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
case HLSL_IR_LOOP:
|
|
|
|
{
|
|
|
|
struct hlsl_ir_loop *loop = hlsl_ir_loop(instr);
|
2021-04-27 10:14:17 -07:00
|
|
|
allocate_const_registers_recurse(ctx, &loop->body, liveness);
|
2021-04-08 21:38:26 -07:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
default:
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2021-04-08 21:38:27 -07:00
|
|
|
static void allocate_const_registers(struct hlsl_ctx *ctx, struct hlsl_ir_function_decl *entry_func)
|
2021-04-08 21:38:26 -07:00
|
|
|
{
|
|
|
|
struct liveness liveness = {0};
|
2021-04-08 21:38:27 -07:00
|
|
|
struct hlsl_ir_var *var;
|
|
|
|
|
2021-04-27 10:14:17 -07:00
|
|
|
allocate_const_registers_recurse(ctx, entry_func->body, &liveness);
|
|
|
|
|
2021-04-15 17:03:44 -07:00
|
|
|
LIST_FOR_EACH_ENTRY(var, &ctx->extern_vars, struct hlsl_ir_var, extern_entry)
|
2021-04-08 21:38:27 -07:00
|
|
|
{
|
|
|
|
if (var->is_uniform && var->last_read)
|
|
|
|
{
|
|
|
|
if (var->data_type->reg_size > 1)
|
2021-05-20 22:32:20 -07:00
|
|
|
var->reg = allocate_range(ctx, &liveness, 1, UINT_MAX, var->data_type->reg_size);
|
2021-04-08 21:38:27 -07:00
|
|
|
else
|
|
|
|
{
|
2021-05-20 22:32:20 -07:00
|
|
|
var->reg = allocate_register(ctx, &liveness, 1, UINT_MAX, 4);
|
2021-04-08 21:38:27 -07:00
|
|
|
var->reg.writemask = (1u << var->data_type->dimx) - 1;
|
|
|
|
}
|
|
|
|
TRACE("Allocated %s to %s.\n", var->name, debug_register('c', var->reg, var->data_type));
|
|
|
|
}
|
|
|
|
}
|
2021-04-08 21:38:26 -07:00
|
|
|
}
|
|
|
|
|
2021-04-08 21:38:23 -07:00
|
|
|
/* Simple greedy temporary register allocation pass that just assigns a unique
|
|
|
|
* index to all (simultaneously live) variables or intermediate values. Agnostic
|
|
|
|
* as to how many registers are actually available for the current backend, and
|
|
|
|
* does not handle constants. */
|
2021-05-20 22:32:20 -07:00
|
|
|
static void allocate_temp_registers(struct hlsl_ctx *ctx, struct hlsl_ir_function_decl *entry_func)
|
2021-04-08 21:38:23 -07:00
|
|
|
{
|
|
|
|
struct liveness liveness = {0};
|
2021-05-20 22:32:20 -07:00
|
|
|
allocate_temp_registers_recurse(ctx, entry_func->body, &liveness);
|
2021-04-08 21:38:23 -07:00
|
|
|
}
|
|
|
|
|
2021-04-27 10:14:21 -07:00
|
|
|
static bool sm1_register_from_semantic(struct hlsl_ctx *ctx, const struct hlsl_semantic *semantic, bool output,
|
|
|
|
D3DSHADER_PARAM_REGISTER_TYPE *type, unsigned int *reg)
|
|
|
|
{
|
|
|
|
unsigned int i;
|
|
|
|
|
|
|
|
static const struct
|
|
|
|
{
|
|
|
|
const char *semantic;
|
|
|
|
bool output;
|
|
|
|
enum vkd3d_shader_type shader_type;
|
|
|
|
unsigned int major_version;
|
|
|
|
D3DSHADER_PARAM_REGISTER_TYPE type;
|
|
|
|
DWORD offset;
|
|
|
|
}
|
|
|
|
register_table[] =
|
|
|
|
{
|
|
|
|
{"color", true, VKD3D_SHADER_TYPE_PIXEL, 2, D3DSPR_COLOROUT},
|
|
|
|
{"depth", true, VKD3D_SHADER_TYPE_PIXEL, 2, D3DSPR_DEPTHOUT},
|
|
|
|
{"sv_depth", true, VKD3D_SHADER_TYPE_PIXEL, 2, D3DSPR_DEPTHOUT},
|
|
|
|
{"sv_target", true, VKD3D_SHADER_TYPE_PIXEL, 2, D3DSPR_COLOROUT},
|
|
|
|
{"color", false, VKD3D_SHADER_TYPE_PIXEL, 2, D3DSPR_INPUT},
|
|
|
|
{"texcoord", false, VKD3D_SHADER_TYPE_PIXEL, 2, D3DSPR_TEXTURE},
|
|
|
|
|
|
|
|
{"color", true, VKD3D_SHADER_TYPE_PIXEL, 3, D3DSPR_COLOROUT},
|
|
|
|
{"depth", true, VKD3D_SHADER_TYPE_PIXEL, 3, D3DSPR_DEPTHOUT},
|
|
|
|
{"sv_depth", true, VKD3D_SHADER_TYPE_PIXEL, 3, D3DSPR_DEPTHOUT},
|
|
|
|
{"sv_target", true, VKD3D_SHADER_TYPE_PIXEL, 3, D3DSPR_COLOROUT},
|
|
|
|
{"sv_position", false, VKD3D_SHADER_TYPE_PIXEL, 3, D3DSPR_MISCTYPE, D3DSMO_POSITION},
|
|
|
|
{"vface", false, VKD3D_SHADER_TYPE_PIXEL, 3, D3DSPR_MISCTYPE, D3DSMO_FACE},
|
|
|
|
{"vpos", false, VKD3D_SHADER_TYPE_PIXEL, 3, D3DSPR_MISCTYPE, D3DSMO_POSITION},
|
|
|
|
|
|
|
|
{"color", true, VKD3D_SHADER_TYPE_VERTEX, 1, D3DSPR_ATTROUT},
|
|
|
|
{"fog", true, VKD3D_SHADER_TYPE_VERTEX, 1, D3DSPR_RASTOUT, D3DSRO_FOG},
|
|
|
|
{"position", true, VKD3D_SHADER_TYPE_VERTEX, 1, D3DSPR_RASTOUT, D3DSRO_POSITION},
|
|
|
|
{"psize", true, VKD3D_SHADER_TYPE_VERTEX, 1, D3DSPR_RASTOUT, D3DSRO_POINT_SIZE},
|
|
|
|
{"sv_position", true, VKD3D_SHADER_TYPE_VERTEX, 1, D3DSPR_RASTOUT, D3DSRO_POSITION},
|
|
|
|
{"texcoord", true, VKD3D_SHADER_TYPE_VERTEX, 1, D3DSPR_TEXCRDOUT},
|
|
|
|
|
|
|
|
{"color", true, VKD3D_SHADER_TYPE_VERTEX, 2, D3DSPR_ATTROUT},
|
|
|
|
{"fog", true, VKD3D_SHADER_TYPE_VERTEX, 2, D3DSPR_RASTOUT, D3DSRO_FOG},
|
|
|
|
{"position", true, VKD3D_SHADER_TYPE_VERTEX, 2, D3DSPR_RASTOUT, D3DSRO_POSITION},
|
|
|
|
{"psize", true, VKD3D_SHADER_TYPE_VERTEX, 2, D3DSPR_RASTOUT, D3DSRO_POINT_SIZE},
|
|
|
|
{"sv_position", true, VKD3D_SHADER_TYPE_VERTEX, 2, D3DSPR_RASTOUT, D3DSRO_POSITION},
|
|
|
|
{"texcoord", true, VKD3D_SHADER_TYPE_VERTEX, 2, D3DSPR_TEXCRDOUT},
|
|
|
|
};
|
|
|
|
|
|
|
|
for (i = 0; i < ARRAY_SIZE(register_table); ++i)
|
|
|
|
{
|
|
|
|
if (!ascii_strcasecmp(semantic->name, register_table[i].semantic)
|
|
|
|
&& output == register_table[i].output
|
|
|
|
&& ctx->profile->type == register_table[i].shader_type
|
|
|
|
&& ctx->profile->major_version == register_table[i].major_version)
|
|
|
|
{
|
|
|
|
*type = register_table[i].type;
|
|
|
|
if (register_table[i].type == D3DSPR_MISCTYPE || register_table[i].type == D3DSPR_RASTOUT)
|
|
|
|
*reg = register_table[i].offset;
|
|
|
|
else
|
|
|
|
*reg = semantic->index;
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
2021-05-10 21:36:07 -07:00
|
|
|
static bool sm1_usage_from_semantic(const struct hlsl_semantic *semantic, D3DDECLUSAGE *usage, uint32_t *usage_idx)
|
|
|
|
{
|
|
|
|
static const struct
|
|
|
|
{
|
|
|
|
const char *name;
|
|
|
|
D3DDECLUSAGE usage;
|
|
|
|
}
|
|
|
|
semantics[] =
|
|
|
|
{
|
|
|
|
{"binormal", D3DDECLUSAGE_BINORMAL},
|
|
|
|
{"blendindices", D3DDECLUSAGE_BLENDINDICES},
|
|
|
|
{"blendweight", D3DDECLUSAGE_BLENDWEIGHT},
|
|
|
|
{"color", D3DDECLUSAGE_COLOR},
|
|
|
|
{"depth", D3DDECLUSAGE_DEPTH},
|
|
|
|
{"fog", D3DDECLUSAGE_FOG},
|
|
|
|
{"normal", D3DDECLUSAGE_NORMAL},
|
|
|
|
{"position", D3DDECLUSAGE_POSITION},
|
|
|
|
{"positiont", D3DDECLUSAGE_POSITIONT},
|
|
|
|
{"psize", D3DDECLUSAGE_PSIZE},
|
|
|
|
{"sample", D3DDECLUSAGE_SAMPLE},
|
|
|
|
{"sv_depth", D3DDECLUSAGE_DEPTH},
|
|
|
|
{"sv_position", D3DDECLUSAGE_POSITION},
|
|
|
|
{"sv_target", D3DDECLUSAGE_COLOR},
|
|
|
|
{"tangent", D3DDECLUSAGE_TANGENT},
|
|
|
|
{"tessfactor", D3DDECLUSAGE_TESSFACTOR},
|
|
|
|
{"texcoord", D3DDECLUSAGE_TEXCOORD},
|
|
|
|
};
|
|
|
|
|
|
|
|
unsigned int i;
|
|
|
|
|
|
|
|
for (i = 0; i < ARRAY_SIZE(semantics); ++i)
|
|
|
|
{
|
|
|
|
if (!ascii_strcasecmp(semantic->name, semantics[i].name))
|
|
|
|
{
|
|
|
|
*usage = semantics[i].usage;
|
|
|
|
*usage_idx = semantic->index;
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
2021-04-27 10:14:21 -07:00
|
|
|
static void allocate_semantic_register(struct hlsl_ctx *ctx, struct hlsl_ir_var *var, unsigned int *counter, bool output)
|
|
|
|
{
|
|
|
|
assert(var->semantic.name);
|
|
|
|
|
|
|
|
if (ctx->profile->major_version < 4)
|
|
|
|
{
|
|
|
|
D3DSHADER_PARAM_REGISTER_TYPE type;
|
2021-05-10 21:36:07 -07:00
|
|
|
uint32_t reg, usage_idx;
|
|
|
|
D3DDECLUSAGE usage;
|
|
|
|
|
|
|
|
if (!sm1_usage_from_semantic(&var->semantic, &usage, &usage_idx))
|
|
|
|
{
|
|
|
|
hlsl_error(ctx, var->loc, VKD3D_SHADER_ERROR_HLSL_INVALID_SEMANTIC,
|
|
|
|
"Invalid semantic '%s'.", var->semantic.name);
|
|
|
|
return;
|
|
|
|
}
|
2021-04-27 10:14:21 -07:00
|
|
|
|
2021-05-16 10:47:51 -07:00
|
|
|
if (sm1_register_from_semantic(ctx, &var->semantic, output, &type, ®))
|
|
|
|
{
|
|
|
|
TRACE("%s %s semantic %s[%u] matches predefined register %#x[%u].\n",
|
|
|
|
ctx->profile->type == VKD3D_SHADER_TYPE_PIXEL ? "Pixel" : "Vertex", output ? "output" : "input",
|
|
|
|
var->semantic.name, var->semantic.index, type, reg);
|
|
|
|
}
|
|
|
|
else
|
2021-04-27 10:14:21 -07:00
|
|
|
{
|
|
|
|
var->reg.allocated = true;
|
|
|
|
var->reg.id = (*counter)++;
|
|
|
|
var->reg.writemask = (1 << var->data_type->dimx) - 1;
|
|
|
|
TRACE("Allocated %s to %s.\n", var->name, debug_register(output ? 'o' : 'v', var->reg, var->data_type));
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static void allocate_semantic_registers(struct hlsl_ctx *ctx)
|
|
|
|
{
|
|
|
|
unsigned int input_counter = 0, output_counter = 0;
|
|
|
|
struct hlsl_ir_var *var;
|
|
|
|
|
|
|
|
LIST_FOR_EACH_ENTRY(var, &ctx->extern_vars, struct hlsl_ir_var, extern_entry)
|
|
|
|
{
|
|
|
|
if (var->is_input_semantic && var->last_read)
|
|
|
|
allocate_semantic_register(ctx, var, &input_counter, false);
|
|
|
|
if (var->is_output_semantic && var->first_write)
|
|
|
|
allocate_semantic_register(ctx, var, &output_counter, true);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2021-05-10 21:36:08 -07:00
|
|
|
static unsigned int map_swizzle(unsigned int swizzle, unsigned int writemask)
|
|
|
|
{
|
|
|
|
unsigned int i, ret = 0;
|
|
|
|
|
|
|
|
for (i = 0; i < 4; ++i)
|
|
|
|
{
|
|
|
|
if (writemask & (1 << i))
|
|
|
|
{
|
|
|
|
ret |= (swizzle & 3) << (i * 2);
|
|
|
|
swizzle >>= 2;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
static unsigned int swizzle_from_writemask(unsigned int writemask)
|
|
|
|
{
|
|
|
|
static const unsigned int swizzles[16] =
|
|
|
|
{
|
|
|
|
0,
|
|
|
|
HLSL_SWIZZLE(X, X, X, X),
|
|
|
|
HLSL_SWIZZLE(Y, Y, Y, Y),
|
|
|
|
HLSL_SWIZZLE(X, Y, X, X),
|
|
|
|
HLSL_SWIZZLE(Z, Z, Z, Z),
|
|
|
|
HLSL_SWIZZLE(X, Z, X, X),
|
|
|
|
HLSL_SWIZZLE(Y, Z, X, X),
|
|
|
|
HLSL_SWIZZLE(X, Y, Z, X),
|
|
|
|
HLSL_SWIZZLE(W, W, W, W),
|
|
|
|
HLSL_SWIZZLE(X, W, X, X),
|
|
|
|
HLSL_SWIZZLE(Y, W, X, X),
|
|
|
|
HLSL_SWIZZLE(X, Y, W, X),
|
|
|
|
HLSL_SWIZZLE(Z, W, X, X),
|
|
|
|
HLSL_SWIZZLE(X, Z, W, X),
|
|
|
|
HLSL_SWIZZLE(Y, Z, W, X),
|
|
|
|
HLSL_SWIZZLE(X, Y, Z, W),
|
|
|
|
};
|
|
|
|
|
|
|
|
return swizzles[writemask & 0xf];
|
|
|
|
}
|
|
|
|
|
|
|
|
static unsigned int combine_writemasks(unsigned int first, unsigned int second)
|
|
|
|
{
|
|
|
|
unsigned int ret = 0, i, j = 0;
|
|
|
|
|
|
|
|
for (i = 0; i < 4; ++i)
|
|
|
|
{
|
|
|
|
if (first & (1 << i))
|
|
|
|
{
|
|
|
|
if (second & (1 << j++))
|
|
|
|
ret |= (1 << i);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2021-05-18 13:55:22 -07:00
|
|
|
static unsigned int combine_swizzles(unsigned int first, unsigned int second, unsigned int dim)
|
|
|
|
{
|
|
|
|
unsigned int ret = 0, i;
|
|
|
|
for (i = 0; i < dim; ++i)
|
|
|
|
{
|
|
|
|
unsigned int s = (second >> (i * 2)) & 3;
|
|
|
|
ret |= ((first >> (s * 2)) & 3) << (i * 2);
|
|
|
|
}
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2021-05-10 21:36:08 -07:00
|
|
|
static bool type_is_single_reg(const struct hlsl_type *type)
|
|
|
|
{
|
|
|
|
return type->type == HLSL_CLASS_SCALAR || type->type == HLSL_CLASS_VECTOR;
|
|
|
|
}
|
|
|
|
|
|
|
|
static struct hlsl_reg hlsl_reg_from_deref(const struct hlsl_deref *deref, const struct hlsl_type *type)
|
|
|
|
{
|
|
|
|
struct hlsl_ir_node *offset_node = deref->offset.node;
|
|
|
|
const struct hlsl_ir_var *var = deref->var;
|
|
|
|
struct hlsl_reg ret = {0};
|
|
|
|
unsigned int offset = 0;
|
|
|
|
|
2021-05-16 10:47:53 -07:00
|
|
|
/* We should always have generated a cast to UINT. */
|
|
|
|
if (offset_node)
|
|
|
|
assert(offset_node->data_type->type == HLSL_CLASS_SCALAR
|
|
|
|
&& offset_node->data_type->base_type == HLSL_TYPE_UINT);
|
|
|
|
|
2021-05-10 21:36:08 -07:00
|
|
|
if (offset_node && offset_node->type != HLSL_IR_CONSTANT)
|
|
|
|
{
|
|
|
|
FIXME("Dereference with non-constant offset of type %s.\n", hlsl_node_type_to_string(offset_node->type));
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
ret = var->reg;
|
|
|
|
|
|
|
|
ret.allocated = var->reg.allocated;
|
|
|
|
ret.id = var->reg.id;
|
|
|
|
if (offset_node)
|
|
|
|
offset = hlsl_ir_constant(offset_node)->value.u[0];
|
|
|
|
ret.id += offset / 4;
|
|
|
|
|
|
|
|
if (type_is_single_reg(var->data_type))
|
|
|
|
{
|
|
|
|
assert(!offset);
|
|
|
|
ret.writemask = var->reg.writemask;
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
assert(type_is_single_reg(type));
|
|
|
|
ret.writemask = ((1 << type->dimx) - 1) << (offset & 3);
|
|
|
|
}
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2021-04-15 17:03:43 -07:00
|
|
|
struct bytecode_buffer
|
|
|
|
{
|
2021-05-20 22:32:20 -07:00
|
|
|
struct hlsl_ctx *ctx;
|
2021-04-15 17:03:43 -07:00
|
|
|
uint32_t *data;
|
|
|
|
size_t count, size;
|
|
|
|
int status;
|
|
|
|
};
|
|
|
|
|
2021-04-27 10:14:16 -07:00
|
|
|
/* Returns the token index. */
|
|
|
|
static unsigned int put_dword(struct bytecode_buffer *buffer, uint32_t value)
|
2021-04-15 17:03:43 -07:00
|
|
|
{
|
2021-04-27 10:14:16 -07:00
|
|
|
unsigned int index = buffer->count;
|
|
|
|
|
2021-04-15 17:03:43 -07:00
|
|
|
if (buffer->status)
|
2021-04-27 10:14:16 -07:00
|
|
|
return index;
|
2021-04-15 17:03:43 -07:00
|
|
|
|
2021-05-20 22:32:20 -07:00
|
|
|
if (!hlsl_array_reserve(buffer->ctx, (void **)&buffer->data, &buffer->size,
|
|
|
|
buffer->count + 1, sizeof(*buffer->data)))
|
2021-04-15 17:03:43 -07:00
|
|
|
{
|
|
|
|
buffer->status = VKD3D_ERROR_OUT_OF_MEMORY;
|
2021-04-27 10:14:16 -07:00
|
|
|
return index;
|
2021-04-15 17:03:43 -07:00
|
|
|
}
|
|
|
|
buffer->data[buffer->count++] = value;
|
2021-04-27 10:14:16 -07:00
|
|
|
|
|
|
|
return index;
|
2021-04-15 17:03:43 -07:00
|
|
|
}
|
|
|
|
|
2021-04-27 10:14:17 -07:00
|
|
|
/* Returns the token index. */
|
|
|
|
static unsigned int put_float(struct bytecode_buffer *buffer, float value)
|
|
|
|
{
|
|
|
|
union
|
|
|
|
{
|
|
|
|
float f;
|
|
|
|
uint32_t u;
|
|
|
|
} u;
|
|
|
|
u.f = value;
|
|
|
|
return put_dword(buffer, u.u);
|
|
|
|
}
|
|
|
|
|
2021-04-15 17:03:46 -07:00
|
|
|
static void set_dword(struct bytecode_buffer *buffer, unsigned int index, uint32_t value)
|
|
|
|
{
|
|
|
|
if (buffer->status)
|
|
|
|
return;
|
|
|
|
|
|
|
|
assert(index < buffer->count);
|
|
|
|
buffer->data[index] = value;
|
|
|
|
}
|
|
|
|
|
2021-04-27 10:14:16 -07:00
|
|
|
/* Returns the token index. */
|
|
|
|
static unsigned int put_string(struct bytecode_buffer *buffer, const char *str)
|
2021-04-15 17:03:46 -07:00
|
|
|
{
|
2021-04-27 10:14:16 -07:00
|
|
|
unsigned int index = buffer->count;
|
2021-04-15 17:03:46 -07:00
|
|
|
size_t len = strlen(str) + 1;
|
|
|
|
unsigned int token_count = (len + 3) / sizeof(*buffer->data);
|
|
|
|
|
|
|
|
if (buffer->status)
|
2021-04-27 10:14:16 -07:00
|
|
|
return index;
|
2021-04-15 17:03:46 -07:00
|
|
|
|
2021-05-20 22:32:20 -07:00
|
|
|
if (!hlsl_array_reserve(buffer->ctx, (void **)&buffer->data, &buffer->size,
|
|
|
|
buffer->count + token_count, sizeof(*buffer->data)))
|
2021-04-15 17:03:46 -07:00
|
|
|
{
|
|
|
|
buffer->status = E_OUTOFMEMORY;
|
2021-04-27 10:14:16 -07:00
|
|
|
return index;
|
2021-04-15 17:03:46 -07:00
|
|
|
}
|
|
|
|
|
|
|
|
buffer->data[buffer->count + token_count - 1] = 0xabababab;
|
|
|
|
memcpy(buffer->data + buffer->count, str, len);
|
|
|
|
buffer->count += token_count;
|
2021-04-27 10:14:16 -07:00
|
|
|
return index;
|
2021-04-15 17:03:46 -07:00
|
|
|
}
|
|
|
|
|
2021-04-15 17:03:43 -07:00
|
|
|
static uint32_t sm1_version(enum vkd3d_shader_type type, unsigned int major, unsigned int minor)
|
|
|
|
{
|
|
|
|
if (type == VKD3D_SHADER_TYPE_VERTEX)
|
|
|
|
return D3DVS_VERSION(major, minor);
|
|
|
|
else
|
|
|
|
return D3DPS_VERSION(major, minor);
|
|
|
|
}
|
|
|
|
|
2021-04-15 17:03:46 -07:00
|
|
|
static D3DXPARAMETER_CLASS sm1_class(const struct hlsl_type *type)
|
|
|
|
{
|
|
|
|
switch (type->type)
|
|
|
|
{
|
|
|
|
case HLSL_CLASS_ARRAY:
|
|
|
|
return sm1_class(type->e.array.type);
|
|
|
|
case HLSL_CLASS_MATRIX:
|
|
|
|
assert(type->modifiers & HLSL_MODIFIERS_MAJORITY_MASK);
|
|
|
|
if (type->modifiers & HLSL_MODIFIER_COLUMN_MAJOR)
|
|
|
|
return D3DXPC_MATRIX_COLUMNS;
|
|
|
|
else
|
|
|
|
return D3DXPC_MATRIX_ROWS;
|
|
|
|
case HLSL_CLASS_OBJECT:
|
|
|
|
return D3DXPC_OBJECT;
|
|
|
|
case HLSL_CLASS_SCALAR:
|
|
|
|
return D3DXPC_SCALAR;
|
|
|
|
case HLSL_CLASS_STRUCT:
|
|
|
|
return D3DXPC_STRUCT;
|
|
|
|
case HLSL_CLASS_VECTOR:
|
|
|
|
return D3DXPC_VECTOR;
|
|
|
|
default:
|
|
|
|
ERR("Invalid class %#x.\n", type->type);
|
|
|
|
assert(0);
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static D3DXPARAMETER_TYPE sm1_base_type(const struct hlsl_type *type)
|
|
|
|
{
|
|
|
|
switch (type->base_type)
|
|
|
|
{
|
|
|
|
case HLSL_TYPE_BOOL:
|
|
|
|
return D3DXPT_BOOL;
|
|
|
|
case HLSL_TYPE_FLOAT:
|
|
|
|
case HLSL_TYPE_HALF:
|
|
|
|
return D3DXPT_FLOAT;
|
|
|
|
case HLSL_TYPE_INT:
|
|
|
|
case HLSL_TYPE_UINT:
|
|
|
|
return D3DXPT_INT;
|
|
|
|
case HLSL_TYPE_PIXELSHADER:
|
|
|
|
return D3DXPT_PIXELSHADER;
|
|
|
|
case HLSL_TYPE_SAMPLER:
|
|
|
|
switch (type->sampler_dim)
|
|
|
|
{
|
|
|
|
case HLSL_SAMPLER_DIM_1D:
|
|
|
|
return D3DXPT_SAMPLER1D;
|
|
|
|
case HLSL_SAMPLER_DIM_2D:
|
|
|
|
return D3DXPT_SAMPLER2D;
|
|
|
|
case HLSL_SAMPLER_DIM_3D:
|
|
|
|
return D3DXPT_SAMPLER3D;
|
|
|
|
case HLSL_SAMPLER_DIM_CUBE:
|
|
|
|
return D3DXPT_SAMPLERCUBE;
|
|
|
|
case HLSL_SAMPLER_DIM_GENERIC:
|
|
|
|
return D3DXPT_SAMPLER;
|
|
|
|
default:
|
|
|
|
ERR("Invalid dimension %#x.\n", type->sampler_dim);
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
case HLSL_TYPE_STRING:
|
|
|
|
return D3DXPT_STRING;
|
|
|
|
case HLSL_TYPE_TEXTURE:
|
|
|
|
switch (type->sampler_dim)
|
|
|
|
{
|
|
|
|
case HLSL_SAMPLER_DIM_1D:
|
|
|
|
return D3DXPT_TEXTURE1D;
|
|
|
|
case HLSL_SAMPLER_DIM_2D:
|
|
|
|
return D3DXPT_TEXTURE2D;
|
|
|
|
case HLSL_SAMPLER_DIM_3D:
|
|
|
|
return D3DXPT_TEXTURE3D;
|
|
|
|
case HLSL_SAMPLER_DIM_CUBE:
|
|
|
|
return D3DXPT_TEXTURECUBE;
|
|
|
|
case HLSL_SAMPLER_DIM_GENERIC:
|
|
|
|
return D3DXPT_TEXTURE;
|
|
|
|
default:
|
|
|
|
ERR("Invalid dimension %#x.\n", type->sampler_dim);
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
case HLSL_TYPE_VERTEXSHADER:
|
|
|
|
return D3DXPT_VERTEXSHADER;
|
|
|
|
case HLSL_TYPE_VOID:
|
|
|
|
return D3DXPT_VOID;
|
|
|
|
default:
|
|
|
|
assert(0);
|
|
|
|
}
|
|
|
|
assert(0);
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static const struct hlsl_type *get_array_type(const struct hlsl_type *type)
|
|
|
|
{
|
|
|
|
if (type->type == HLSL_CLASS_ARRAY)
|
|
|
|
return get_array_type(type->e.array.type);
|
|
|
|
return type;
|
|
|
|
}
|
|
|
|
|
|
|
|
static unsigned int get_array_size(const struct hlsl_type *type)
|
|
|
|
{
|
|
|
|
if (type->type == HLSL_CLASS_ARRAY)
|
|
|
|
return get_array_size(type->e.array.type) * type->e.array.elements_count;
|
|
|
|
return 1;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void write_sm1_type(struct bytecode_buffer *buffer, struct hlsl_type *type, unsigned int ctab_start)
|
|
|
|
{
|
|
|
|
const struct hlsl_type *array_type = get_array_type(type);
|
|
|
|
unsigned int fields_offset = 0, field_count = 0;
|
|
|
|
unsigned int array_size = get_array_size(type);
|
|
|
|
struct hlsl_struct_field *field;
|
|
|
|
|
|
|
|
if (type->bytecode_offset)
|
|
|
|
return;
|
|
|
|
|
|
|
|
if (array_type->type == HLSL_CLASS_STRUCT)
|
|
|
|
{
|
|
|
|
LIST_FOR_EACH_ENTRY(field, array_type->e.elements, struct hlsl_struct_field, entry)
|
|
|
|
{
|
2021-04-27 10:14:16 -07:00
|
|
|
field->name_bytecode_offset = put_string(buffer, field->name);
|
2021-04-15 17:03:46 -07:00
|
|
|
write_sm1_type(buffer, field->type, ctab_start);
|
|
|
|
}
|
|
|
|
|
|
|
|
fields_offset = (buffer->count - ctab_start) * sizeof(*buffer->data);
|
|
|
|
|
|
|
|
LIST_FOR_EACH_ENTRY(field, array_type->e.elements, struct hlsl_struct_field, entry)
|
|
|
|
{
|
2021-04-27 10:14:15 -07:00
|
|
|
put_dword(buffer, (field->name_bytecode_offset - ctab_start) * sizeof(*buffer->data));
|
2021-04-15 17:03:46 -07:00
|
|
|
put_dword(buffer, (field->type->bytecode_offset - ctab_start) * sizeof(*buffer->data));
|
|
|
|
++field_count;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2021-04-27 10:14:16 -07:00
|
|
|
type->bytecode_offset = put_dword(buffer, sm1_class(type) | (sm1_base_type(type) << 16));
|
2021-04-15 17:03:46 -07:00
|
|
|
put_dword(buffer, type->dimy | (type->dimx << 16));
|
|
|
|
put_dword(buffer, array_size | (field_count << 16));
|
|
|
|
put_dword(buffer, fields_offset);
|
|
|
|
}
|
|
|
|
|
2021-04-15 17:03:47 -07:00
|
|
|
static void sm1_sort_extern(struct list *sorted, struct hlsl_ir_var *to_sort)
|
|
|
|
{
|
|
|
|
struct hlsl_ir_var *var;
|
|
|
|
|
|
|
|
list_remove(&to_sort->extern_entry);
|
|
|
|
|
|
|
|
LIST_FOR_EACH_ENTRY(var, sorted, struct hlsl_ir_var, extern_entry)
|
|
|
|
{
|
|
|
|
if (strcmp(to_sort->name, var->name) < 0)
|
|
|
|
{
|
|
|
|
list_add_before(&var->extern_entry, &to_sort->extern_entry);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
list_add_tail(sorted, &to_sort->extern_entry);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void sm1_sort_externs(struct hlsl_ctx *ctx)
|
|
|
|
{
|
|
|
|
struct list sorted = LIST_INIT(sorted);
|
|
|
|
struct hlsl_ir_var *var, *next;
|
|
|
|
|
|
|
|
LIST_FOR_EACH_ENTRY_SAFE(var, next, &ctx->extern_vars, struct hlsl_ir_var, extern_entry)
|
|
|
|
sm1_sort_extern(&sorted, var);
|
|
|
|
list_move_tail(&ctx->extern_vars, &sorted);
|
|
|
|
}
|
|
|
|
|
2021-04-15 17:03:46 -07:00
|
|
|
static void write_sm1_uniforms(struct hlsl_ctx *ctx, struct bytecode_buffer *buffer,
|
|
|
|
struct hlsl_ir_function_decl *entry_func)
|
|
|
|
{
|
2021-04-27 10:14:16 -07:00
|
|
|
unsigned int ctab_start, vars_start, size_offset, creator_offset, offset;
|
2021-04-15 17:03:46 -07:00
|
|
|
unsigned int uniform_count = 0;
|
|
|
|
struct hlsl_ir_var *var;
|
|
|
|
|
|
|
|
LIST_FOR_EACH_ENTRY(var, &ctx->extern_vars, struct hlsl_ir_var, extern_entry)
|
|
|
|
{
|
2021-04-27 10:14:19 -07:00
|
|
|
if (!var->semantic.name && var->reg.allocated)
|
2021-04-15 17:03:46 -07:00
|
|
|
{
|
|
|
|
++uniform_count;
|
|
|
|
|
|
|
|
if (var->is_param && var->is_uniform)
|
|
|
|
{
|
|
|
|
struct vkd3d_string_buffer *name;
|
|
|
|
|
2021-05-20 22:32:21 -07:00
|
|
|
if (!(name = hlsl_get_string_buffer(ctx)))
|
2021-04-15 17:03:46 -07:00
|
|
|
{
|
|
|
|
buffer->status = VKD3D_ERROR_OUT_OF_MEMORY;
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
vkd3d_string_buffer_printf(name, "$%s", var->name);
|
|
|
|
vkd3d_free((char *)var->name);
|
2021-05-20 22:32:20 -07:00
|
|
|
var->name = hlsl_strdup(ctx, name->buffer);
|
2021-05-20 22:32:21 -07:00
|
|
|
hlsl_release_string_buffer(ctx, name);
|
2021-04-15 17:03:46 -07:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2021-04-15 17:03:47 -07:00
|
|
|
sm1_sort_externs(ctx);
|
|
|
|
|
2021-04-27 10:14:16 -07:00
|
|
|
size_offset = put_dword(buffer, 0);
|
2021-04-15 17:03:46 -07:00
|
|
|
put_dword(buffer, MAKEFOURCC('C','T','A','B'));
|
|
|
|
|
2021-04-27 10:14:16 -07:00
|
|
|
ctab_start = put_dword(buffer, sizeof(D3DXSHADER_CONSTANTTABLE));
|
|
|
|
creator_offset = put_dword(buffer, 0);
|
2021-04-15 17:03:46 -07:00
|
|
|
put_dword(buffer, sm1_version(ctx->profile->type, ctx->profile->major_version, ctx->profile->minor_version));
|
|
|
|
put_dword(buffer, uniform_count);
|
|
|
|
put_dword(buffer, sizeof(D3DXSHADER_CONSTANTTABLE)); /* offset of constants */
|
|
|
|
put_dword(buffer, 0); /* FIXME: flags */
|
|
|
|
put_dword(buffer, 0); /* FIXME: target string */
|
|
|
|
|
|
|
|
vars_start = buffer->count;
|
|
|
|
|
|
|
|
LIST_FOR_EACH_ENTRY(var, &ctx->extern_vars, struct hlsl_ir_var, extern_entry)
|
|
|
|
{
|
2021-04-27 10:14:19 -07:00
|
|
|
if (!var->semantic.name && var->reg.allocated)
|
2021-04-15 17:03:46 -07:00
|
|
|
{
|
|
|
|
put_dword(buffer, 0); /* name */
|
|
|
|
put_dword(buffer, D3DXRS_FLOAT4 | (var->reg.id << 16));
|
|
|
|
put_dword(buffer, var->data_type->reg_size);
|
|
|
|
put_dword(buffer, 0); /* type */
|
|
|
|
put_dword(buffer, 0); /* FIXME: default value */
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
uniform_count = 0;
|
|
|
|
|
|
|
|
LIST_FOR_EACH_ENTRY(var, &ctx->extern_vars, struct hlsl_ir_var, extern_entry)
|
|
|
|
{
|
2021-04-27 10:14:19 -07:00
|
|
|
if (!var->semantic.name && var->reg.allocated)
|
2021-04-15 17:03:46 -07:00
|
|
|
{
|
|
|
|
set_dword(buffer, vars_start + (uniform_count * 5), (buffer->count - ctab_start) * sizeof(*buffer->data));
|
|
|
|
put_string(buffer, var->name);
|
|
|
|
|
|
|
|
write_sm1_type(buffer, var->data_type, ctab_start);
|
|
|
|
set_dword(buffer, vars_start + (uniform_count * 5) + 3,
|
|
|
|
(var->data_type->bytecode_offset - ctab_start) * sizeof(*buffer->data));
|
|
|
|
++uniform_count;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2021-04-27 10:14:16 -07:00
|
|
|
offset = put_string(buffer, vkd3d_shader_get_version(NULL, NULL));
|
|
|
|
set_dword(buffer, creator_offset, (offset - ctab_start) * sizeof(*buffer->data));
|
2021-04-15 17:03:46 -07:00
|
|
|
|
2021-04-27 10:14:16 -07:00
|
|
|
set_dword(buffer, size_offset, D3DSIO_COMMENT | ((buffer->count - (ctab_start - 1)) << 16));
|
2021-04-15 17:03:46 -07:00
|
|
|
}
|
|
|
|
|
2021-04-27 10:14:17 -07:00
|
|
|
static uint32_t sm1_encode_register_type(D3DSHADER_PARAM_REGISTER_TYPE type)
|
|
|
|
{
|
|
|
|
return ((type << D3DSP_REGTYPE_SHIFT) & D3DSP_REGTYPE_MASK)
|
|
|
|
| ((type << D3DSP_REGTYPE_SHIFT2) & D3DSP_REGTYPE_MASK2);
|
|
|
|
}
|
|
|
|
|
2021-05-10 21:36:08 -07:00
|
|
|
struct sm1_instruction
|
|
|
|
{
|
|
|
|
D3DSHADER_INSTRUCTION_OPCODE_TYPE opcode;
|
|
|
|
|
2021-05-16 10:47:52 -07:00
|
|
|
struct sm1_dst_register
|
2021-05-10 21:36:08 -07:00
|
|
|
{
|
|
|
|
D3DSHADER_PARAM_REGISTER_TYPE type;
|
|
|
|
D3DSHADER_PARAM_DSTMOD_TYPE mod;
|
|
|
|
unsigned int writemask;
|
|
|
|
uint32_t reg;
|
|
|
|
} dst;
|
|
|
|
|
2021-05-16 10:47:52 -07:00
|
|
|
struct sm1_src_register
|
2021-05-10 21:36:08 -07:00
|
|
|
{
|
|
|
|
D3DSHADER_PARAM_REGISTER_TYPE type;
|
|
|
|
D3DSHADER_PARAM_SRCMOD_TYPE mod;
|
|
|
|
unsigned int swizzle;
|
|
|
|
uint32_t reg;
|
|
|
|
} srcs[2];
|
|
|
|
unsigned int src_count;
|
|
|
|
|
|
|
|
unsigned int has_dst;
|
|
|
|
};
|
|
|
|
|
2021-05-16 10:47:52 -07:00
|
|
|
static void write_sm1_dst_register(struct bytecode_buffer *buffer, const struct sm1_dst_register *reg)
|
|
|
|
{
|
|
|
|
assert(reg->writemask);
|
|
|
|
put_dword(buffer, (1u << 31) | sm1_encode_register_type(reg->type) | reg->mod | (reg->writemask << 16) | reg->reg);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void write_sm1_src_register(struct bytecode_buffer *buffer,
|
|
|
|
const struct sm1_src_register *reg, unsigned int dst_writemask)
|
|
|
|
{
|
|
|
|
unsigned int swizzle = map_swizzle(reg->swizzle, dst_writemask);
|
|
|
|
|
|
|
|
put_dword(buffer, (1u << 31) | sm1_encode_register_type(reg->type) | reg->mod | (swizzle << 16) | reg->reg);
|
|
|
|
}
|
|
|
|
|
2021-05-10 21:36:08 -07:00
|
|
|
static void write_sm1_instruction(struct hlsl_ctx *ctx, struct bytecode_buffer *buffer,
|
|
|
|
const struct sm1_instruction *instr)
|
|
|
|
{
|
|
|
|
uint32_t token = instr->opcode;
|
|
|
|
unsigned int i;
|
|
|
|
|
|
|
|
if (ctx->profile->major_version > 1)
|
|
|
|
token |= (instr->has_dst + instr->src_count) << D3DSI_INSTLENGTH_SHIFT;
|
|
|
|
put_dword(buffer, token);
|
|
|
|
|
|
|
|
if (instr->has_dst)
|
2021-05-16 10:47:52 -07:00
|
|
|
write_sm1_dst_register(buffer, &instr->dst);
|
2021-05-10 21:36:08 -07:00
|
|
|
|
|
|
|
for (i = 0; i < instr->src_count; ++i)
|
2021-05-16 10:47:52 -07:00
|
|
|
write_sm1_src_register(buffer, &instr->srcs[i], instr->dst.writemask);
|
2021-05-10 21:36:08 -07:00
|
|
|
};
|
|
|
|
|
2021-05-18 13:55:23 -07:00
|
|
|
static void write_sm1_binary_op(struct hlsl_ctx *ctx, struct bytecode_buffer *buffer,
|
|
|
|
D3DSHADER_INSTRUCTION_OPCODE_TYPE opcode, const struct hlsl_reg *dst,
|
|
|
|
const struct hlsl_reg *src1, const struct hlsl_reg *src2)
|
|
|
|
{
|
|
|
|
const struct sm1_instruction instr =
|
|
|
|
{
|
|
|
|
.opcode = opcode,
|
|
|
|
|
|
|
|
.dst.type = D3DSPR_TEMP,
|
|
|
|
.dst.writemask = dst->writemask,
|
|
|
|
.dst.reg = dst->id,
|
|
|
|
.has_dst = 1,
|
|
|
|
|
|
|
|
.srcs[0].type = D3DSPR_TEMP,
|
|
|
|
.srcs[0].swizzle = swizzle_from_writemask(src1->writemask),
|
|
|
|
.srcs[0].reg = src1->id,
|
|
|
|
.srcs[1].type = D3DSPR_TEMP,
|
|
|
|
.srcs[1].swizzle = swizzle_from_writemask(src2->writemask),
|
|
|
|
.srcs[1].reg = src2->id,
|
|
|
|
.src_count = 2,
|
|
|
|
};
|
|
|
|
write_sm1_instruction(ctx, buffer, &instr);
|
|
|
|
}
|
|
|
|
|
2021-05-18 13:55:25 -07:00
|
|
|
static void write_sm1_unary_op(struct hlsl_ctx *ctx, struct bytecode_buffer *buffer,
|
|
|
|
D3DSHADER_INSTRUCTION_OPCODE_TYPE opcode, const struct hlsl_reg *dst,
|
|
|
|
const struct hlsl_reg *src, D3DSHADER_PARAM_SRCMOD_TYPE src_mod)
|
|
|
|
{
|
|
|
|
const struct sm1_instruction instr =
|
|
|
|
{
|
|
|
|
.opcode = opcode,
|
|
|
|
|
|
|
|
.dst.type = D3DSPR_TEMP,
|
|
|
|
.dst.writemask = dst->writemask,
|
|
|
|
.dst.reg = dst->id,
|
|
|
|
.has_dst = 1,
|
|
|
|
|
|
|
|
.srcs[0].type = D3DSPR_TEMP,
|
|
|
|
.srcs[0].swizzle = swizzle_from_writemask(src->writemask),
|
|
|
|
.srcs[0].reg = src->id,
|
|
|
|
.srcs[0].mod = src_mod,
|
|
|
|
.src_count = 1,
|
|
|
|
};
|
|
|
|
write_sm1_instruction(ctx, buffer, &instr);
|
|
|
|
}
|
|
|
|
|
2021-04-27 10:14:17 -07:00
|
|
|
static void write_sm1_constant_defs(struct hlsl_ctx *ctx, struct bytecode_buffer *buffer)
|
|
|
|
{
|
|
|
|
unsigned int i, x;
|
|
|
|
|
|
|
|
for (i = 0; i < ctx->constant_defs.count; ++i)
|
|
|
|
{
|
|
|
|
uint32_t token = D3DSIO_DEF;
|
2021-05-16 10:47:52 -07:00
|
|
|
const struct sm1_dst_register reg =
|
|
|
|
{
|
|
|
|
.type = D3DSPR_CONST,
|
|
|
|
.writemask = VKD3DSP_WRITEMASK_ALL,
|
|
|
|
.reg = i,
|
|
|
|
};
|
2021-04-27 10:14:17 -07:00
|
|
|
|
|
|
|
if (ctx->profile->major_version > 1)
|
|
|
|
token |= 5 << D3DSI_INSTLENGTH_SHIFT;
|
|
|
|
put_dword(buffer, token);
|
|
|
|
|
2021-05-16 10:47:52 -07:00
|
|
|
write_sm1_dst_register(buffer, ®);
|
2021-04-27 10:14:17 -07:00
|
|
|
for (x = 0; x < 4; ++x)
|
|
|
|
put_float(buffer, ctx->constant_defs.values[i].f[x]);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2021-05-10 21:36:07 -07:00
|
|
|
static void write_sm1_semantic_dcl(struct hlsl_ctx *ctx, struct bytecode_buffer *buffer,
|
|
|
|
const struct hlsl_ir_var *var, bool output)
|
|
|
|
{
|
2021-05-16 10:47:52 -07:00
|
|
|
struct sm1_dst_register reg = {0};
|
|
|
|
uint32_t token, usage_idx;
|
2021-05-10 21:36:07 -07:00
|
|
|
D3DDECLUSAGE usage;
|
|
|
|
bool ret;
|
|
|
|
|
2021-05-16 10:47:52 -07:00
|
|
|
if (sm1_register_from_semantic(ctx, &var->semantic, output, ®.type, ®.reg))
|
2021-05-10 21:36:07 -07:00
|
|
|
{
|
|
|
|
usage = 0;
|
|
|
|
usage_idx = 0;
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
ret = sm1_usage_from_semantic(&var->semantic, &usage, &usage_idx);
|
|
|
|
assert(ret);
|
2021-05-16 10:47:52 -07:00
|
|
|
reg.type = output ? D3DSPR_OUTPUT : D3DSPR_INPUT;
|
|
|
|
reg.reg = var->reg.id;
|
2021-05-10 21:36:07 -07:00
|
|
|
}
|
|
|
|
|
|
|
|
token = D3DSIO_DCL;
|
|
|
|
if (ctx->profile->major_version > 1)
|
|
|
|
token |= 2 << D3DSI_INSTLENGTH_SHIFT;
|
|
|
|
put_dword(buffer, token);
|
|
|
|
|
|
|
|
token = (1u << 31);
|
|
|
|
token |= usage << D3DSP_DCL_USAGE_SHIFT;
|
|
|
|
token |= usage_idx << D3DSP_DCL_USAGEINDEX_SHIFT;
|
|
|
|
put_dword(buffer, token);
|
2021-05-16 10:47:52 -07:00
|
|
|
|
|
|
|
reg.writemask = (1 << var->data_type->dimx) - 1;
|
|
|
|
write_sm1_dst_register(buffer, ®);
|
2021-05-10 21:36:07 -07:00
|
|
|
}
|
|
|
|
|
|
|
|
static void write_sm1_semantic_dcls(struct hlsl_ctx *ctx, struct bytecode_buffer *buffer)
|
|
|
|
{
|
|
|
|
bool write_in = false, write_out = false;
|
|
|
|
struct hlsl_ir_var *var;
|
|
|
|
|
|
|
|
if (ctx->profile->type == VKD3D_SHADER_TYPE_PIXEL)
|
|
|
|
write_in = true;
|
|
|
|
else if (ctx->profile->type == VKD3D_SHADER_TYPE_VERTEX && ctx->profile->major_version == 3)
|
|
|
|
write_in = write_out = true;
|
|
|
|
else if (ctx->profile->type == VKD3D_SHADER_TYPE_VERTEX && ctx->profile->major_version < 3)
|
|
|
|
write_in = true;
|
|
|
|
|
|
|
|
LIST_FOR_EACH_ENTRY(var, &ctx->extern_vars, struct hlsl_ir_var, extern_entry)
|
|
|
|
{
|
|
|
|
if (write_in && var->is_input_semantic)
|
|
|
|
write_sm1_semantic_dcl(ctx, buffer, var, false);
|
|
|
|
if (write_out && var->is_output_semantic)
|
|
|
|
write_sm1_semantic_dcl(ctx, buffer, var, true);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2021-05-18 13:55:21 -07:00
|
|
|
static void write_sm1_constant(struct hlsl_ctx *ctx, struct bytecode_buffer *buffer, const struct hlsl_ir_node *instr)
|
|
|
|
{
|
|
|
|
const struct hlsl_ir_constant *constant = hlsl_ir_constant(instr);
|
|
|
|
struct sm1_instruction sm1_instr =
|
|
|
|
{
|
|
|
|
.opcode = D3DSIO_MOV,
|
|
|
|
|
|
|
|
.dst.type = D3DSPR_TEMP,
|
|
|
|
.dst.reg = instr->reg.id,
|
|
|
|
.dst.writemask = instr->reg.writemask,
|
|
|
|
.has_dst = 1,
|
|
|
|
|
|
|
|
.srcs[0].type = D3DSPR_CONST,
|
|
|
|
.srcs[0].reg = constant->reg.id,
|
|
|
|
.srcs[0].swizzle = swizzle_from_writemask(constant->reg.writemask),
|
|
|
|
.src_count = 1,
|
|
|
|
};
|
|
|
|
|
|
|
|
assert(instr->reg.allocated);
|
|
|
|
assert(constant->reg.allocated);
|
|
|
|
write_sm1_instruction(ctx, buffer, &sm1_instr);
|
|
|
|
}
|
|
|
|
|
2021-05-18 13:55:23 -07:00
|
|
|
static void write_sm1_expr(struct hlsl_ctx *ctx, struct bytecode_buffer *buffer, const struct hlsl_ir_node *instr)
|
|
|
|
{
|
|
|
|
struct hlsl_ir_expr *expr = hlsl_ir_expr(instr);
|
|
|
|
struct hlsl_ir_node *arg1 = expr->operands[0].node;
|
|
|
|
struct hlsl_ir_node *arg2 = expr->operands[1].node;
|
|
|
|
|
|
|
|
assert(instr->reg.allocated);
|
|
|
|
|
|
|
|
if (instr->data_type->base_type != HLSL_TYPE_FLOAT)
|
|
|
|
{
|
|
|
|
FIXME("Non-float operations need to be lowered.\n");
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
switch (expr->op)
|
|
|
|
{
|
|
|
|
case HLSL_IR_BINOP_ADD:
|
|
|
|
write_sm1_binary_op(ctx, buffer, D3DSIO_ADD, &instr->reg, &arg1->reg, &arg2->reg);
|
|
|
|
break;
|
|
|
|
|
2021-05-18 13:55:24 -07:00
|
|
|
case HLSL_IR_BINOP_MUL:
|
|
|
|
write_sm1_binary_op(ctx, buffer, D3DSIO_MUL, &instr->reg, &arg1->reg, &arg2->reg);
|
|
|
|
break;
|
|
|
|
|
2021-05-18 13:55:25 -07:00
|
|
|
case HLSL_IR_UNOP_NEG:
|
|
|
|
write_sm1_unary_op(ctx, buffer, D3DSIO_MOV, &instr->reg, &arg1->reg, D3DSPSM_NEG);
|
|
|
|
break;
|
|
|
|
|
2021-05-18 13:55:23 -07:00
|
|
|
default:
|
|
|
|
FIXME("Unhandled op %u.\n", expr->op);
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2021-05-16 10:47:54 -07:00
|
|
|
static void write_sm1_load(struct hlsl_ctx *ctx, struct bytecode_buffer *buffer, const struct hlsl_ir_node *instr)
|
|
|
|
{
|
|
|
|
const struct hlsl_ir_load *load = hlsl_ir_load(instr);
|
|
|
|
const struct hlsl_reg reg = hlsl_reg_from_deref(&load->src, instr->data_type);
|
|
|
|
struct sm1_instruction sm1_instr =
|
|
|
|
{
|
|
|
|
.opcode = D3DSIO_MOV,
|
|
|
|
|
|
|
|
.dst.type = D3DSPR_TEMP,
|
|
|
|
.dst.reg = instr->reg.id,
|
|
|
|
.dst.writemask = instr->reg.writemask,
|
|
|
|
.has_dst = 1,
|
|
|
|
|
|
|
|
.srcs[0].type = D3DSPR_TEMP,
|
|
|
|
.srcs[0].reg = reg.id,
|
|
|
|
.srcs[0].swizzle = swizzle_from_writemask(reg.writemask),
|
|
|
|
.src_count = 1,
|
|
|
|
};
|
|
|
|
|
|
|
|
assert(instr->reg.allocated);
|
|
|
|
|
|
|
|
if (load->src.var->is_uniform)
|
|
|
|
{
|
|
|
|
assert(reg.allocated);
|
|
|
|
sm1_instr.srcs[0].type = D3DSPR_CONST;
|
|
|
|
}
|
|
|
|
else if (load->src.var->is_input_semantic)
|
|
|
|
{
|
|
|
|
if (!sm1_register_from_semantic(ctx, &load->src.var->semantic,
|
|
|
|
false, &sm1_instr.srcs[0].type, &sm1_instr.srcs[0].reg))
|
|
|
|
{
|
|
|
|
assert(reg.allocated);
|
|
|
|
sm1_instr.srcs[0].type = D3DSPR_INPUT;
|
|
|
|
sm1_instr.srcs[0].reg = reg.id;
|
|
|
|
}
|
|
|
|
else
|
|
|
|
sm1_instr.srcs[0].swizzle = swizzle_from_writemask((1 << load->src.var->data_type->dimx) - 1);
|
|
|
|
}
|
|
|
|
|
|
|
|
write_sm1_instruction(ctx, buffer, &sm1_instr);
|
|
|
|
}
|
|
|
|
|
2021-05-10 21:36:08 -07:00
|
|
|
static void write_sm1_store(struct hlsl_ctx *ctx, struct bytecode_buffer *buffer, const struct hlsl_ir_node *instr)
|
|
|
|
{
|
|
|
|
const struct hlsl_ir_store *store = hlsl_ir_store(instr);
|
|
|
|
const struct hlsl_ir_node *rhs = store->rhs.node;
|
|
|
|
const struct hlsl_reg reg = hlsl_reg_from_deref(&store->lhs, rhs->data_type);
|
|
|
|
struct sm1_instruction sm1_instr =
|
|
|
|
{
|
|
|
|
.opcode = D3DSIO_MOV,
|
|
|
|
|
|
|
|
.dst.type = D3DSPR_TEMP,
|
|
|
|
.dst.reg = reg.id,
|
|
|
|
.dst.writemask = combine_writemasks(reg.writemask, store->writemask),
|
|
|
|
.has_dst = 1,
|
|
|
|
|
|
|
|
.srcs[0].type = D3DSPR_TEMP,
|
|
|
|
.srcs[0].reg = rhs->reg.id,
|
|
|
|
.srcs[0].swizzle = swizzle_from_writemask(rhs->reg.writemask),
|
|
|
|
.src_count = 1,
|
|
|
|
};
|
|
|
|
|
|
|
|
if (store->lhs.var->data_type->type == HLSL_CLASS_MATRIX)
|
|
|
|
{
|
|
|
|
FIXME("Matrix writemasks need to be lowered.\n");
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (store->lhs.var->is_output_semantic)
|
|
|
|
{
|
|
|
|
if (!sm1_register_from_semantic(ctx, &store->lhs.var->semantic, true, &sm1_instr.dst.type, &sm1_instr.dst.reg))
|
|
|
|
{
|
|
|
|
assert(reg.allocated);
|
|
|
|
sm1_instr.dst.type = D3DSPR_OUTPUT;
|
|
|
|
sm1_instr.dst.reg = reg.id;
|
|
|
|
}
|
|
|
|
else
|
|
|
|
sm1_instr.dst.writemask = (1u << store->lhs.var->data_type->dimx) - 1;
|
|
|
|
}
|
|
|
|
else
|
|
|
|
assert(reg.allocated);
|
|
|
|
|
|
|
|
write_sm1_instruction(ctx, buffer, &sm1_instr);
|
|
|
|
}
|
|
|
|
|
2021-05-18 13:55:22 -07:00
|
|
|
static void write_sm1_swizzle(struct hlsl_ctx *ctx, struct bytecode_buffer *buffer, const struct hlsl_ir_node *instr)
|
|
|
|
{
|
|
|
|
const struct hlsl_ir_swizzle *swizzle = hlsl_ir_swizzle(instr);
|
|
|
|
const struct hlsl_ir_node *val = swizzle->val.node;
|
|
|
|
struct sm1_instruction sm1_instr =
|
|
|
|
{
|
|
|
|
.opcode = D3DSIO_MOV,
|
|
|
|
|
|
|
|
.dst.type = D3DSPR_TEMP,
|
|
|
|
.dst.reg = instr->reg.id,
|
|
|
|
.dst.writemask = instr->reg.writemask,
|
|
|
|
.has_dst = 1,
|
|
|
|
|
|
|
|
.srcs[0].type = D3DSPR_TEMP,
|
|
|
|
.srcs[0].reg = val->reg.id,
|
|
|
|
.srcs[0].swizzle = combine_swizzles(swizzle_from_writemask(val->reg.writemask),
|
|
|
|
swizzle->swizzle, instr->data_type->dimx),
|
|
|
|
.src_count = 1,
|
|
|
|
};
|
|
|
|
|
|
|
|
assert(instr->reg.allocated);
|
|
|
|
assert(val->reg.allocated);
|
|
|
|
write_sm1_instruction(ctx, buffer, &sm1_instr);
|
|
|
|
}
|
|
|
|
|
2021-05-10 21:36:08 -07:00
|
|
|
static void write_sm1_instructions(struct hlsl_ctx *ctx, struct bytecode_buffer *buffer,
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const struct hlsl_ir_function_decl *entry_func)
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{
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const struct hlsl_ir_node *instr;
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LIST_FOR_EACH_ENTRY(instr, entry_func->body, struct hlsl_ir_node, entry)
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{
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if (instr->data_type)
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{
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if (instr->data_type->type == HLSL_CLASS_MATRIX)
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{
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FIXME("Matrix operations need to be lowered.\n");
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break;
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}
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assert(instr->data_type->type == HLSL_CLASS_SCALAR || instr->data_type->type == HLSL_CLASS_VECTOR);
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}
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switch (instr->type)
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{
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2021-05-18 13:55:21 -07:00
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case HLSL_IR_CONSTANT:
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write_sm1_constant(ctx, buffer, instr);
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break;
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2021-05-18 13:55:23 -07:00
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case HLSL_IR_EXPR:
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write_sm1_expr(ctx, buffer, instr);
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break;
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2021-05-16 10:47:54 -07:00
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case HLSL_IR_LOAD:
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write_sm1_load(ctx, buffer, instr);
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break;
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2021-05-10 21:36:08 -07:00
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case HLSL_IR_STORE:
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write_sm1_store(ctx, buffer, instr);
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break;
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2021-05-18 13:55:22 -07:00
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case HLSL_IR_SWIZZLE:
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write_sm1_swizzle(ctx, buffer, instr);
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break;
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2021-05-10 21:36:08 -07:00
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default:
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FIXME("Unhandled instruction type %s.\n", hlsl_node_type_to_string(instr->type));
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}
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}
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}
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2021-04-15 17:03:43 -07:00
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static int write_sm1_shader(struct hlsl_ctx *ctx, struct hlsl_ir_function_decl *entry_func,
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struct vkd3d_shader_code *out)
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{
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2021-05-20 22:32:20 -07:00
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struct bytecode_buffer buffer = {.ctx = ctx};
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2021-04-15 17:03:43 -07:00
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int ret;
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put_dword(&buffer, sm1_version(ctx->profile->type, ctx->profile->major_version, ctx->profile->minor_version));
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2021-04-15 17:03:46 -07:00
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write_sm1_uniforms(ctx, &buffer, entry_func);
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2021-04-27 10:14:17 -07:00
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write_sm1_constant_defs(ctx, &buffer);
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2021-05-10 21:36:07 -07:00
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write_sm1_semantic_dcls(ctx, &buffer);
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2021-05-10 21:36:08 -07:00
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write_sm1_instructions(ctx, &buffer, entry_func);
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2021-04-27 10:14:17 -07:00
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2021-04-15 17:03:43 -07:00
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put_dword(&buffer, D3DSIO_END);
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if (!(ret = buffer.status))
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{
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out->code = buffer.data;
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2021-04-15 17:03:46 -07:00
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out->size = buffer.count * sizeof(*buffer.data);
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2021-04-15 17:03:43 -07:00
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}
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return ret;
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}
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int hlsl_emit_dxbc(struct hlsl_ctx *ctx, struct hlsl_ir_function_decl *entry_func, struct vkd3d_shader_code *out)
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2021-03-02 13:34:46 -08:00
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{
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2021-03-28 12:46:55 -07:00
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struct hlsl_ir_var *var;
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2021-03-02 13:34:46 -08:00
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list_move_head(entry_func->body, &ctx->static_initializers);
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2021-03-28 12:46:55 -07:00
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LIST_FOR_EACH_ENTRY(var, &ctx->globals->vars, struct hlsl_ir_var, scope_entry)
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{
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2021-04-15 17:03:44 -07:00
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if (var->data_type->type == HLSL_CLASS_OBJECT)
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list_add_tail(&ctx->extern_vars, &var->extern_entry);
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2021-05-16 10:47:50 -07:00
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else if (var->modifiers & HLSL_STORAGE_UNIFORM)
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2021-03-28 12:46:55 -07:00
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prepend_uniform_copy(ctx, entry_func->body, var);
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}
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LIST_FOR_EACH_ENTRY(var, entry_func->parameters, struct hlsl_ir_var, param_entry)
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{
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2021-04-15 17:03:44 -07:00
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if (var->data_type->type == HLSL_CLASS_OBJECT)
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2021-04-27 10:14:18 -07:00
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{
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2021-04-15 17:03:44 -07:00
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list_add_tail(&ctx->extern_vars, &var->extern_entry);
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2021-04-27 10:14:18 -07:00
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}
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else
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{
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if (var->modifiers & HLSL_STORAGE_UNIFORM)
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{
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prepend_uniform_copy(ctx, entry_func->body, var);
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}
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else
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{
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2021-04-27 10:14:19 -07:00
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if (var->data_type->type != HLSL_CLASS_STRUCT && !var->semantic.name)
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2021-04-27 10:14:18 -07:00
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hlsl_error(ctx, var->loc, VKD3D_SHADER_ERROR_HLSL_MISSING_SEMANTIC,
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"Parameter \"%s\" is missing a semantic.", var->name);
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if (var->modifiers & HLSL_STORAGE_IN)
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prepend_input_var_copy(ctx, entry_func->body, var);
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if (var->modifiers & HLSL_STORAGE_OUT)
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append_output_var_copy(ctx, entry_func->body, var);
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}
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}
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2021-03-28 12:46:55 -07:00
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}
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2021-03-28 12:46:59 -07:00
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if (entry_func->return_var)
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2021-04-27 10:14:18 -07:00
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{
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2021-04-27 10:14:19 -07:00
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if (entry_func->return_var->data_type->type != HLSL_CLASS_STRUCT && !entry_func->return_var->semantic.name)
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2021-04-27 10:14:18 -07:00
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hlsl_error(ctx, entry_func->loc, VKD3D_SHADER_ERROR_HLSL_MISSING_SEMANTIC,
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"Entry point \"%s\" is missing a return value semantic.", entry_func->func->name);
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2021-03-28 12:46:59 -07:00
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append_output_var_copy(ctx, entry_func->body, entry_func->return_var);
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2021-04-27 10:14:18 -07:00
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}
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2021-03-28 12:46:55 -07:00
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2021-03-16 14:31:55 -07:00
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while (transform_ir(ctx, fold_redundant_casts, entry_func->body, NULL));
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2021-03-17 22:22:21 -07:00
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while (transform_ir(ctx, split_struct_copies, entry_func->body, NULL));
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2021-03-16 14:31:53 -07:00
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while (transform_ir(ctx, fold_constants, entry_func->body, NULL));
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2021-03-17 22:22:22 -07:00
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do
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compute_liveness(ctx, entry_func);
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2021-03-16 14:31:54 -07:00
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while (transform_ir(ctx, dce, entry_func->body, NULL));
|
2021-03-16 14:31:53 -07:00
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2021-03-17 22:22:22 -07:00
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compute_liveness(ctx, entry_func);
|
2021-03-02 13:34:46 -08:00
|
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if (TRACE_ON())
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rb_for_each_entry(&ctx->functions, dump_function, NULL);
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|
2021-05-20 22:32:20 -07:00
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allocate_temp_registers(ctx, entry_func);
|
2021-04-08 21:38:26 -07:00
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if (ctx->profile->major_version < 4)
|
2021-04-08 21:38:27 -07:00
|
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allocate_const_registers(ctx, entry_func);
|
2021-04-27 10:14:21 -07:00
|
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allocate_semantic_registers(ctx);
|
2021-04-08 21:38:23 -07:00
|
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|
2021-03-02 13:34:46 -08:00
|
|
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if (ctx->failed)
|
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|
|
return VKD3D_ERROR_INVALID_SHADER;
|
2021-04-15 17:03:43 -07:00
|
|
|
|
|
|
|
if (ctx->profile->major_version < 4)
|
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|
|
return write_sm1_shader(ctx, entry_func, out);
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|
|
|
else
|
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|
|
return VKD3D_ERROR_NOT_IMPLEMENTED;
|
2021-03-02 13:34:46 -08:00
|
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|
}
|