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105 Commits

Author SHA1 Message Date
Giovanni Mascellani
21f76257b0 vkd3d-shader/d3d-asm: Print labels in red. 
They are substantially different from any other register type, so
it makes sense to have them stand out. Also, they help segmenting
visually the code into blocks, because labels are usually found
either at the beginning or at the end of a block.
 2024-03-08 23:36:25 +01:00
Conor McCarthy
f212aad0ff vkd3d-shader/dxil: Support FCMP_ORD and FCMP_UNO for CMP2. 2024-03-08 23:36:13 +01:00
Giovanni Mascellani
9aa86901e3 vkd3d-shader/d3d-asm: Support emitting the shader signature. 2024-03-07 23:08:24 +01:00
Giovanni Mascellani
01a687a7fc vkd3d-shader/d3d-asm: Refactor dumping a write mask to a dedicated function. 2024-03-07 23:08:23 +01:00
Giovanni Mascellani
9d99389663 vkd3d-shader/d3d-asm: Describe the ASM dialect with a bunch of flags instead of a plain enum. 2024-03-07 23:08:22 +01:00
Giovanni Mascellani
94d641783b vkd3d-shader/d3d-asm: Do not make a copy of the buffer before returning it. 2024-03-07 23:08:20 +01:00
Conor McCarthy
625e289574 vkd3d-shader/dxil: Handle hyperbolic trigonometric functions in sm6_parser_emit_dx_unary(). 2024-02-07 22:59:23 +01:00
Conor McCarthy
19d23fa696 vkd3d-shader/dxil: Handle inverse trigonometric functions in sm6_parser_emit_dx_unary(). 2024-02-06 23:09:53 +01:00
Giovanni Mascellani
1f536238a8 vkd3d-shader: Use 64 bit swizzles for 64 bit data types in VSIR. 
The handling of write masks and swizzles for 64 bit data types is
currently irregular: write masks are always 64 bit, while swizzles
are usually 32 bit, except for SSA registers with are 64 bit.
With this change we always use 64 bit swizzles, in order to make
the situation less surprising and make it easier to convert
registers between SSA and TEMP.

64 bit swizzles are always required to have X in their last two
components.
 2024-01-29 22:33:33 +01:00
Conor McCarthy
93d7c30395 vkd3d-shader/dxil: Handle DX intrinsic Tan in sm6_parser_emit_dx_unary(). 2024-01-25 22:24:43 +01:00
Conor McCarthy
8ae69c745b vkd3d-shader/spirv: Handle thread group UAV barriers. 2024-01-25 22:24:23 +01:00
Conor McCarthy
41cce4cbf1 vkd3d-shader/dxil: Handle floating point special value comparisons in sm6_parser_emit_dx_unary(). 2024-01-24 22:37:59 +01:00
Henri Verbeet
23dcd4f22b vkd3d-shader/ir: Store the shader version in struct vsir_program. 2024-01-22 22:18:50 +01:00
Conor McCarthy
efe800f7f0 vkd3d-shader/dxil: Handle the DXIL SWITCH instruction. 2024-01-18 23:15:14 +01:00
Conor McCarthy
ba1ee27b4b vkd3d-shader/dxil: Handle the DXIL PHI instruction. 2024-01-18 23:15:12 +01:00
Conor McCarthy
ffc65215ba vkd3d-shader/ir: Flatten SWITCH/CASE/DEFAULT/ENDSWITCH control flow instructions. 2024-01-17 22:28:36 +01:00
Conor McCarthy
e1dddc01b7 vkd3d-shader/ir: Flatten IF/ELSE/ENDIF control flow instructions. 2024-01-17 22:28:34 +01:00
Giovanni Mascellani
017f86aaaf vkd3d-shader/d3d-asm: Guess a sensible data type for literals. 
When the typing information is not reliable.
 2024-01-11 23:04:34 +01:00
Henri Verbeet
ed4f3f3272 vkd3d-shader/ir: Rename the "immconst_double" field of struct vkd3d_shader_register to "immconst_f64". 2024-01-03 22:37:49 +01:00
Henri Verbeet
05a542ba00 vkd3d-shader/ir: Rename the "immconst_float" field of struct vkd3d_shader_register to "immconst_f32". 2024-01-03 22:37:41 +01:00
Henri Verbeet
e33d3b3954 vkd3d-shader/ir: Rename the "immconst_uint" field of struct vkd3d_shader_register to "immconst_u32". 
For consistency with the rest of vkd3d-shader; e.g. put_u32() and
read_u32().
 2024-01-03 22:37:39 +01:00
Henri Verbeet
8a1de71fb1 vkd3d-shader/ir: Pass a uint32_t swizzle to vkd3d_swizzle_get_component(). 2023-12-14 23:19:49 +01:00
Henri Verbeet
21491d1bbb vkd3d-shader/ir: Pass a uint32_t write mask to vkd3d_write_mask_32_from_64(). 2023-12-13 22:33:07 +01:00
Giovanni Mascellani
1015cc952e vkd3d-shader/d3d-asm: Add an "internal" mode for the ASM dumper. 
The new mode exposes more details about what's going on inside the VSIR
code and it's meant to ease development and debugging.
 2023-12-12 23:16:26 +01:00
Giovanni Mascellani
e7fdf2e97f vkd3d-shader/d3d-asm: Dump unknown types as "<unknown>". 
In analogy with "<continued>" and "<unused>".
 2023-12-12 23:16:24 +01:00
Giovanni Mascellani
1caaf90ee2 vkd3d-shader/d3d-asm: Dump recently added types. 2023-12-12 23:16:23 +01:00
Giovanni Mascellani
4b6e596740 vkd3d-shader/d3d-asm: Write a single type in shader_dump_data_type(). 2023-12-12 23:16:22 +01:00
Giovanni Mascellani
bd50f15d31 vkd3d-shader/d3d-asm: Indent on IFC. 2023-12-12 23:16:21 +01:00
Conor McCarthy
1929432559 vkd3d-shader: Introduce an instruction flag to suppress masking of bitwise shift counts. 
DXIL does not use implicit masking of shift counts.
 2023-12-12 22:50:46 +01:00
Conor McCarthy
a0f5d70792 vkd3d-shader/dxil: Support global variable initialisers. 2023-11-22 22:07:57 +01:00
Conor McCarthy
85d5f83fb7 vkd3d-shader/dxil: Implement default address space global variables. 2023-11-22 22:07:54 +01:00
Conor McCarthy
22960753e9 vkd3d-shader/spirv: Introduce orderedness to comparison instructions. 2023-11-10 20:23:51 +01:00
Conor McCarthy
58ffb5d181 vkd3d-shader/spirv: Introduce integer width cast instructions. 
ITOI and UTOU may cast from a bool to a 32-bit integer. Cast to a 64-bit
integer from a smaller type will be added later.
 2023-11-09 21:14:32 +01:00
Conor McCarthy
acbc80cba2 vkd3d-shader/spirv: Introduce an IDIV instruction. 2023-11-06 23:09:00 +01:00
Conor McCarthy
c8d3515d8b vkd3d-shader/spirv: Introduce an FREM instruction. 2023-11-06 23:08:58 +01:00
Giovanni Mascellani
0d4aebd2e7 vkd3d-shader: Explicitly cast vkd3d_shader_global_flags to uint64_t. 
On macOS vkd3d_shader_global_flags has underlying type unsigned long,
while uint64_t is defined as unsigned long long. This difference
causes a few warnings to be raised.
 2023-11-06 23:08:37 +01:00
Giovanni Mascellani
2ba8c5771c vkd3d-shader: Deduplicate profile version comparison functions. 2023-11-02 18:22:35 +01:00
Conor McCarthy
1e5f91b371 vkd3d-shader: Emit IR CBV declaration sizes in bytes. 
DXIL declares CBV sizes in bytes and they are not aligned to 16 bytes.
 2023-10-19 23:07:43 +02:00
Conor McCarthy
a4ed06bc5b vkd3d-shader/d3d-asm: Recognise the 'rasteriser ordered view' UAV flag. 2023-10-18 20:58:27 +02:00
Conor McCarthy
06f8a88466 vkd3d-shader: Define more global flags. 2023-10-17 22:18:23 +02:00
Conor McCarthy
df4e1b7393 vkd3d-shader/dxil: Read immediate constant arrays. 2023-10-11 22:21:19 +02:00
Zebediah Figura
2bcd6ea893 vkd3d-shader: Introduce a separate register type for combined samplers. 2023-10-09 21:58:38 +02:00
Henri Verbeet
98d158d004 vkd3d-shader/tpf: Get rid of the output map. 
Map output registers in the backend instead, as needed.
 2023-10-09 21:57:46 +02:00
Francisco Casas
123e399b89 vkd3d-shader/d3d-asm: Don't print offset for DEPTHOUT registers. 
This register is unique and thus is not accompanied with an offset in
the native disassembler output.
 2023-09-27 22:34:48 +02:00
Francisco Casas
ef1567c17b vkd3d-shader/d3d-asm: Use vkd3d_shader_register.dimension to know when to dump writemask. 
This change ensures that we don't dump the writemask for registers that
have a scalar dimension.

For instance, for this shader:

    float r;

    float4 main(out float d : DEPTH) : sv_target
    {
        d = r;
        return 0;
    }

we now correctly dump

    dcl_output oDepth

instead of

    dcl_output oDepth.x
 2023-09-27 22:34:47 +02:00
Francisco Casas
a358722f71 vkd3d-shader/d3d-asm: Use vkd3d_shader_register.dimension to know when to dump swizzle. 
The assumption that sampler registers never have a swizzle is not
totally correct.

For instance, for the following shader:

    Texture2D tex;
    sampler sam;

    float4 main() : sv_target
    {
        return tex.GatherGreen(sam, float2(0, 0));
    }

the gather instruction is being disassembled as

  gather4_indexable(texture2d) o0.xyzw, l(0.0, 0.0, 0.0, 0.0), t0.xyzw, s0

instead of

  gather4_indexable(texture2d)(float,float,float,float) o0.xyzw, l(0.0, 0.0, 0.0, 0.0), t0.xyzw, s0.y

(notice the missing swizzle in the last parameter s0).

This is because the Gather instructions give the sampler register a vec4
dimension (and scalar swizzle type) to indicate the channel for the
gather operation.

The solution is using the new vkd3d_shader_register.dimension instead of
checking the swizzle type.
 2023-09-27 22:34:46 +02:00
Francisco Casas
e904660497 vkd3d-shader: Turn vkd3d_shader_register.immconst_type into vkd3d_shader_register.dimension. 2023-09-26 22:07:04 +02:00
Conor McCarthy
3249723972 vkd3d-shader/spirv: Introduce a Static Single Assignment register type. 2023-09-25 22:07:04 +02:00
Conor McCarthy
a67a85989f vkd3d-shader/d3d-asm: Trace undefined registers. 2023-09-25 22:07:02 +02:00
Giovanni Mascellani
603170106c vkd3d-shader/ir: Validate destination parameters. 2023-09-22 11:06:17 +02:00
Nikolay Sivov
45541dd9b2 vkd3d-shader/asm: Tweak TEXCOORD declaration name. 
Signed-off-by: Nikolay Sivov <nsivov@codeweavers.com>
 2023-09-13 23:11:16 +02:00
Nikolay Sivov
69f32796b0 vkd3d-shader: Unify static string arrays initialization pattern. 2023-06-28 21:40:21 +02:00
Nikolay Sivov
ccad49d486 vkd3d-shader/d3d-asm: Fix 3D sampler declaration instruction name. 2023-06-05 22:27:33 +02:00
Nikolay Sivov
44a90f5d41 vkd3d-shader: Fix dcl_uav_typed_* formatting. 
Signed-off-by: Nikolay Sivov <nsivov@codeweavers.com>
 2023-05-22 22:03:24 +02:00
Henri Verbeet
3f8aa0e272 vkd3d-shader/d3d-asm: Rename trace.c to d3d_asm.c. 2023-05-02 20:45:33 +02:00