The condition in d3d12_resource_is_cpu_accessible() is going to be
changed in the following commits.
Signed-off-by: Józef Kucia <jkucia@codeweavers.com>
Signed-off-by: Henri Verbeet <hverbeet@codeweavers.com>
Signed-off-by: Alexandre Julliard <julliard@winehq.org>
In Vulkan both behaviors are allowed.
Signed-off-by: Józef Kucia <jkucia@codeweavers.com>
Signed-off-by: Henri Verbeet <hverbeet@codeweavers.com>
Signed-off-by: Alexandre Julliard <julliard@winehq.org>
The Vulkan spec says:
"Conditional rendering must also either begin and end inside the same
subpass of a render pass instance, or must both begin and end outside
of a render pass instance (i.e. contain entire render pass instances)."
Signed-off-by: Józef Kucia <jkucia@codeweavers.com>
Signed-off-by: Henri Verbeet <hverbeet@codeweavers.com>
Signed-off-by: Alexandre Julliard <julliard@winehq.org>
Fixes crashes, Vulkan and Direct3D validation errors.
* Fix state transitions.
* Use a multisample texture with ResolveSubresource().
Signed-off-by: Józef Kucia <jkucia@codeweavers.com>
Signed-off-by: Henri Verbeet <hverbeet@codeweavers.com>
Signed-off-by: Alexandre Julliard <julliard@winehq.org>
This fixes a regression introduced by commit
91820630cb.
We need to take into account the combined write mask returned from
needs_private_io_variable().
Signed-off-by: Józef Kucia <jkucia@codeweavers.com>
Signed-off-by: Henri Verbeet <hverbeet@codeweavers.com>
Signed-off-by: Alexandre Julliard <julliard@winehq.org>
Predicate arguments which are only non-zero in bit 32 or higher are not
supported. Predicates will not be applied to clear and copy commands because
Vulkan does not support predication of these command classes.
Signed-off-by: Conor McCarthy <cmccarthy@codeweavers.com>
Signed-off-by: Henri Verbeet <hverbeet@codeweavers.com>
Signed-off-by: Alexandre Julliard <julliard@winehq.org>
This might delay updating a d3d12_fence when a fence enqueued later than
other fences is signaled before them. On the other hand, it
significantly reduces CPU usage. I haven't found a program negatively
impacted by this change so far.
Signed-off-by: Józef Kucia <jkucia@codeweavers.com>
Signed-off-by: Henri Verbeet <hverbeet@codeweavers.com>
Signed-off-by: Alexandre Julliard <julliard@winehq.org>
We maintain separate arrays for enqueued fences and fences owned by the
fence worker thread.
Signed-off-by: Józef Kucia <jkucia@codeweavers.com>
Signed-off-by: Henri Verbeet <hverbeet@codeweavers.com>
Signed-off-by: Alexandre Julliard <julliard@winehq.org>
The debug log level is demoted to WARN after the FIXME is printed once.
Signed-off-by: Józef Kucia <jkucia@codeweavers.com>
Signed-off-by: Henri Verbeet <hverbeet@codeweavers.com>
Signed-off-by: Alexandre Julliard <julliard@winehq.org>
It isn't immediately obvious what "1u << graphics->rt_count" means.
Use dsv_attachment_mask() helper instead.
Signed-off-by: Józef Kucia <jkucia@codeweavers.com>
Signed-off-by: Henri Verbeet <hverbeet@codeweavers.com>
Signed-off-by: Alexandre Julliard <julliard@winehq.org>
On radv with AMD Polaris GPUs, the alignment may be as high as 0x20000
or 0x40000. World of Warcraft seems to ignore the alignment returned
from GetResourceAllocationInfo(), and simply aligns to 0x10000
(D3D12_DEFAULT_RESOURCE_PLACEMENT_ALIGNMENT).
Signed-off-by: Józef Kucia <jkucia@codeweavers.com>
Signed-off-by: Henri Verbeet <hverbeet@codeweavers.com>
Signed-off-by: Alexandre Julliard <julliard@winehq.org>
We use transfer operations instead of unordered access.
Signed-off-by: Józef Kucia <jkucia@codeweavers.com>
Signed-off-by: Henri Verbeet <hverbeet@codeweavers.com>
Signed-off-by: Alexandre Julliard <julliard@winehq.org>
With plane slice and component mapping.
Signed-off-by: Józef Kucia <jkucia@codeweavers.com>
Signed-off-by: Henri Verbeet <hverbeet@codeweavers.com>
Signed-off-by: Alexandre Julliard <julliard@winehq.org>
