728 Commits

Author SHA1 Message Date
Giovanni Mascellani
7f9803620f vkd3d-shader/spirv: Specify behavior for bit field instructions.
Bit field instructions in SPIR-V do not specify what happens when
offset + count exceeds the type bit width. After this commit we
refine the emitted code's behavior to match TPF.

This fixes a few failures on MoltenVK.
2024-01-08 21:44:52 +01:00
Henri Verbeet
60842b7181 vkd3d-shader/ir: Store source parameter swizzles as a uint32_t. 2024-01-04 22:23:51 +01:00
Henri Verbeet
9f4ca3bc9c vkd3d-shader/ir: Store instruction flags as a uint32_t. 2024-01-04 22:23:49 +01:00
Henri Verbeet
7f94fda05c vkd3d-shader/ir: Rename the "immconst_uint64" field of struct vkd3d_shader_register to "immconst_u64". 2024-01-03 22:37:43 +01:00
Henri Verbeet
e33d3b3954 vkd3d-shader/ir: Rename the "immconst_uint" field of struct vkd3d_shader_register to "immconst_u32".
For consistency with the rest of vkd3d-shader; e.g. put_u32() and
read_u32().
2024-01-03 22:37:39 +01:00
Conor McCarthy
78343dcf87 vkd3d-shader/spirv: Decorate non-float32 non-built-in pixel shader inputs as Flat.
As per VUID-StandaloneSpirv-Flat-04744. Not strictly a regression, but
revealed by 66cb2815f because it declares unused inputs.
2024-01-02 23:03:59 +01:00
Conor McCarthy
812f01c2e2 vkd3d-shader/spirv: Handle ITOI and UTOU in spirv_compiler_map_alu_instruction().
These instructions perform integer casts to/from 64 bits.
2024-01-02 23:03:07 +01:00
Conor McCarthy
1eaa7d1dbe vkd3d-shader/spirv: Support UINT64 source in spirv_compiler_emit_bool_cast(). 2024-01-02 23:03:06 +01:00
Conor McCarthy
99924d913b vkd3d-shader/spirv: Support 64-bit sources in spirv_compiler_emit_int_div(). 2024-01-02 23:03:05 +01:00
Conor McCarthy
13459a55f1 vkd3d-shader/spirv: Introduce a UINT64 component type. 2024-01-02 23:03:04 +01:00
Conor McCarthy
fe44873979 vkd3d-shader/spirv: Introduce a data_type_is_64_bit() helper function. 2024-01-02 23:03:03 +01:00
Conor McCarthy
511c66d595 vkd3d-shader/spirv: Use data_type_is_integer() in spirv_compiler_emit_neg(). 2024-01-02 23:03:02 +01:00
Henri Verbeet
f96a791807 vkd3d-shader/ir: Pass a uint32_t swizzle to vkd3d_swizzle_get_component64(). 2023-12-14 23:19:51 +01:00
Henri Verbeet
8a1de71fb1 vkd3d-shader/ir: Pass a uint32_t swizzle to vkd3d_swizzle_get_component(). 2023-12-14 23:19:49 +01:00
Henri Verbeet
21491d1bbb vkd3d-shader/ir: Pass a uint32_t write mask to vkd3d_write_mask_32_from_64(). 2023-12-13 22:33:07 +01:00
Henri Verbeet
713adaa56a vkd3d-shader/ir: Pass a uint32_t write mask to vkd3d_write_mask_component_count(). 2023-12-13 22:33:04 +01:00
Henri Verbeet
e1aa12f94b vkd3d-shader/ir: Pass a uint32_t write mask to vkd3d_write_mask_get_component_idx(). 2023-12-13 22:33:03 +01:00
Giovanni Mascellani
ec4986e9e2 vkd3d-shader/spirv: Honor force_validation after emitting SPIR-V code. 2023-12-13 22:32:25 +01:00
Conor McCarthy
cdb9eecfd1 vkd3d-shader/spirv: Introduce a compiler feature flag for int64 capability. 2023-12-12 22:50:53 +01:00
Conor McCarthy
0610867334 vkd3d-shader/spirv: Emit an error if 64-bit integers are used. 2023-12-12 22:50:48 +01:00
Conor McCarthy
1929432559 vkd3d-shader: Introduce an instruction flag to suppress masking of bitwise shift counts.
DXIL does not use implicit masking of shift counts.
2023-12-12 22:50:46 +01:00
Conor McCarthy
2037daae32 vkd3d-shader/spirv: Bitcast if necessary in the spirv_compiler_emit_mov() general implementation.
In SM 6, this is needed when storing an asfloat() or asuint() result in
an indexable temp, because dxc performs the bitcast by casting the
destination pointer.
2023-12-11 23:18:52 +01:00
Zebediah Figura
66cb2815f0 vkd3d-shader/spirv: Declare I/O registers from the signature.
Instead of parsing DCL instructions.

This allows sm1 to work without further effort, and simplifies sm6 code.
2023-12-11 23:18:44 +01:00
Zebediah Figura
8876030590 vkd3d-shader/spirv: Do not use the output_info array for patch constants. 2023-12-11 23:18:40 +01:00
Conor McCarthy
cb88844a3d vkd3d-shader: Add a register index to struct vkd3d_shader_immediate_constant_buffer. 2023-12-07 21:56:47 +01:00