Commit Graph

108 Commits

Author SHA1 Message Date
21491d1bbb vkd3d-shader/ir: Pass a uint32_t write mask to vkd3d_write_mask_32_from_64(). 2023-12-13 22:33:07 +01:00
1015cc952e vkd3d-shader/d3d-asm: Add an "internal" mode for the ASM dumper.
The new mode exposes more details about what's going on inside the VSIR
code and it's meant to ease development and debugging.
2023-12-12 23:16:26 +01:00
e7fdf2e97f vkd3d-shader/d3d-asm: Dump unknown types as "<unknown>".
In analogy with "<continued>" and "<unused>".
2023-12-12 23:16:24 +01:00
1caaf90ee2 vkd3d-shader/d3d-asm: Dump recently added types. 2023-12-12 23:16:23 +01:00
4b6e596740 vkd3d-shader/d3d-asm: Write a single type in shader_dump_data_type(). 2023-12-12 23:16:22 +01:00
bd50f15d31 vkd3d-shader/d3d-asm: Indent on IFC. 2023-12-12 23:16:21 +01:00
1929432559 vkd3d-shader: Introduce an instruction flag to suppress masking of bitwise shift counts.
DXIL does not use implicit masking of shift counts.
2023-12-12 22:50:46 +01:00
a0f5d70792 vkd3d-shader/dxil: Support global variable initialisers. 2023-11-22 22:07:57 +01:00
85d5f83fb7 vkd3d-shader/dxil: Implement default address space global variables. 2023-11-22 22:07:54 +01:00
22960753e9 vkd3d-shader/spirv: Introduce orderedness to comparison instructions. 2023-11-10 20:23:51 +01:00
58ffb5d181 vkd3d-shader/spirv: Introduce integer width cast instructions.
ITOI and UTOU may cast from a bool to a 32-bit integer. Cast to a 64-bit
integer from a smaller type will be added later.
2023-11-09 21:14:32 +01:00
acbc80cba2 vkd3d-shader/spirv: Introduce an IDIV instruction. 2023-11-06 23:09:00 +01:00
c8d3515d8b vkd3d-shader/spirv: Introduce an FREM instruction. 2023-11-06 23:08:58 +01:00
0d4aebd2e7 vkd3d-shader: Explicitly cast vkd3d_shader_global_flags to uint64_t.
On macOS vkd3d_shader_global_flags has underlying type unsigned long,
while uint64_t is defined as unsigned long long. This difference
causes a few warnings to be raised.
2023-11-06 23:08:37 +01:00
2ba8c5771c vkd3d-shader: Deduplicate profile version comparison functions. 2023-11-02 18:22:35 +01:00
1e5f91b371 vkd3d-shader: Emit IR CBV declaration sizes in bytes.
DXIL declares CBV sizes in bytes and they are not aligned to 16 bytes.
2023-10-19 23:07:43 +02:00
a4ed06bc5b vkd3d-shader/d3d-asm: Recognise the 'rasteriser ordered view' UAV flag. 2023-10-18 20:58:27 +02:00
06f8a88466 vkd3d-shader: Define more global flags. 2023-10-17 22:18:23 +02:00
df4e1b7393 vkd3d-shader/dxil: Read immediate constant arrays. 2023-10-11 22:21:19 +02:00
2bcd6ea893 vkd3d-shader: Introduce a separate register type for combined samplers. 2023-10-09 21:58:38 +02:00
98d158d004 vkd3d-shader/tpf: Get rid of the output map.
Map output registers in the backend instead, as needed.
2023-10-09 21:57:46 +02:00
123e399b89 vkd3d-shader/d3d-asm: Don't print offset for DEPTHOUT registers.
This register is unique and thus is not accompanied with an offset in
the native disassembler output.
2023-09-27 22:34:48 +02:00
ef1567c17b vkd3d-shader/d3d-asm: Use vkd3d_shader_register.dimension to know when to dump writemask.
This change ensures that we don't dump the writemask for registers that
have a scalar dimension.

For instance, for this shader:

    float r;

    float4 main(out float d : DEPTH) : sv_target
    {
        d = r;
        return 0;
    }

we now correctly dump

    dcl_output oDepth

instead of

    dcl_output oDepth.x
2023-09-27 22:34:47 +02:00
a358722f71 vkd3d-shader/d3d-asm: Use vkd3d_shader_register.dimension to know when to dump swizzle.
The assumption that sampler registers never have a swizzle is not
totally correct.

For instance, for the following shader:

    Texture2D tex;
    sampler sam;

    float4 main() : sv_target
    {
        return tex.GatherGreen(sam, float2(0, 0));
    }

the gather instruction is being disassembled as

  gather4_indexable(texture2d) o0.xyzw, l(0.0, 0.0, 0.0, 0.0), t0.xyzw, s0

instead of

  gather4_indexable(texture2d)(float,float,float,float) o0.xyzw, l(0.0, 0.0, 0.0, 0.0), t0.xyzw, s0.y

(notice the missing swizzle in the last parameter s0).

This is because the Gather instructions give the sampler register a vec4
dimension (and scalar swizzle type) to indicate the channel for the
gather operation.

The solution is using the new vkd3d_shader_register.dimension instead of
checking the swizzle type.
2023-09-27 22:34:46 +02:00
e904660497 vkd3d-shader: Turn vkd3d_shader_register.immconst_type into vkd3d_shader_register.dimension. 2023-09-26 22:07:04 +02:00