46 Commits

Author SHA1 Message Date
Zebediah Figura
852eefc01d vkd3d-shader/ir: Synthesize HS inputs with the register index and write mask of the signature element.
This pass was written as if to output normalized I/O, but it runs before the I/O
normalization pass.

Fixes: 98b5e2c6e01199d714d18fccfe54826a680aecbf
2023-11-07 22:26:53 +01:00
Zebediah Figura
12240efa79 vkd3d-shader/spirv: Use register counts from the signature and shader desc. 2023-11-07 22:26:49 +01:00
Giovanni Mascellani
7d49f9637a vkd3d-shader/ir: Check that SWITCH blocks are correctly nested. 2023-11-07 22:26:05 +01:00
Giovanni Mascellani
93632fb407 vkd3d-shader/ir: Check that REP blocks are correctly nested. 2023-11-07 22:26:04 +01:00
Giovanni Mascellani
92c36615ed vkd3d-shader/ir: Check that LOOP blocks are correctly nested. 2023-11-07 22:26:03 +01:00
Giovanni Mascellani
2f7d52dba4 vkd3d-shader/ir: Check that IF blocks are correctly nested. 2023-11-07 22:26:01 +01:00
Giovanni Mascellani
0a7e200f89 vkd3d-shader/ir: Do not enfore DCL_TEMPS count for hull shaders.
Hull shaders have a different temps count for each phase, and the
parser only reports the count for the patch constant phase.
In order to properly check for temps count on hull shaders, we first
need to decode its phases.
2023-11-07 22:26:00 +01:00
Giovanni Mascellani
ca3f594ae3 vkd3d-shader/ir: Emit an ERR() on validation errors. 2023-11-07 22:25:58 +01:00
Zebediah Figura
b73d2c978d vkd3d-shader/ir: Check for vocp usage during IR normalization.
The hull shader barrier used for this was broken by I/O normalization, since
vocp is no longer exposed to the spirv backend.

Restore this barrier by checking for vocp during normalization instead.
2023-11-06 23:07:56 +01:00
Zebediah Figura
8b42f523f2 vkd3d-shader/ir: Pass a vkd3d_shader_parser to instruction_array_normalise_io_registers(). 2023-11-06 23:07:54 +01:00
Giovanni Mascellani
af72466db1 vkd3d-shader/ir: Validate the index of a TEMP register. 2023-11-02 18:22:52 +01:00
Giovanni Mascellani
4140b87499 vkd3d-shader/ir: Validate the DCL_TEMPS instruction. 2023-11-02 18:22:50 +01:00
Giovanni Mascellani
79fa5fd8bb vkd3d-shader/ir: Validate the register index count. 2023-11-02 18:22:49 +01:00
Giovanni Mascellani
26e4191d4b vkd3d-shader/ir: Validate the register dimension. 2023-11-02 18:22:47 +01:00
Giovanni Mascellani
f3a20be35a vkd3d-shader/ir: Validate the register data type. 2023-11-02 18:22:38 +01:00
Giovanni Mascellani
72d0f765f2 vkd3d-shader/ir: Validate the register precision. 2023-11-02 18:22:37 +01:00
Zebediah Figura
15b69721de vkd3d-shader/tpf: Set the interpolation mode for signature elements. 2023-10-31 21:59:38 +01:00
Zebediah Figura
6a942581db vkd3d-shader/ir: Translate TEX instructions to SAMPLE. 2023-10-09 21:58:40 +02:00
Francisco Casas
e904660497 vkd3d-shader: Turn vkd3d_shader_register.immconst_type into vkd3d_shader_register.dimension. 2023-09-26 22:07:04 +02:00
Francisco Casas
5d6899888d vkd3d-shader: Rename shader_register_init() to vsir_register_init(). 2023-09-26 22:06:50 +02:00
Giovanni Mascellani
d9c8b49ea0 vkd3d-shader/ir: Remove dead code during normalisation.
The SPIR-V backend generates invalid SPIR-V code when
VSIR has dead code (except for NOPs).
2023-09-25 22:07:27 +02:00
Giovanni Mascellani
34b1c0fe5d vkd3d-shader/ir: Validate source parameters. 2023-09-22 11:06:18 +02:00
Giovanni Mascellani
603170106c vkd3d-shader/ir: Validate destination parameters. 2023-09-22 11:06:17 +02:00
Giovanni Mascellani
585e60ad3b vkd3d-shader/ir: Validate register types. 2023-09-22 11:06:16 +02:00
Giovanni Mascellani
b09cfbda90 vkd3d-shader/ir: Validate instruction handlers. 2023-09-22 11:06:15 +02:00