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874ca85a95
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304 Commits

Author SHA1 Message Date
Francisco Casas
874ca85a95 vkd3d-shader/hlsl: Store SM4 stores in the vsir program. 2024-11-21 19:28:46 +01:00
Francisco Casas
5dedcff665 vkd3d-shader/tpf: Remove HLSL_IR_SWIZZLE handling. 2024-11-21 19:28:46 +01:00
Francisco Casas
5df836c513 vkd3d-shader/hlsl: Store SM4 MOD in the vsir program. 2024-11-06 22:49:12 +01:00
Francisco Casas
30bc6965a2 vkd3d-shader/hlsl: Store SM4 DOT in the vsir program. 2024-11-06 22:48:13 +01:00
Francisco Casas
e8b373e3ff vkd3d-shader/hlsl: Store SM4 DIV in the vsir program. 2024-11-06 22:47:42 +01:00
Francisco Casas
24f4308982 vkd3d-shader/hlsl: Store SM4 MUL in the vsir program. 2024-11-06 22:45:46 +01:00
Francisco Casas
e4d36bd855 vkd3d-shader/hlsl: Store SM4 SAT in the vsir program. 2024-11-06 22:45:23 +01:00
Francisco Casas
2e3f4a01bf vkd3d-shader/hlsl: Store SM4 RCP in the vsir program. 2024-11-06 22:40:50 +01:00
Francisco Casas
3c4889add3 vkd3d-shader/hlsl: Store SM4 SIN and COS in the vsir program. 2024-11-06 22:38:04 +01:00
Francisco Casas
befba8e813 vkd3d-shader/hlsl: Store SM4 casts in the vsir program. 2024-11-06 22:27:49 +01:00
Nikolay Sivov
e5ba79b4f1 vkd3d-shader/hlsl: Implement the ByteAddressBuffer.Load*() methods. 
Signed-off-by: Nikolay Sivov <nsivov@codeweavers.com>
 2024-11-06 22:09:23 +01:00
Francisco Casas
90a07ada8e vkd3d-shader/tpf: Use SCALAR swizzle dimension for RASTERIZER registers. 
While we currently output instructions like this:

    sampleinfo_uint r0.x, rasterizer.xxxx

    > SAMPLE_INFO (111)
    0  0000100[len:4]  0000000000001[1]  00001101111[opcode:111]
    └─ 0  000[d3i:0]  000[d2i:0]  000[d1i:0]  01[idxs:1]  00000000[type:0]  0000[0]  0001[wmask:1]  00[swtype:0]  10[dim:2]
       └─ 00000000000000000000000000000000[0|0.0]
    └─ 0  000[d3i:0]  000[d2i:0]  000[d1i:0]  00[idxs:0]  00001110[type:14]  00000000[sw:0]  01[swtype:1]  10[dim:2]

FXC/d3dcompiler outputs instructions like this:

    sampleinfo o0.x, rasterizer.x

    > SAMPLE_INFO (111)
    0  0000100[len:4]  0000000000000[0]  00001101111[opcode:111]
    └─ 0  000[d3i:0]  000[d2i:0]  000[d1i:0]  01[idxs:1]  00000010[type:2]  0000[0]  0001[wmask:1]  00[swtype:0]  10[dim:2]
       └─ 00000000000000000000000000000000[0|0.0]
    └─ 0  000[d3i:0]  000[d2i:0]  000[d1i:0]  00[idxs:0]  00001110[type:14]  000000[0]  00[swcomp:0]  10[swtype:2]  10[dim:2]

Note the difference in swtype of the rasterizer src register.
 2024-11-05 19:50:55 +01:00
Francisco Casas
950c381728 vkd3d-shader/hlsl: Store RASTERIZER_SAMPLE_COUNT in the vsir program. 
Also, the profile check for GetRenderTargetSampleCount() is moved to
parse time.
 2024-11-05 19:48:31 +01:00
Francisco Casas
ab60f4e082 vkd3d-shader/hlsl: Store simple SM4 expressions in the vsir program. 2024-11-05 19:35:52 +01:00
Francisco Casas
b4608e99e3 vkd3d-shader/tpf: Remove HLSL IR ABS handling. 2024-11-05 19:20:21 +01:00
Shaun Ren
64c4a3a442 vkd3d-shader/hlsl: Store SM4 semantic declarations in the vsir program. 2024-11-05 19:19:22 +01:00
Francisco Casas
6f52bb6b1a vkd3d-shader/hlsl: Store SM4 swizzles in the vsir program. 2024-11-04 16:08:38 +01:00
Francisco Casas
2083d505c7 vkd3d-shader/tpf: Use instr.extra_bits for IF. 2024-11-04 15:37:46 +01:00
Nikolay Sivov
89e5912fd2 vkd3d-shader/hlsl: Implement RWByteAddressBuffer.Store*() methods. 
Signed-off-by: Nikolay Sivov <nsivov@codeweavers.com>
 2024-10-28 17:51:04 +01:00
Nikolay Sivov
5eff8bf918 vkd3d-shader/hlsl: Handle SV_GroupIndex. 
Signed-off-by: Nikolay Sivov <nsivov@codeweavers.com>
 2024-10-24 20:54:04 +02:00
Francisco Casas
23be6ed0dd vkd3d-shader/hlsl: Store temp declarations in the vsir program. 
Move the temp allocation back to hlsl_codegen.c.

Note that the DCL_TEMPS instructions wouldn't be necessary if we had the
capacity to store the temp_count for both the main program and the patch
constant program (or more generally speaking, a temp_count for all
phases).

The plan is to eventually also move the HS_CONTROL_POINT and
HS_FORK_PHASE markers to the vsir_program, making it able to contain
both functions.
 2024-10-24 20:50:59 +02:00
Francisco Casas
cf7fade580 vkd3d-shader/hlsl: Store the thread group size in the vsir program. 2024-10-24 20:48:20 +02:00
Elizabeth Figura
32e6a1bb4d vkd3d-shader: Validate the parsed shader in vsir_parse(). 2024-10-23 16:02:09 +02:00
Henri Verbeet
1113d24a70 vkd3d-shader/ir: Store the global flags in struct vsir_program. 2024-10-22 20:40:31 +02:00
Nikolay Sivov
cf3e251a9f vkd3d-shader/hlsl: Implement the f32tof16() intrinsic. 
Signed-off-by: Nikolay Sivov <nsivov@codeweavers.com>
 2024-10-22 20:28:33 +02:00
Francisco Casas
2a8c1b2823 vkd3d-shader/hlsl: Sort signature elements by register id. 2024-10-22 20:25:40 +02:00
Francisco Casas
7fd6c29ee8 vkd3d-shader/hlsl: Allow accounting for interpolation mode when allocating semantics. 
For now this has no effect since semantics are allocated with reg_size
4, but will have effect when optimizing interstage signatures.
 2024-10-22 20:03:39 +02:00
Nikolay Sivov
fb2b974466 vkd3d-shader/hlsl: Handle snorm/unorm types as resource formats. 
Signed-off-by: Nikolay Sivov <nsivov@codeweavers.com>
 2024-10-22 19:14:51 +02:00
Giovanni Mascellani
ed4d45355a vkd3d-shader/ir: Represent the normalisation level with an enumeration. 2024-10-21 18:21:39 +02:00
Shaun Ren
abed6d9cb7 vkd3d-shader/tpf: Implement semantics for domain shaders. 2024-10-21 18:18:25 +02:00
Shaun Ren
0273ff007b vkd3d-shader/tpf: Write domain shader declarations. 2024-10-21 18:18:00 +02:00
Shaun Ren
26efba30b4 vkd3d-shader/tpf: Use vpc input registers for domain shaders. 2024-10-21 18:17:06 +02:00
Shaun Ren
2b897296a1 vkd3d-shader/tpf: Write the input signature of domain shaders as PCSG. 2024-10-21 18:16:50 +02:00
Giovanni Mascellani
eba8fd4720 vkd3d-shader: Keep track of whether programs have normalised I/O. 2024-10-17 17:34:55 +02:00
Shaun Ren
1ed5f1a4d0 vkd3d-shader/tpf: Write the patch constant function in hull shaders. 
We use a single hs_fork_phase here for the patch constant function.
 2024-10-16 21:40:40 +02:00
Shaun Ren
ae2d86b99c vkd3d-shader/tpf: Determine SIV from SV and index in write_sm4_dcl_semantic(). 2024-10-16 21:12:29 +02:00
Shaun Ren
df3aaac7cf vkd3d-shader/tpf: Introduce tpf_write_shader_function(). 2024-10-16 21:12:13 +02:00
Shaun Ren
147f8898ca vkd3d-shader/hlsl: Process the patch constant function in hlsl_emit_bytecode(). 
Also, support patch constant function semantics in sm4_sysval_semantic_from_semantic_name().
 2024-10-16 21:10:24 +02:00
Shaun Ren
cbed70c60f vkd3d-shader/tpf: Implement semantics for hull shaders. 2024-10-16 21:07:53 +02:00
Shaun Ren
beb342ed5f vkd3d-shader/tpf: Write hull shader declarations. 2024-10-16 21:07:53 +02:00
Francisco Casas
7eee877dd4 vkd3d-shader/tpf: Make hlsl_sm4_register_from_semantic() independent of HLSL IR. 2024-10-16 21:07:51 +02:00
Francisco Casas
a243862b8c vkd3d-shader/tpf: Make sysval_semantic_from_hlsl() independent of HLSL IR. 2024-10-16 21:05:10 +02:00
Francisco Casas
7cc8151b81 vkd3d-shader/tpf: Replace uses of ctx->profile with tpf->program->shader_version. 2024-10-16 18:50:15 +02:00
Francisco Casas
c75fbaf94e vkd3d-shader/tpf: Use the I/O signatures from the vsir program in tpf_write_signature(). 2024-10-16 17:40:26 +02:00
Francisco Casas
10442369d8 vkd3d-shader/tpf: Pass a tpf_compiler structure to tpf_compile() callees. 2024-10-16 17:26:47 +02:00
Francisco Casas
16d9a10dd5 vkd3d-shader/tpf: Rename "tpf_writer" to "tpf_compiler". 
Analog to d3dbc_compiler.
 2024-10-16 17:09:15 +02:00
Francisco Casas
5b21cc67f1 vkd3d-shader/hlsl: Split hlsl_sm4_write(). 
Similarly to the already done split from

    HLSL IR -> d3dbc

to

    HLSL IR -> vsir -> d3bc

we now start splitting the

    HLSL IR -> tpf

translation into

    HLSL IR -> vsir -> tpf

So hlsl_sm4_write is split into two functions, sm4_generate_vsir() and
tpf_compile().

This translation should be completed once tpf_compile() no longer needs
the hlsl_ctx and entry_func parameters.
 2024-10-16 17:08:50 +02:00
Francisco Casas
104435df5f vkd3d-shader/tpf: Use dcl_input_ps_sgv for sv_isfrontface. 
As the native compiler does.
 2024-10-15 16:44:38 +02:00
Francisco Casas
ad2f821ff5 vkd3d-shader/tpf: Write sysval semantic consistently. 
Specifically we should write the sysval semantic as an instruction idx
for the following instructions:

    VKD3D_SM4_OP_DCL_INPUT_SGV
    VKD3D_SM4_OP_DCL_INPUT_PS_SGV
    VKD3D_SM4_OP_DCL_INPUT_SIV
    VKD3D_SM4_OP_DCL_INPUT_PS_SIV
    VKD3D_SM4_OP_DCL_OUTPUT_SIV

and not the following ones:

    VKD3D_SM4_OP_DCL_INPUT
    VKD3D_SM4_OP_DCL_PS_INPUT
    VKD3D_SM4_OP_DCL_OUTPUT

Which is consistent with what we do when reading these instructions in
the following functions:

    shader_sm4_read_declaration_register_semantic()
    shader_sm4_read_dcl_input_ps_siv()

and

    shader_sm4_read_dcl_input_ps()
    shader_sm4_read_declaration_dst()

for the non-SGV and non-SIV cases.

Note that the non-SGV and non-SIV instructions don't need/use this
extra information because they rely on the dst register type and index.

I suggest to introduce this change because the here replaced check is
brittle, and we might be omitting the sysval semantic in some cases.
 2024-10-15 16:44:38 +02:00
Shaun Ren
0c5dc53fd2 vkd3d-shader/hlsl: Allocate temporary registers separately for each entry function. 2024-10-15 16:39:50 +02:00