Commit Graph

2440 Commits

Author SHA1 Message Date
edc406d297 vkd3d-shader/ir: Check that SSA registers are used with compatible data types.
Specifically, accesses are always 32 bit or always 64 bit.
2024-01-29 22:33:34 +01:00
1f536238a8 vkd3d-shader: Use 64 bit swizzles for 64 bit data types in VSIR.
The handling of write masks and swizzles for 64 bit data types is
currently irregular: write masks are always 64 bit, while swizzles
are usually 32 bit, except for SSA registers with are 64 bit.
With this change we always use 64 bit swizzles, in order to make
the situation less surprising and make it easier to convert
registers between SSA and TEMP.

64 bit swizzles are always required to have X in their last two
components.
2024-01-29 22:33:33 +01:00
2b93aae069 vkd3d-shader: Convert write masks between 32 and 64 bit by cases.
There are only three cases, and while the code is longer it is also
hopefully easier to read. Moreover, an error message is casted if
we're doing something unexpected.
2024-01-29 22:33:30 +01:00
13f713f74b vkd3d-shader/hlsl: Turn register(cX) reservations into buffer offset for SM4. 2024-01-29 22:33:27 +01:00
c7f7636534 vkd3d-shader/hlsl: Make register(cX) reservations work for SM1. 2024-01-29 22:33:25 +01:00
92f0b37133 vkd3d-shader/spirv: Support 64-bit source value for bitfield instructions. 2024-01-29 22:33:22 +01:00
3bbe374ca8 vkd3d-shader/dxil: Implement DX intrinsic Tertiary.
IBFE and UBFE are not emitted for HLSL sources which perform bitfield
extractions, e.g. loading a value from a struct containing bitfields, or
the equivalent done with bit shifts. These instructions are probably
only emitted by the TPF -> DXIL converter, which makes them hard to test.
2024-01-29 22:33:20 +01:00
026c502f31 vkd3d-shader/ir: Fixup PHI nodes when lowering switches to selection ladders.
A map between the blocks before and after the pass is built and then
used to fix the PHI nodes.
2024-01-29 22:33:17 +01:00
378109051c vkd3d-shader/ir: Lower monolithic switches to selection ladders.
PHI nodes must be fixed up after this pass, because the block references
might have become broken. For simplicitly this is not handled yet.

The goal for this pass is to make the CFG structurizer simpler, because
only conditional and unconditional branches must be supported.
Eventually this limitation might be lifted if there is advantage in
doing so.
2024-01-29 22:33:15 +01:00
b97edee03d vkd3d-shader/spirv: Emit an error if merge information is missing.
Instead of crashing.
2024-01-29 22:33:14 +01:00
e08c0cfc4f vkd3d-shader/dxil: Implement DX intrinsic RawBufferLoad. 2024-01-29 22:33:10 +01:00
1bab93843d vkd3d-shader/dxil: Load raw/structured buffer SRV/UAV descriptors. 2024-01-29 22:33:09 +01:00
fee3b94563 vkd3d-shader: Start an if-block on VKD3DSIH_IFC in vkd3d_shader_scan_instruction(). 2024-01-25 22:24:50 +01:00
f954724870 vkd3d-shader/spirv: Handle the TAN instruction in spirv_compiler_emit_ext_glsl_instruction(). 2024-01-25 22:24:44 +01:00
93d7c30395 vkd3d-shader/dxil: Handle DX intrinsic Tan in sm6_parser_emit_dx_unary(). 2024-01-25 22:24:43 +01:00
2a260b8d56 vkd3d-shader/dxil: Implement DX intrinsics Cos and Sin. 2024-01-25 22:24:41 +01:00
cec45da45b vkd3d-shader/ir: Update flatten_control_flow_constructs() comment. 2024-01-25 22:24:27 +01:00
8ae69c745b vkd3d-shader/spirv: Handle thread group UAV barriers. 2024-01-25 22:24:23 +01:00
18e9148f58 vkd3d-shader/spirv: Include Uniform in the memory semantics for UAV barriers.
The UniformMemory semantic applies the constraints to Uniform storage
class memory, which matches how UAV variables are declared.
2024-01-25 22:24:22 +01:00
adfbecef3c vkd3d-shader/spirv: Handle globally coherent UAVs. 2024-01-25 22:24:20 +01:00
eabcaf15fb vkd3d-shader/ir: Use vsir_instruction_is_dcl() in vsir_validate_instruction(). 2024-01-24 22:38:36 +01:00
365ad56888 vkd3d-shader/ir: Get rid of shader_instruction_is_dcl(). 2024-01-24 22:38:34 +01:00
54f6e6dd67 vkd3d-shader/spirv: Check for FEATURE_FLOAT64 when double precision use is flagged. 2024-01-24 22:38:09 +01:00
e973271a40 vkd3d-shader/spirv: Handle the ISINF and ISNAN instructions in spirv_compiler_emit_alu_instruction(). 2024-01-24 22:38:04 +01:00
cd674d593e vkd3d-shader/spirv: Implement the ISFINITE instruction. 2024-01-24 22:38:03 +01:00