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vkd3d-shader/dxil: Implement DX intrinsic Tertiary.

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IBFE and UBFE are not emitted for HLSL sources which perform bitfield
extractions, e.g. loading a value from a struct containing bitfields, or
the equivalent done with bit shifts. These instructions are probably
only emitted by the TPF -> DXIL converter, which makes them hard to test.
This commit is contained in:
Conor McCarthy 2024-01-23 12:32:39 +10:00 committed by Alexandre Julliard
parent 026c502f31
commit 3bbe374ca8
Notes: Alexandre Julliard 2024-01-29 22:51:22 +01:00 
Approved-by: Giovanni Mascellani (@giomasce)
Approved-by: Henri Verbeet (@hverbeet)
Approved-by: Alexandre Julliard (@julliard)
Merge-Request: https://gitlab.winehq.org/wine/vkd3d/-/merge_requests/587
1 changed files with 32 additions and 0 deletions
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32
libs/vkd3d-shader/dxil.c
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@ -354,6 +354,8 @@ enum dx_intrinsic_opcode
DX_IMIN = 38,
DX_UMAX = 39,
DX_UMIN = 40,
DX_IBFE = 51,
DX_UBFE = 52,
DX_CREATE_HANDLE = 57,
DX_CBUFFER_LOAD_LEGACY = 59,
DX_BUFFER_LOAD = 68,
@ -3701,6 +3703,34 @@ static void sm6_parser_emit_dx_create_handle(struct sm6_parser *sm6, enum dx_int
ins->handler_idx = VKD3DSIH_NOP;
}
static enum vkd3d_shader_opcode sm6_dx_map_tertiary_op(enum dx_intrinsic_opcode op)
{
switch (op)
{
case DX_IBFE:
return VKD3DSIH_IBFE;
case DX_UBFE:
return VKD3DSIH_UBFE;
default:
vkd3d_unreachable();
}
}
static void sm6_parser_emit_dx_tertiary(struct sm6_parser *sm6, enum dx_intrinsic_opcode op,
const struct sm6_value **operands, struct function_emission_state *state)
{
struct vkd3d_shader_instruction *ins = state->ins;
struct vkd3d_shader_src_param *src_params;
unsigned int i;
vsir_instruction_init(ins, &sm6->p.location, sm6_dx_map_tertiary_op(op));
src_params = instruction_src_params_alloc(ins, 3, sm6);
for (i = 0; i < 3; ++i)
src_param_init_from_value(&src_params[i], operands[i]);
instruction_dst_param_init_ssa_scalar(ins, sm6);
}
static void sm6_parser_emit_dx_load_input(struct sm6_parser *sm6, enum dx_intrinsic_opcode op,
const struct sm6_value **operands, struct function_emission_state *state)
{
@ -3936,6 +3966,7 @@ static const struct sm6_dx_opcode_info sm6_dx_op_table[] =
[DX_FMAX ] = {"g", "RR", sm6_parser_emit_dx_binary},
[DX_FMIN ] = {"g", "RR", sm6_parser_emit_dx_binary},
[DX_FRC ] = {"g", "R", sm6_parser_emit_dx_unary},
[DX_IBFE ] = {"m", "iiR", sm6_parser_emit_dx_tertiary},
[DX_IMAX ] = {"m", "RR", sm6_parser_emit_dx_binary},
[DX_IMIN ] = {"m", "RR", sm6_parser_emit_dx_binary},
[DX_ISFINITE ] = {"1", "g", sm6_parser_emit_dx_unary},
@ -3955,6 +3986,7 @@ static const struct sm6_dx_opcode_info sm6_dx_op_table[] =
[DX_SQRT ] = {"g", "R", sm6_parser_emit_dx_unary},
[DX_STORE_OUTPUT ] = {"v", "ii8o", sm6_parser_emit_dx_store_output},
[DX_TAN ] = {"g", "R", sm6_parser_emit_dx_unary},
[DX_UBFE ] = {"m", "iiR", sm6_parser_emit_dx_tertiary},
[DX_UMAX ] = {"m", "RR", sm6_parser_emit_dx_binary},
[DX_UMIN ] = {"m", "RR", sm6_parser_emit_dx_binary},
};