Commit Graph

2119 Commits

Author SHA1 Message Date
aa5380f32a vkd3d-shader/tpf: Do not write RDEF constant buffer entries for HLSL_CLASS_OBJECT variables.
RWBuffer objects would trigger a vkd3d_unreachable() in sm4_base_type().
It would be easy enough to add the required case there, but (manual,
unfortunately) tests show that we aren't supposed to write constant
buffer entries for objects in the first place, as you'd expect.

This particular path ends up being exercised by vkd3d's internal UAV
clear shaders, but unfortunately it looks like our RDEF data may have
more issues; the ability to write tests for it would seem helpful.
2023-11-06 23:09:47 +01:00
a9f33e8657 vkd3d-shader/hlsl: Consistently use HLSL allocation functions. 2023-11-06 23:09:22 +01:00
b9c164c1c4 vkd3d-shader/hlsl: Sort keywords.
Done with `LC_ALL=C sort -f`.
2023-11-06 23:09:20 +01:00
7632365e60 vkd3d-shader/hlsl: Remove C++ comment lexing.
This is already handled by the preprocessor.
2023-11-06 23:09:19 +01:00
4cfc7d44ab vkd3d-shader/hlsl: Remove some tokens from the lexer.
None of these currently have any meaning, and none of these can currently be
parsed as distinct tokens either (i.e. they will generate a syntax error
anyway).
2023-11-06 23:09:18 +01:00
98b5eb474a vkd3d-shader/tpf: Don't pass 0x4 as mask for vec4 constant src registers.
Co-authored-by: Evan Tang <etang@codeweavers.com>

Evan Tang reported that new fixmes appeared on the shader_runner when
running some of his tests after
f50d0ae2cb.

    vkd3d:652593:fixme:shader_sm4_read_src_param Unhandled mask 0x4.

The change to blame seems to be this added line in
sm4_src_from_constant_value().

    +    src->swizzle = VKD3D_SHADER_NO_SWIZZLE;

On tpf binaries the last 12 bits of each src register in an instruction
specify the swizzle, and there are 5 possible combinations:

    Dimension NONE
    -------- 00

    Dimension SCALAR
    -------- 01

    Dimension VEC4, with a 4 bit writemask:
    ---- xxxx 00 01

    Dimension VEC4, with an 8 bit swizzle:
    xx xx xx xx 01 01

    Dimension VEC4, with a 2bit scalar dimension number:
    ------ xx 10 01

So far, we have only seen src registers use 4 bit writemasks in a
single case: for vec4 constants, and it is always zero.

So we expect this:

    ---- 0000 00 01

Now, I probably wanted to initialize src->swizzle to zero when writing
constants, but VKD3D_SHADER_NO_SWIZZLE is not zero, it is actually the
default swizzle:

    11 10 01 00

And the last 4 bits (0x4) get written in the mask part, which causes
the reader to complain.
2023-11-06 23:09:10 +01:00
749df8dec2 vkd3d-shader/dxil: Implement the DXIL BINOP instruction. 2023-11-06 23:09:03 +01:00
3e0638148a vkd3d-shader/spirv: Support VKD3D_DATA_UINT in spirv_compiler_emit_neg().
The DXIL parser uses unsigned types even if the source code uses signed,
so unsigned values may be negated.
2023-11-06 23:09:02 +01:00
4905d047bd vkd3d-shader/spirv: Handle the UMUL instruction. 2023-11-06 23:09:01 +01:00
acbc80cba2 vkd3d-shader/spirv: Introduce an IDIV instruction. 2023-11-06 23:09:00 +01:00
c8d3515d8b vkd3d-shader/spirv: Introduce an FREM instruction. 2023-11-06 23:08:58 +01:00
0d4aebd2e7 vkd3d-shader: Explicitly cast vkd3d_shader_global_flags to uint64_t.
On macOS vkd3d_shader_global_flags has underlying type unsigned long,
while uint64_t is defined as unsigned long long. This difference
causes a few warnings to be raised.
2023-11-06 23:08:37 +01:00
31346e2cba vkd3d-shader/tpf: Fix used temp registers accounting for dcl_temps.
Otherwise we always output "dcl_temps 1" even when no temp registers were used.
2023-11-06 23:08:10 +01:00
f05be8ff12 vkd3d-shader/spirv: No longer handle builtin array size mismatch in spirv_compiler_emit_input().
This is taken care of by prior I/O lowering. We no longer need to deal with this here.
2023-11-06 23:07:59 +01:00
fa23165cc0 vkd3d-shader/spirv: Remove handling of VKD3DSPR_OUTCONTROLPOINT.
I/O normalization removes this register type.
2023-11-06 23:07:58 +01:00
b73d2c978d vkd3d-shader/ir: Check for vocp usage during IR normalization.
The hull shader barrier used for this was broken by I/O normalization, since
vocp is no longer exposed to the spirv backend.

Restore this barrier by checking for vocp during normalization instead.
2023-11-06 23:07:56 +01:00
8b42f523f2 vkd3d-shader/ir: Pass a vkd3d_shader_parser to instruction_array_normalise_io_registers(). 2023-11-06 23:07:54 +01:00
7419f4e31d vkd3d-shader/dxil: Allow empty struct types. 2023-11-02 18:23:12 +01:00
dbcc4c4e40 vkd3d-shader/hlsl: Parse empty technique declarations.
Signed-off-by: Nikolay Sivov <nsivov@codeweavers.com>
2023-11-02 18:23:07 +01:00
53b0101a53 vkd3d-shader/hlsl: Use case-insensitive match for the "technique" keyword.
Signed-off-by: Nikolay Sivov <nsivov@codeweavers.com>
2023-11-02 18:23:06 +01:00
ea8ff5394c vkd3d-shader/hlsl: Add a keyword for fx_5_0 techniques.
Signed-off-by: Nikolay Sivov <nsivov@codeweavers.com>
2023-11-02 18:23:05 +01:00
7ca6a5452a vkd3d-shader/dxil: Always apply the signature element start column to used_mask.
The used_mask value loaded from an additional tag/value pair is relative
to the start column.
2023-11-02 18:22:59 +01:00
af72466db1 vkd3d-shader/ir: Validate the index of a TEMP register. 2023-11-02 18:22:52 +01:00
4140b87499 vkd3d-shader/ir: Validate the DCL_TEMPS instruction. 2023-11-02 18:22:50 +01:00
79fa5fd8bb vkd3d-shader/ir: Validate the register index count. 2023-11-02 18:22:49 +01:00