3712 Commits

Author SHA1 Message Date
Giovanni Mascellani
1cfe23569c vkd3d-shader/ir: Synthesize the default control point phase in the HS control point I/O normaliser.
This makes it available to all backends, without requiring an
ad-hoc solution for each of them. It also gets rid of an
undocumented flag we're currently passing to
DCL_CONTROL_POINT_PHASE.
2024-11-27 13:57:09 +01:00
Francisco Casas
198c3dc7b9 vkd3d-shader/hlsl: Remove hlsl_ir_vsir_instruction_ref, again. 2024-11-27 13:03:15 +01:00
Francisco Casas
d6d6f37578 vkd3d-shader/hlsl: Migrate SM4 control flow instructions to the vsir program.
Translate the instructions that contain hlsl_blocks. Also move
other control flow instructions such as HS_CONTROL_POINT_PHASE and
RET to the vsir_program so that we can directly iterate over it now.
2024-11-27 13:02:53 +01:00
Francisco Casas
81fa4d45b9 vkd3d-shader/tpf: Apply extra bits to all conditional ops. 2024-11-27 12:54:27 +01:00
Francisco Casas
28ad600b43 vkd3d-shader/hlsl: Store SM4 jumps in the vsir program. 2024-11-27 12:54:15 +01:00
Giovanni Mascellani
2c3a7b0dd9 vkd3d-shader/ir: Validate the register type for DCL_OUTPUT_SIV instructions. 2024-11-25 20:51:29 +01:00
Giovanni Mascellani
3832e38ce0 vkd3d-shader/ir: Validate the register type for DCL_OUTPUT instructions. 2024-11-25 20:51:25 +01:00
Giovanni Mascellani
e7770eaaf6 vkd3d-shader/ir: Validate the register type for DCL_INPUT_PS_SGV instructions. 2024-11-25 20:48:39 +01:00
Giovanni Mascellani
1d9862261f vkd3d-shader/ir: Validate the register type for DCL_INPUT_PS_SIV instructions. 2024-11-25 20:48:39 +01:00
Giovanni Mascellani
09ede1e7f2 vkd3d-shader/ir: Validate the register type for DCL_INPUT_PS instructions. 2024-11-25 20:48:39 +01:00
Giovanni Mascellani
31f6b18c84 vkd3d-shader/ir: Validate the register type for DCL_INPUT_SGV instructions. 2024-11-25 20:48:39 +01:00
Giovanni Mascellani
fadaa69b92 vkd3d-shader/ir: Validate the register type for DCL_INPUT_SIV instructions. 2024-11-25 20:48:39 +01:00
Giovanni Mascellani
b007b1dd79 vkd3d-shader/ir: Validate the register type for DCL_INPUT instructions. 2024-11-25 20:48:39 +01:00
Giovanni Mascellani
a8c5f9e667 vkd3d-shader/dxil: Emit register SAMPLEMASK for output sysval SV_Coverage. 2024-11-25 20:47:24 +01:00
Giovanni Mascellani
c22812e20b vkd3d-shader/ir: Validate index count for OUTSTENCILREF registers. 2024-11-25 20:45:44 +01:00
Giovanni Mascellani
e367dc0783 vkd3d-shader/ir: Validate index count for WAVELANEINDEX registers. 2024-11-25 20:45:44 +01:00
Giovanni Mascellani
5b04a7973b vkd3d-shader/ir: Validate index count for WAVELANECOUNT registers. 2024-11-25 20:45:44 +01:00
Giovanni Mascellani
820a545950 vkd3d-shader/ir: Validate index count for GSINSTID registers. 2024-11-25 20:45:44 +01:00
Giovanni Mascellani
07b31761fb vkd3d-shader/ir: Validate index count for SAMPLEMASK registers. 2024-11-25 20:45:44 +01:00
Giovanni Mascellani
9f3bbad6bc vkd3d-shader/ir: Validate index count for COVERAGE registers. 2024-11-25 20:45:44 +01:00
Feifan He
71ce43313f vkd3d-shader/msl: Implement VKD3DSIH_MOVC. 2024-11-25 20:43:13 +01:00
Feifan He
32a507ace6 vkd3d-shader/msl: Implement VKD3DSIH_FRC. 2024-11-25 20:43:13 +01:00
Feifan He
154847c696 vkd3d-shader/msl: Implement VKD3DSIH_GEO. 2024-11-25 20:43:13 +01:00
Feifan He
38d7f8415d vkd3d-shader/msl: Implement support for VKD3DSPSM_NEG modifiers. 2024-11-25 20:43:13 +01:00
Feifan He
64ea19b7f7 vkd3d-shader/msl: Implement VKD3DSIH_DIV. 2024-11-25 20:43:13 +01:00