2262 Commits

Author SHA1 Message Date
Nikolay Sivov
522a0dfb56 vkd3d-shader/hlsl: Add tex2Dlod() function.
Signed-off-by: Nikolay Sivov <nsivov@codeweavers.com>
2023-11-08 22:49:26 +01:00
Zebediah Figura
852eefc01d vkd3d-shader/ir: Synthesize HS inputs with the register index and write mask of the signature element.
This pass was written as if to output normalized I/O, but it runs before the I/O
normalization pass.

Fixes: 98b5e2c6e01199d714d18fccfe54826a680aecbf
2023-11-07 22:26:53 +01:00
Zebediah Figura
12240efa79 vkd3d-shader/spirv: Use register counts from the signature and shader desc. 2023-11-07 22:26:49 +01:00
Zebediah Figura
0058764f01 vkd3d-shader: Store the control point counts in struct vkd3d_shader_desc. 2023-11-07 22:26:49 +01:00
Zebediah Figura
3ff22ac5af vkd3d-shader/spirv: Use the array sizes for shader phase builtins as well. 2023-11-07 22:26:47 +01:00
Zebediah Figura
f0a6c7de1d vkd3d-shader/hlsl: Record partial allocations in allocate_range(). 2023-11-07 22:26:11 +01:00
Zebediah Figura
c683fc9402 vkd3d-shader/hlsl: Check that a partial register's mask is also available in is_range_available(). 2023-11-07 22:26:10 +01:00
Giovanni Mascellani
7d49f9637a vkd3d-shader/ir: Check that SWITCH blocks are correctly nested. 2023-11-07 22:26:05 +01:00
Giovanni Mascellani
93632fb407 vkd3d-shader/ir: Check that REP blocks are correctly nested. 2023-11-07 22:26:04 +01:00
Giovanni Mascellani
92c36615ed vkd3d-shader/ir: Check that LOOP blocks are correctly nested. 2023-11-07 22:26:03 +01:00
Giovanni Mascellani
2f7d52dba4 vkd3d-shader/ir: Check that IF blocks are correctly nested. 2023-11-07 22:26:01 +01:00
Giovanni Mascellani
0a7e200f89 vkd3d-shader/ir: Do not enfore DCL_TEMPS count for hull shaders.
Hull shaders have a different temps count for each phase, and the
parser only reports the count for the patch constant phase.
In order to properly check for temps count on hull shaders, we first
need to decode its phases.
2023-11-07 22:26:00 +01:00
Giovanni Mascellani
ca3f594ae3 vkd3d-shader/ir: Emit an ERR() on validation errors. 2023-11-07 22:25:58 +01:00
Francisco Casas
0ef25ad137 vkd3d-shader/tpf: Support relative addressing for indexable temps in SM4.
For relative addressing, the vkd3d_shader_registers must point to
another vkd3d_shader_src_param. For now, use the sm4_instruction to save
them, since the only purpose of this struct is to be used as paramter
for write_sm4_instruction.
2023-11-07 22:25:49 +01:00
Francisco Casas
281796c526 vkd3d-shader/tpf: Move sm4_register_from_node() up. 2023-11-07 22:25:48 +01:00
Francisco Casas
e10d41d799 vkd3d-shader/tpf: Support writing relative addressing indexes. 2023-11-07 22:25:47 +01:00
Francisco Casas
617a20bffc vkd3d-shader/tpf: Write register index addressing. 2023-11-07 22:25:45 +01:00
Francisco Casas
043526a9f7 vkd3d-shader/tpf: Encode dst and src registers using the same function.
This function will also be required to encode rel_addr registers.
2023-11-07 22:25:44 +01:00
Henri Verbeet
aa5380f32a vkd3d-shader/tpf: Do not write RDEF constant buffer entries for HLSL_CLASS_OBJECT variables.
RWBuffer objects would trigger a vkd3d_unreachable() in sm4_base_type().
It would be easy enough to add the required case there, but (manual,
unfortunately) tests show that we aren't supposed to write constant
buffer entries for objects in the first place, as you'd expect.

This particular path ends up being exercised by vkd3d's internal UAV
clear shaders, but unfortunately it looks like our RDEF data may have
more issues; the ability to write tests for it would seem helpful.
2023-11-06 23:09:47 +01:00
Zebediah Figura
a9f33e8657 vkd3d-shader/hlsl: Consistently use HLSL allocation functions. 2023-11-06 23:09:22 +01:00
Zebediah Figura
b9c164c1c4 vkd3d-shader/hlsl: Sort keywords.
Done with `LC_ALL=C sort -f`.
2023-11-06 23:09:20 +01:00
Zebediah Figura
7632365e60 vkd3d-shader/hlsl: Remove C++ comment lexing.
This is already handled by the preprocessor.
2023-11-06 23:09:19 +01:00
Zebediah Figura
4cfc7d44ab vkd3d-shader/hlsl: Remove some tokens from the lexer.
None of these currently have any meaning, and none of these can currently be
parsed as distinct tokens either (i.e. they will generate a syntax error
anyway).
2023-11-06 23:09:18 +01:00
Francisco Casas
98b5eb474a vkd3d-shader/tpf: Don't pass 0x4 as mask for vec4 constant src registers.
Co-authored-by: Evan Tang <etang@codeweavers.com>

Evan Tang reported that new fixmes appeared on the shader_runner when
running some of his tests after
f50d0ae2cbc5ee2a26fedd7b8aac2def62decd6c.

    vkd3d:652593:fixme:shader_sm4_read_src_param Unhandled mask 0x4.

The change to blame seems to be this added line in
sm4_src_from_constant_value().

    +    src->swizzle = VKD3D_SHADER_NO_SWIZZLE;

On tpf binaries the last 12 bits of each src register in an instruction
specify the swizzle, and there are 5 possible combinations:

    Dimension NONE
    -------- 00

    Dimension SCALAR
    -------- 01

    Dimension VEC4, with a 4 bit writemask:
    ---- xxxx 00 01

    Dimension VEC4, with an 8 bit swizzle:
    xx xx xx xx 01 01

    Dimension VEC4, with a 2bit scalar dimension number:
    ------ xx 10 01

So far, we have only seen src registers use 4 bit writemasks in a
single case: for vec4 constants, and it is always zero.

So we expect this:

    ---- 0000 00 01

Now, I probably wanted to initialize src->swizzle to zero when writing
constants, but VKD3D_SHADER_NO_SWIZZLE is not zero, it is actually the
default swizzle:

    11 10 01 00

And the last 4 bits (0x4) get written in the mask part, which causes
the reader to complain.
2023-11-06 23:09:10 +01:00
Conor McCarthy
749df8dec2 vkd3d-shader/dxil: Implement the DXIL BINOP instruction. 2023-11-06 23:09:03 +01:00