Henrik Rydgård
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d6cdb6e5d9
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Merge pull request #17900 from unknownbrackets/irjit-vsgelt
irjit: Implement vsge/vslt
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2023-08-13 19:59:14 +02:00 |
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Unknown W. Brackets
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23c79f8e7f
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irjit: Implement vsge/vslt.
These are not ideal especially for SIMD, but they do work.
Improves performance in Silent Hill on RISC-V by like 20%.
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2023-08-13 10:40:47 -07:00 |
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Unknown W. Brackets
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5d20f2aabd
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irjit: Simplify VecDo3.
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2023-08-13 10:40:47 -07:00 |
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Unknown W. Brackets
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2b36e0a625
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irjit: ZeroFpCond -> FpCondFromReg.
We already have a zero reg, so this is more useful and symmetrical.
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2023-08-13 10:40:47 -07:00 |
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Unknown W. Brackets
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2bb67db43c
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riscv: Switch to the logBlocks model for disasm.
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2023-08-13 10:37:21 -07:00 |
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Unknown W. Brackets
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8c036a889d
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riscv: Add debug log of block disasm.
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2023-08-13 10:32:04 -07:00 |
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Unknown W. Brackets
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7cc6c5fa62
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riscv: Fix load error w/o pointerify.
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2023-08-13 10:20:28 -07:00 |
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Unknown W. Brackets
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be938a850b
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riscv: Remove FMul safety check.
Let's just see if everything's right, this bloats multiplies a lot.
Doesn't seem to impact perf a lot, though.
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2023-08-13 10:20:20 -07:00 |
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Unknown W. Brackets
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fa53b80574
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irjit: Cleanup/purge FPU/VFPU temps.
A lot of cases are followed by an FMov that just moved the temp to a
regular register, from VFPU instructions playing safe about overlaps.
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2023-08-13 10:14:10 -07:00 |
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Unknown W. Brackets
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81f67c717c
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riscv: Fix block link for prev blocks.
Oops, was just reversed so never linking.
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2023-08-12 10:48:39 -07:00 |
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Unknown W. Brackets
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fcc90095f7
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riscv: Enable block linking.
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2023-08-12 09:37:02 -07:00 |
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Unknown W. Brackets
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247788806a
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irjit: Add direct helper for start PC.
It's annoying always fetching length too.
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2023-08-12 09:37:02 -07:00 |
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Unknown W. Brackets
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b3cdf06c5a
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riscv: Write fixup on block invalidation.
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2023-08-12 09:37:02 -07:00 |
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Unknown W. Brackets
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3757ebca2d
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irjit: Invalidate/finalize target blocks.
Doesn't actually do anything yet, but adds plumbing.
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2023-08-12 09:37:02 -07:00 |
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Henrik Rydgård
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2342c4522c
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Merge pull request #17875 from unknownbrackets/riscv-jit
RISC-V: Implement a few more ops
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2023-08-09 09:30:15 +02:00 |
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Henrik Rydgård
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bac4e8d42d
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Merge pull request #17874 from unknownbrackets/irjit-exits
IR: Simplify exits to ExitToConst when viable
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2023-08-09 09:11:52 +02:00 |
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Unknown W. Brackets
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2c13b6d973
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riscv: Implement vc2i.
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2023-08-08 23:17:32 -07:00 |
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Unknown W. Brackets
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28c58c1d24
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irjit: Allow more forms of vmidt.
Mildly worth it.
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2023-08-08 23:17:32 -07:00 |
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Unknown W. Brackets
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4b9011e475
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riscv: Reduce call bloat using temps.
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2023-08-08 23:17:32 -07:00 |
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Unknown W. Brackets
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ddf3d02a3c
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riscv: Implement vi2uc.
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2023-08-08 23:17:32 -07:00 |
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Unknown W. Brackets
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268adf1aa1
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riscv: Implement scaled float/int convert.
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2023-08-08 23:17:32 -07:00 |
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Unknown W. Brackets
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0b4e7d60f9
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riscv: Implement ReverseBits in jit.
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2023-08-08 23:17:32 -07:00 |
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Unknown W. Brackets
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ad4cbbab8e
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riscv: Don't cache mipState on backend.
Bad sign if we're trying to use it, anyway.
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2023-08-08 23:17:32 -07:00 |
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Unknown W. Brackets
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31ff23746c
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irjit: Prefer ExitToConst over ExitToReg.
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2023-08-08 23:14:01 -07:00 |
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Unknown W. Brackets
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3f97545f99
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irjit: Reduce exits from constants.
This reduces bloat a bit, and may help with common funcs that enter short
loops.
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2023-08-08 23:05:14 -07:00 |
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