Unknown W. Brackets
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57123e8f9e
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irjit: Reserve some arrays that churn.
Improves IR compile time by around 20-30%.
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2023-08-20 08:59:47 -07:00 |
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Henrik Rydgård
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cd1c5beb60
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Merge pull request #17934 from unknownbrackets/riscv-centralize
RISC-V: Centralize IR regcaches
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2023-08-20 14:49:18 +02:00 |
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Unknown W. Brackets
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161465ab66
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riscv: Centralize register FlushAll().
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2023-08-19 21:30:03 -07:00 |
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Unknown W. Brackets
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f3d4bd8c11
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riscv: Centralize reg-as-pointer.
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2023-08-19 21:24:36 -07:00 |
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Unknown W. Brackets
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bd1d93ae6f
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irjit: Cleanup Write() calls with extra const.
Some instructions, such as Vec4Blend, are encoded requiring the const
field, and this interface was designed when we used a pool.
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2023-08-19 16:23:42 -07:00 |
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Unknown W. Brackets
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92f7374c89
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riscv: Centralize reg mapping itself.
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2023-08-19 16:15:49 -07:00 |
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Unknown W. Brackets
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718a1b3944
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riscv: Centralize MarkDirty flagging.
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2023-08-19 16:15:49 -07:00 |
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Unknown W. Brackets
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4e41f83ecc
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riscv: Centralize IR reg cache metadata checks.
These are all largely the same between backends.
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2023-08-17 23:03:31 -07:00 |
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Unknown W. Brackets
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ebab0e1591
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riscv: Centralize reg allocation.
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2023-08-17 18:50:33 -07:00 |
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Unknown W. Brackets
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b30daa5760
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riscv: Centralize state of regcaches.
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2023-08-15 21:51:38 -07:00 |
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Henrik Rydgård
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1b2cffe632
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Address feedback
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2023-08-14 11:06:20 +02:00 |
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Henrik Rydgård
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ff6e118fff
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Get rid of a lot of ifdefs around presentation mode. Instead, set things dynamically.
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2023-08-14 11:02:29 +02:00 |
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Henrik Rydgård
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1beb01af6a
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Merge pull request #17905 from unknownbrackets/irjit-opt
irjit: Implement some missing, handle partial Vec4s more
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2023-08-14 07:49:45 +02:00 |
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Henrik Rydgård
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63b3b31feb
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Merge pull request #17906 from unknownbrackets/riscv-blocklink
riscv: Fix crash on clear icache
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2023-08-14 07:42:38 +02:00 |
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Henrik Rydgård
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a7bc70834c
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Merge pull request #17907 from unknownbrackets/riscv-minor
riscv: Implement vs2i
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2023-08-14 07:41:45 +02:00 |
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Unknown W. Brackets
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52cc38bf2a
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riscv: Implement vs2i.
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2023-08-13 18:27:19 -07:00 |
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Unknown W. Brackets
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3f8f8d36d9
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riscv: Fix crash on clear icache.
Oops, can't avoid marking all blocks invalid. Luckily a syscall should
always take more bytes than the bail invalidated block code.
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2023-08-13 18:25:46 -07:00 |
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Unknown W. Brackets
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159b41a0fa
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irjit: Fuse unaligned svl.q/svr.q together.
They're almost never used outside paired, which we can do on most
platforms easily.
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2023-08-13 18:10:40 -07:00 |
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Unknown W. Brackets
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5729de90d2
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irjit: Use more partial Vec4s / Vec4Blend.
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2023-08-13 18:10:40 -07:00 |
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Unknown W. Brackets
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2e6dbab5fa
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irjit: Add flag to prefer Vec4, use for add/sub.
This will improve things when using SIMD.
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2023-08-13 18:10:40 -07:00 |
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Unknown W. Brackets
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e0be6858b8
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irjit: Implement vcrs.t.
As used in Jeanne d'Arc.
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2023-08-13 18:10:12 -07:00 |
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Unknown W. Brackets
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217a1837ed
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irjit: Allow typical prefixes in vdiv/vasin/etc.
Some of these behave strangely, but there are some common usages that work
fine.
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2023-08-13 18:10:07 -07:00 |
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Henrik Rydgård
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2cdcc413b7
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Merge pull request #17898 from unknownbrackets/irjit-vfputemps
irjit: Cleanup/purge FPU/VFPU temps
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2023-08-13 21:08:00 +02:00 |
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Henrik Rydgård
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5dcd14b17a
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Merge pull request #17901 from unknownbrackets/riscv-disasm
riscv: Add debug log of block disasm
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2023-08-13 21:07:37 +02:00 |
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Unknown W. Brackets
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f03cd0b2ad
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Merge pull request #17899 from unknownbrackets/riscv-minor
Minor RISC-V cleanups, frame profiler fix
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2023-08-13 11:19:42 -07:00 |
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