2700 Commits

Author	SHA1	Message	Date
Unknown W. Brackets	9f917488c3	riscv: Fix PC in disassembly.	2023-07-30 14:19:28 -07:00
Unknown W. Brackets	e34736fbb2	riscv: Reduce norms in Slt/Sltu overlap cases. ... We can skip an SEXT.W in common cases where the dest and src overlap.	2023-07-30 14:19:28 -07:00
Unknown W. Brackets	d1dc346899	riscv: Fix pointer add/sub.	2023-07-30 14:19:28 -07:00
Unknown W. Brackets	09f3842a32	riscv: Fix VFPU compare typos.	2023-07-30 14:19:28 -07:00
Unknown W. Brackets	f3240393fa	irjit: Use vf for vfpu regs, v0 is a gpr.	2023-07-30 14:16:17 -07:00
Unknown W. Brackets	6819acd29f	irjit: Fix flag on float cond move.	2023-07-30 14:16:17 -07:00
Unknown W. Brackets	5db6b11ef2	irjit: Cleanup self-fmovs. ... These were sometimes getting emitted.	2023-07-30 14:16:17 -07:00
Unknown W. Brackets	c24e3ef831	riscv: Implement ll/sc.	2023-07-30 00:45:51 -07:00
Unknown W. Brackets	26a527bdf8	riscv: Implement float/int conversion.	2023-07-30 00:45:51 -07:00
Henrik Rydgård	b93275bb35	Merge pull request #17800 from unknownbrackets/riscv-jit ... More RISC-V jit ops	2023-07-30 09:26:22 +02:00
Henrik Rydgård	c8447ff4b7	Merge pull request #17801 from unknownbrackets/irjit-vminmax ... irjit: Fix vmin/vmax nan handling	2023-07-30 09:18:25 +02:00
Henrik Rydgård	180bda6f6b	Merge pull request #17799 from unknownbrackets/irjit-lsu ... Add ll/sc to IR and x86jit	2023-07-30 09:15:55 +02:00
Unknown W. Brackets	0036f3c494	riscv: Implement FMin/FMax.	2023-07-30 00:02:10 -07:00
Unknown W. Brackets	8e8081c686	riscv: Implement VFPU compares.	2023-07-30 00:02:10 -07:00
Unknown W. Brackets	9c9330a207	riscv: Implement float conditional move.	2023-07-30 00:02:10 -07:00
Unknown W. Brackets	70ff18a463	riscv: Implement count leading zeros.	2023-07-30 00:02:10 -07:00
Unknown W. Brackets	a5671bc716	riscv: Add simple debug log of missed ops.	2023-07-30 00:02:10 -07:00
Unknown W. Brackets	6aa4b0c5e1	irjit: Fix vmin/vmax nan handling. ... Should be relevant to NFS MW and possibly other game bugs.	2023-07-29 19:13:12 -07:00
Unknown W. Brackets	6d4fb949c2	riscv: Implement float compare ops.	2023-07-29 19:02:15 -07:00
Unknown W. Brackets	6b632a103d	riscv: Implement FSin/similar.	2023-07-29 19:02:15 -07:00
Unknown W. Brackets	921bd2391c	riscv: Implement vi2s.	2023-07-29 19:02:15 -07:00
Unknown W. Brackets	e2765db4dc	riscv: Implement division.	2023-07-29 19:02:15 -07:00
Unknown W. Brackets	f65b6fdb20	riscv: Remove incomplete block check. ... It shouldn't be necessary and bad things would happen anyway if it did.	2023-07-29 19:02:15 -07:00
Unknown W. Brackets	8d60c10a64	riscv: Use jit address offsets directly. ... We'll have IR able to use block number or target offset.	2023-07-29 19:02:15 -07:00
Unknown W. Brackets	b6d2e64aca	Debugger: Fix disasm of ll/sc.	2023-07-29 18:50:09 -07:00