Unknown W. Brackets
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5f9a8fd1a1
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irjit: Rename IRRegCache to IRImmRegCache.
For clarity, since it's not a native regcache.
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2023-08-08 23:05:14 -07:00 |
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Unknown W. Brackets
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1a92027810
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riscv: Make Vec4Shuffle overlap safe.
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2023-08-08 23:00:45 -07:00 |
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Unknown W. Brackets
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e73c203984
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irjit: Fix Vec4Shuffle overlap issue.
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2023-08-08 23:00:39 -07:00 |
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Henrik Rydgård
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e9431d0d1e
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Merge pull request #17859 from unknownbrackets/irjit-vec4
irjit: Use Vec4 a bit more
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2023-08-06 23:05:33 +02:00 |
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Unknown W. Brackets
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3dc71cff75
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irjit: Keep a couple more ops in Vec4.
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2023-08-06 13:46:24 -07:00 |
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Unknown W. Brackets
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6a1dbd4cde
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irjit: Allow Vec4 to be used with masks.
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2023-08-06 13:46:24 -07:00 |
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Unknown W. Brackets
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2b964fd3b0
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irjit: Handle more common Vec4 prefix cases.
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2023-08-06 13:38:00 -07:00 |
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Unknown W. Brackets
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79ca880ac7
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irjit: Implement vqmul, add Vec4Blend.
Should be useful more places.
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2023-08-06 13:38:00 -07:00 |
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Unknown W. Brackets
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85ee7c85c1
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irjit: Allow masked vneg.q.
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2023-08-06 13:38:00 -07:00 |
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Henrik Rydgård
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d90dbcb28e
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Merge pull request #17857 from unknownbrackets/ir-vfpuctrl
irjit: Fix mfvc eating prefixes
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2023-08-06 17:56:22 +02:00 |
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Unknown W. Brackets
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a32889d3ca
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irjit: Consistently dirty vfpuctrl in IR.
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2023-08-06 08:36:19 -07:00 |
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Unknown W. Brackets
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a29a35b91a
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irjit: Fix mfvc eating prefixes.
It doesn't and shouldn't, which is why it's marked as not.
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2023-08-06 08:28:25 -07:00 |
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Henrik Rydgård
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70622e0d4e
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Merge pull request #17853 from Nemoumbra/buildfix
Buildfix for VS2017
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2023-08-06 14:29:04 +02:00 |
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Nemoumbra
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c2f9ae2e16
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Buildfix for VS2017
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2023-08-06 15:06:54 +03:00 |
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Unknown W. Brackets
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93e3d35f5d
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irjit: Move more to IRNativeBackend, split.
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2023-08-06 00:16:43 -07:00 |
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Unknown W. Brackets
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691799a0ca
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irjit: Centralize native jit compile dispatch.
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2023-08-03 23:14:58 -07:00 |
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Unknown W. Brackets
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0d0029fc9d
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riscv: Add bitmanip ops to disasm.
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2023-07-30 17:45:36 -07:00 |
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Unknown W. Brackets
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c24dca12bb
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Build: Fix link issue for rv64 disasm.
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2023-07-30 16:06:55 -07:00 |
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Unknown W. Brackets
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b03398a46c
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Merge pull request #17815 from unknownbrackets/riscv-jit
riscv: Spill registers more intelligently
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2023-07-30 14:49:37 -07:00 |
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Henrik Rydgård
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fa2b831dbc
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Merge pull request #17814 from unknownbrackets/riscv-jit-debug
riscv: Implement block debug interface
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2023-07-30 23:42:14 +02:00 |
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Henrik Rydgård
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fa558b5b71
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Merge pull request #17813 from unknownbrackets/riscv-jit-fixes
Fix some typos and mistakes in RISC-V jit
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2023-07-30 23:41:13 +02:00 |
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Unknown W. Brackets
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f870271011
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riscv: Spill registers more intelligently.
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2023-07-30 14:24:12 -07:00 |
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Unknown W. Brackets
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020706f545
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riscv: Implement float saturate clamping.
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2023-07-30 14:24:12 -07:00 |
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Unknown W. Brackets
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45d44c1d4f
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riscv: Implement block debug interface.
This gives us the target disasm in jit compare, bloat, etc.
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2023-07-30 14:21:43 -07:00 |
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Unknown W. Brackets
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5ef4b2b5fa
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riscv: Fix assert when flushing not mapped reg.
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2023-07-30 14:19:28 -07:00 |
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