Henrik Rydgård
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61bf366d30
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Merge pull request #17942 from unknownbrackets/irjit-clobber
irjit: Fix regalloc clobber on exit
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2023-08-21 08:04:50 +02:00 |
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Unknown W. Brackets
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2b914046ff
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x86jit: Implement most exits.
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2023-08-20 22:28:54 -07:00 |
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Unknown W. Brackets
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104b6d8c15
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x86jit: Implement some basic arithmetic.
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2023-08-20 22:28:54 -07:00 |
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Unknown W. Brackets
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5045cf012e
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x86jit: Fix flushing of zero register.
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2023-08-20 22:28:54 -07:00 |
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Unknown W. Brackets
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08ea31f405
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x86jit: Improve debug disasm.
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2023-08-20 22:28:54 -07:00 |
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Unknown W. Brackets
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4e7f8cf213
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x86jit: Implement load/store.
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2023-08-20 22:28:54 -07:00 |
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Unknown W. Brackets
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a47b4424e5
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x86jit: Fix some silly mistakes.
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2023-08-20 22:28:54 -07:00 |
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Unknown W. Brackets
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4e3f3860f9
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x86jit: Stub out op categories to files.
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2023-08-20 22:28:54 -07:00 |
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Unknown W. Brackets
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622c69dbb9
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x86jit: Expose option to select new IR based jit.
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2023-08-20 22:28:54 -07:00 |
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Unknown W. Brackets
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c491f701ba
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x86jit: Add initial IR-based jit backend.
It works, but pretty slow in some parts with everything stubbed.
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2023-08-20 22:28:54 -07:00 |
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Unknown W. Brackets
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81e24a9fee
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irjit: Fix regalloc clobber on exit.
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2023-08-20 22:12:52 -07:00 |
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Unknown W. Brackets
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8dfc2f04d7
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riscv: Use a single reg for LO/HI.
This is the same optimization we have for arm64, basically.
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2023-08-20 14:49:09 -07:00 |
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Henrik Rydgård
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629d46ef5b
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Merge pull request #17938 from unknownbrackets/riscv-centralize
Centralize IR regcache from RISC-V
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2023-08-20 23:47:02 +02:00 |
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Henrik Rydgård
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6554b3eb75
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Merge pull request #17939 from unknownbrackets/ir-vec-minor
irjit: Implement vtfm 4x4 using dots
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2023-08-20 23:40:04 +02:00 |
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Unknown W. Brackets
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82fb41cba0
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irjit: Implement vtfm 4x4 using dots.
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2023-08-20 13:50:02 -07:00 |
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Unknown W. Brackets
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36b6aa4728
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riscv: Allow GPR "SIMD" without FPR SIMD.
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2023-08-20 12:42:11 -07:00 |
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Unknown W. Brackets
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6a75e6712e
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riscv: Use automapping for special cases too.
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2023-08-20 12:42:11 -07:00 |
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Unknown W. Brackets
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a190793ad2
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riscv: Simplify mapping for more instructions.
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2023-08-20 12:42:11 -07:00 |
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Unknown W. Brackets
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cc4bc406d5
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riscv: Cleanup VfpuCtrlToReg meta, use auto-map.
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2023-08-20 12:42:11 -07:00 |
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Unknown W. Brackets
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e40ae60029
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riscv: Mark normalized32 after mapping.
It's less confusing to separate it.
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2023-08-20 12:42:11 -07:00 |
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Unknown W. Brackets
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f9bf7de701
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riscv: Use a single reg cache.
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2023-08-20 12:42:11 -07:00 |
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Unknown W. Brackets
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e30fb82a64
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riscv: Remove some unused reg funcs.
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2023-08-20 12:42:11 -07:00 |
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Unknown W. Brackets
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a23ade8f75
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riscv: Map IR regs based on metadata.
Only doing this in places without GPR/FPR mix or FPR/Vec overlap for now.
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2023-08-20 12:42:11 -07:00 |
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Unknown W. Brackets
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32d8f6196f
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irjit: Cut time flushing imm regs.
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2023-08-20 08:59:47 -07:00 |
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Unknown W. Brackets
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552cd88938
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irjit: Skip some work in PurgeTemps.
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2023-08-20 08:59:47 -07:00 |
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