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Sometimes SM1-3 shaders contain write masks that exceed the signature element masks. That happens because SM1-3 shaders do not have a concept of signature and signature masks, and OTOH aren't always able to express any given write mask. In VSIR we don't want to deal with I/O register masks exceeding the corresponding signature element mask or usage mask, because, for instance, for higher shader models it can complicate dealing with DCL_INDEX_RANGE. In order to have uniform rules for all shader models we normalise masks coming from SM1-3 shaders. We don't do that normalisation when disassembling, in order to preserve the expected output.