625e289574
vkd3d-shader/dxil: Handle hyperbolic trigonometric functions in sm6_parser_emit_dx_unary().
2024-02-07 22:59:23 +01:00
7f87a3e5fc
vkd3d-shader/spirv: Handle the ACOS, ASIN and ATAN instructions in spirv_compiler_emit_ext_glsl_instruction().
2024-02-06 23:09:55 +01:00
eb723a8d2b
vkd3d-shader/spirv: Support bool TEMP registers.
2024-02-06 23:06:58 +01:00
49f0fd42b8
vkd3d-shader/spirv: Move bool casting helpers above register loading helpers.
2024-02-06 23:06:55 +01:00
ee994e95dd
vkd3d-shader/spirv: Convert the swizzle according to the source bit width.
...
Fixes: 1f536238a8
2024-02-06 23:06:53 +01:00
95e4222cc6
vkd3d-shader/spirv: Emit a vector bitcast if necessary in spirv_compiler_emit_load_ssa_reg().
2024-02-01 22:25:04 +01:00
ebec0aa434
vkd3d-shader/dxil: Implement DX intrinsic TextureLoad.
2024-02-01 22:25:02 +01:00
cc72a8d311
vkd3d-shader/spirv: Free binary SPIR-V code (Valgrind).
2024-02-01 00:08:28 +01:00
1f536238a8
vkd3d-shader: Use 64 bit swizzles for 64 bit data types in VSIR.
...
The handling of write masks and swizzles for 64 bit data types is
currently irregular: write masks are always 64 bit, while swizzles
are usually 32 bit, except for SSA registers with are 64 bit.
With this change we always use 64 bit swizzles, in order to make
the situation less surprising and make it easier to convert
registers between SSA and TEMP.
64 bit swizzles are always required to have X in their last two
components.
2024-01-29 22:33:33 +01:00
92f0b37133
vkd3d-shader/spirv: Support 64-bit source value for bitfield instructions.
2024-01-29 22:33:22 +01:00
378109051c
vkd3d-shader/ir: Lower monolithic switches to selection ladders.
...
PHI nodes must be fixed up after this pass, because the block references
might have become broken. For simplicitly this is not handled yet.
The goal for this pass is to make the CFG structurizer simpler, because
only conditional and unconditional branches must be supported.
Eventually this limitation might be lifted if there is advantage in
doing so.
2024-01-29 22:33:15 +01:00
b97edee03d
vkd3d-shader/spirv: Emit an error if merge information is missing.
...
Instead of crashing.
2024-01-29 22:33:14 +01:00
f954724870
vkd3d-shader/spirv: Handle the TAN instruction in spirv_compiler_emit_ext_glsl_instruction().
2024-01-25 22:24:44 +01:00
8ae69c745b
vkd3d-shader/spirv: Handle thread group UAV barriers.
2024-01-25 22:24:23 +01:00
18e9148f58
vkd3d-shader/spirv: Include Uniform in the memory semantics for UAV barriers.
...
The UniformMemory semantic applies the constraints to Uniform storage
class memory, which matches how UAV variables are declared.
2024-01-25 22:24:22 +01:00
adfbecef3c
vkd3d-shader/spirv: Handle globally coherent UAVs.
2024-01-25 22:24:20 +01:00
54f6e6dd67
vkd3d-shader/spirv: Check for FEATURE_FLOAT64 when double precision use is flagged.
2024-01-24 22:38:09 +01:00
e973271a40
vkd3d-shader/spirv: Handle the ISINF and ISNAN instructions in spirv_compiler_emit_alu_instruction().
2024-01-24 22:38:04 +01:00
cd674d593e
vkd3d-shader/spirv: Implement the ISFINITE instruction.
2024-01-24 22:38:03 +01:00
b92f6c448a
vkd3d-shader/ir: Lower texkill instructions to discard_nz.
2024-01-24 22:37:41 +01:00
bf628f0c74
vkd3d-shader/ir: Store block names in struct vsir_program.
2024-01-23 20:27:35 +01:00
f3c7d2d05c
vkd3d-shader/ir: Store the block count in struct vsir_program.
2024-01-23 20:27:34 +01:00
98c6e85b33
vkd3d-shader/ir: Store control point counts in struct vsir_program.
2024-01-23 20:27:32 +01:00
e4660fe0e6
vkd3d-shader/spirv: Emit DISCARD as a function call.
2024-01-23 20:26:59 +01:00
de9725b6ba
vkd3d-shader/ir: Remove DCL_TEMPS instructions.
...
We have to do work to keep it updated across passes and we never read it.
2024-01-23 20:26:38 +01:00
