Unknown W. Brackets
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3383d5b93a
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Merge pull request #17751 from unknownbrackets/riscv-jit
Initial RISC-V jit based on IR
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2023-07-25 00:42:22 -07:00 |
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Henrik Rydgård
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a72c4aa383
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Actually fix the race condition. Can't do any initialization step while waiting.
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2023-07-24 12:08:15 +02:00 |
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Henrik Rydgård
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3ae520c35d
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RetroAchievements: Fix another race condition, improve logging.
Seems to help the frontend problem.
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2023-07-24 12:00:16 +02:00 |
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Unknown W. Brackets
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b6f83ca969
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riscv: Cleanup some pointerification flags.
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2023-07-23 21:17:55 -07:00 |
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Unknown W. Brackets
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18c48681a8
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riscv: Implement multiply instructions.
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2023-07-23 18:01:50 -07:00 |
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Unknown W. Brackets
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7f4689e8fa
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riscv: Use direct SLI/SLIU instructions.
Derp, I forgot these existed on RISC-V for a moment.
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2023-07-23 18:01:46 -07:00 |
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Unknown W. Brackets
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ca15fa7061
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riscv: Enable jit by default.
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2023-07-23 18:01:00 -07:00 |
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Unknown W. Brackets
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4100767b5e
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riscv: Optimize SetConst a bit.
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2023-07-23 18:01:00 -07:00 |
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Unknown W. Brackets
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f7f7531500
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riscv: Fix min/max normalization.
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2023-07-23 18:01:00 -07:00 |
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Unknown W. Brackets
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34bfe93ea5
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riscv: Fix block lookup issues.
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2023-07-23 18:01:00 -07:00 |
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Unknown W. Brackets
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92694e765f
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riscv: Implement conditional moves.
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2023-07-23 18:01:00 -07:00 |
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Unknown W. Brackets
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2c7da94bd1
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riscv: Implement shifts and compares.
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2023-07-23 18:01:00 -07:00 |
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Unknown W. Brackets
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5ed2f0d559
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riscv: Implement logic ops.
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2023-07-23 18:01:00 -07:00 |
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Unknown W. Brackets
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94be343591
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riscv: Try to keep regs normalized, track.
Since we can't address the lower 32-bits only in compares, this can help
us avoid renormalizing before a compare.
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2023-07-23 18:01:00 -07:00 |
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Unknown W. Brackets
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7aafa11d24
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riscv: Implement conditional exits.
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2023-07-23 18:01:00 -07:00 |
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Unknown W. Brackets
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8ee73264bf
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riscv: Correct depointerify on FlushAll().
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2023-07-23 18:01:00 -07:00 |
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Unknown W. Brackets
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720f868a10
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riscv: Use R_RA as a temporary for calls.
This is the most logical thing, since we're about to write it anyway.
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2023-07-23 18:01:00 -07:00 |
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Unknown W. Brackets
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76e3246065
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riscv: Reduce jit codesize a bit.
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2023-07-23 18:01:00 -07:00 |
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Unknown W. Brackets
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d31eded9ba
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riscv: Allow dirty pointers, explicitly.
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2023-07-23 18:01:00 -07:00 |
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Unknown W. Brackets
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624caa2dea
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riscv: Implement the simplest exits.
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2023-07-23 18:01:00 -07:00 |
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Unknown W. Brackets
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1dfedde741
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riscv: Avoid needless save/load around compile.
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2023-07-23 18:01:00 -07:00 |
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Unknown W. Brackets
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165169eb31
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riscv: Implement load and store ops.
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2023-07-23 18:01:00 -07:00 |
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Unknown W. Brackets
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c2da7d18bb
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riscv: Stub out more IR compilation categories.
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2023-07-23 18:01:00 -07:00 |
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Unknown W. Brackets
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05a2789cf4
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riscv: Implement some simple assign instructions.
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2023-07-23 18:01:00 -07:00 |
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Unknown W. Brackets
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c6c25af484
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riscv: Add some safety to pointerifying.
We have to clear the upper bits in case of sign extension or other things.
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2023-07-23 18:01:00 -07:00 |
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