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12621 Commits

Author SHA1 Message Date
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e34736fbb2 riscv: Reduce norms in Slt/Sltu overlap cases. 
We can skip an SEXT.W in common cases where the dest and src overlap.
 2023-07-30 14:19:28 -07:00
Unknown W. Brackets
d1dc346899 riscv: Fix pointer add/sub. 2023-07-30 14:19:28 -07:00
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09f3842a32 riscv: Fix VFPU compare typos. 2023-07-30 14:19:28 -07:00
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f3240393fa irjit: Use vf for vfpu regs, v0 is a gpr. 2023-07-30 14:16:17 -07:00
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6819acd29f irjit: Fix flag on float cond move. 2023-07-30 14:16:17 -07:00
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5db6b11ef2 irjit: Cleanup self-fmovs. 
These were sometimes getting emitted.
 2023-07-30 14:16:17 -07:00
Henrik Rydgård
f0fd9e85aa Try dirtying CULL_PLANES in Execute_BoundingBox in SoftGPU 2023-07-30 18:35:18 +02:00
Henrik Rydgård
36951a0b98 Merge pull request #17806 from hrydgard/update-rcheevos 
Update to the latest version of rcheevos.
 2023-07-30 12:19:40 +02:00
Henrik Rydgård
1c05f71b50 Update to the latest version of rcheevos. 2023-07-30 11:58:55 +02:00
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c24e3ef831 riscv: Implement ll/sc. 2023-07-30 00:45:51 -07:00
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26a527bdf8 riscv: Implement float/int conversion. 2023-07-30 00:45:51 -07:00
Henrik Rydgård
b93275bb35 Merge pull request #17800 from unknownbrackets/riscv-jit 
More RISC-V jit ops
 2023-07-30 09:26:22 +02:00
Henrik Rydgård
c8447ff4b7 Merge pull request #17801 from unknownbrackets/irjit-vminmax 
irjit: Fix vmin/vmax nan handling
 2023-07-30 09:18:25 +02:00
Henrik Rydgård
180bda6f6b Merge pull request #17799 from unknownbrackets/irjit-lsu 
Add ll/sc to IR and x86jit
 2023-07-30 09:15:55 +02:00
Unknown W. Brackets
0036f3c494 riscv: Implement FMin/FMax. 2023-07-30 00:02:10 -07:00
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8e8081c686 riscv: Implement VFPU compares. 2023-07-30 00:02:10 -07:00
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9c9330a207 riscv: Implement float conditional move. 2023-07-30 00:02:10 -07:00
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70ff18a463 riscv: Implement count leading zeros. 2023-07-30 00:02:10 -07:00
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a5671bc716 riscv: Add simple debug log of missed ops. 2023-07-30 00:02:10 -07:00
Unknown W. Brackets
6aa4b0c5e1 irjit: Fix vmin/vmax nan handling. 
Should be relevant to NFS MW and possibly other game bugs.
 2023-07-29 19:13:12 -07:00
Unknown W. Brackets
6d4fb949c2 riscv: Implement float compare ops. 2023-07-29 19:02:15 -07:00
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6b632a103d riscv: Implement FSin/similar. 2023-07-29 19:02:15 -07:00
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921bd2391c riscv: Implement vi2s. 2023-07-29 19:02:15 -07:00
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e2765db4dc riscv: Implement division. 2023-07-29 19:02:15 -07:00
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f65b6fdb20 riscv: Remove incomplete block check. 
It shouldn't be necessary and bad things would happen anyway if it did.
 2023-07-29 19:02:15 -07:00