12621 Commits

Author	SHA1	Message	Date
Hoe Hao Cheng	805821e01e	Core: decouple UpdateScreenScale from preprocessor defines	2023-08-02 22:34:46 +08:00
Hoe Hao Cheng	0d7a1831b6	sdl: support HiDPI on wayland	2023-08-02 22:34:46 +08:00
Henrik Rydgård	cda59e8510	Vulkan: Keep track of some timestamps in a frame	2023-08-02 16:25:17 +02:00
Henrik Rydgård	0b4fee1259	One too much	2023-08-02 14:07:47 +02:00
Henrik Rydgård	c3511529e4	Somehow forgot to delete some unused bools	2023-08-02 14:07:05 +02:00
Henrik Rydgård	fc6879674e	Refactor overlays into an enum	2023-08-02 13:03:04 +02:00
Henrik Rydgård	9a8919810b	Translation cleanups	2023-08-01 13:04:52 +02:00
Henrik Rydgård	f45176fd25	Allow configuring in which corner achievement notifications can show up.	2023-08-01 12:52:09 +02:00
Henrik Rydgård	1071e1f248	Move towards separate types for leaderboard events	2023-08-01 11:57:28 +02:00
Bashar Astifan	401377818c	Merge branch 'master' into master	2023-08-01 05:29:56 +04:00
Henrik Rydgård	d268dd639a	Move the ScreenEdgePosition enum to a more appropriate location	2023-08-01 01:01:57 +02:00
Henrik Rydgård	3563d625b9	Allow configuring the location on-screen of leaderboard trackers.	2023-08-01 00:28:54 +02:00
Henrik Rydgård	48d577014a	Refactor the on-screen display to be more customizable	2023-08-01 00:28:54 +02:00
Henrik Rydgård	f39b9640b7	Rename the ChatPosition enum to a ScreenEdgePosition enum class (for future use)	2023-08-01 00:28:54 +02:00
Unknown W. Brackets	0d0029fc9d	riscv: Add bitmanip ops to disasm.	2023-07-30 17:45:36 -07:00
Unknown W. Brackets	c24dca12bb	Build: Fix link issue for rv64 disasm.	2023-07-30 16:06:55 -07:00
Unknown W. Brackets	b03398a46c	Merge pull request #17815 from unknownbrackets/riscv-jit ... riscv: Spill registers more intelligently	2023-07-30 14:49:37 -07:00
Henrik Rydgård	fa2b831dbc	Merge pull request #17814 from unknownbrackets/riscv-jit-debug ... riscv: Implement block debug interface	2023-07-30 23:42:14 +02:00
Henrik Rydgård	fa558b5b71	Merge pull request #17813 from unknownbrackets/riscv-jit-fixes ... Fix some typos and mistakes in RISC-V jit	2023-07-30 23:41:13 +02:00
Henrik Rydgård	100f7c838e	Merge pull request #17812 from unknownbrackets/irjit-floats ... Cleanup IR cond move flag, fmov to self	2023-07-30 23:36:37 +02:00
Unknown W. Brackets	f870271011	riscv: Spill registers more intelligently.	2023-07-30 14:24:12 -07:00
Unknown W. Brackets	020706f545	riscv: Implement float saturate clamping.	2023-07-30 14:24:12 -07:00
Unknown W. Brackets	45d44c1d4f	riscv: Implement block debug interface. ... This gives us the target disasm in jit compare, bloat, etc.	2023-07-30 14:21:43 -07:00
Unknown W. Brackets	5ef4b2b5fa	riscv: Fix assert when flushing not mapped reg.	2023-07-30 14:19:28 -07:00
Unknown W. Brackets	9f917488c3	riscv: Fix PC in disassembly.	2023-07-30 14:19:28 -07:00