2700 Commits

Author	SHA1	Message	Date
Unknown W. Brackets	4100767b5e	riscv: Optimize SetConst a bit.	2023-07-23 18:01:00 -07:00
Unknown W. Brackets	f7f7531500	riscv: Fix min/max normalization.	2023-07-23 18:01:00 -07:00
Unknown W. Brackets	34bfe93ea5	riscv: Fix block lookup issues.	2023-07-23 18:01:00 -07:00
Unknown W. Brackets	92694e765f	riscv: Implement conditional moves.	2023-07-23 18:01:00 -07:00
Unknown W. Brackets	2c7da94bd1	riscv: Implement shifts and compares.	2023-07-23 18:01:00 -07:00
Unknown W. Brackets	5ed2f0d559	riscv: Implement logic ops.	2023-07-23 18:01:00 -07:00
Unknown W. Brackets	94be343591	riscv: Try to keep regs normalized, track. ... Since we can't address the lower 32-bits only in compares, this can help us avoid renormalizing before a compare.	2023-07-23 18:01:00 -07:00
Unknown W. Brackets	7aafa11d24	riscv: Implement conditional exits.	2023-07-23 18:01:00 -07:00
Unknown W. Brackets	8ee73264bf	riscv: Correct depointerify on FlushAll().	2023-07-23 18:01:00 -07:00
Unknown W. Brackets	720f868a10	riscv: Use R_RA as a temporary for calls. ... This is the most logical thing, since we're about to write it anyway.	2023-07-23 18:01:00 -07:00
Unknown W. Brackets	76e3246065	riscv: Reduce jit codesize a bit.	2023-07-23 18:01:00 -07:00
Unknown W. Brackets	d31eded9ba	riscv: Allow dirty pointers, explicitly.	2023-07-23 18:01:00 -07:00
Unknown W. Brackets	624caa2dea	riscv: Implement the simplest exits.	2023-07-23 18:01:00 -07:00
Unknown W. Brackets	1dfedde741	riscv: Avoid needless save/load around compile.	2023-07-23 18:01:00 -07:00
Unknown W. Brackets	165169eb31	riscv: Implement load and store ops.	2023-07-23 18:01:00 -07:00
Unknown W. Brackets	c2da7d18bb	riscv: Stub out more IR compilation categories.	2023-07-23 18:01:00 -07:00
Unknown W. Brackets	05a2789cf4	riscv: Implement some simple assign instructions.	2023-07-23 18:01:00 -07:00
Unknown W. Brackets	c6c25af484	riscv: Add some safety to pointerifying. ... We have to clear the upper bits in case of sign extension or other things.	2023-07-23 18:01:00 -07:00
Unknown W. Brackets	bf7a6eb2cd	riscv: Add jit for some initial instructions.	2023-07-23 18:01:00 -07:00
Unknown W. Brackets	4c1cc2dfdc	riscv: Add a register cache for jit. ... Not yet actually used. Might be buggy.	2023-07-23 18:01:00 -07:00
Unknown W. Brackets	b2d3c750f1	irjit: Define a specific IRReg type.	2023-07-23 18:01:00 -07:00
Unknown W. Brackets	47b81985bd	riscv: Initial untested dispatcher. ... The minimum to actually, probably, running code. Pretty slow.	2023-07-23 18:01:00 -07:00
Unknown W. Brackets	e271e43ec5	riscv: Initial staffolding for IR based jit.	2023-07-23 18:01:00 -07:00
Unknown W. Brackets	3468423bb4	Debugger: Handle missing crash/block ptrs better.	2023-07-23 18:01:00 -07:00
Unknown W. Brackets	e4f9c72fe9	riscv: Avoid unaligned mem combine in IR.	2023-07-16 16:20:58 -07:00