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vkd3d-1.18
Commit Graph

1064 Commits

Author SHA1 Message Date
Giovanni Mascellani
ffbf0320ba tests/hlsl: Mark a denormalization mode test as todo on Intel. 
It behaves the same as llvmpipe.
 2025-11-17 15:20:47 +01:00
Anna (navi) Figueiredo Gomes
990be02cca vkd3d-shader/hlsl: Add a default value fail test with all allowed instructions. 
Co-Authored-By: Francisco Casas <fcasas@codeweavers.com>
 2025-11-17 15:15:47 +01:00
Giovanni Mascellani
7f377879fc vkd3d-shader/spirv: Clamp push constant CBV sizes to those of the push constant ranges backing them. 
Otherwise invalid SPIR-V may be generated, because the CBV field in
"push_cb_struct" may end up overlapping with a subsequent one.
 2025-11-12 15:24:30 +01:00
Giovanni Mascellani
2903831f79 tests/hlsl: Test using an SRV in combination with a CBV larger than the declared uniforms. 
This appears to be valid on native (no validation message is
raised) but is not properly handled by vkd3d.
 2025-11-12 15:19:33 +01:00
Henri Verbeet
4039168bca vkd3d-shader/hlsl: Consider scalars to be equivalent to 1-component vectors in hlsl_add_conditional(). 2025-11-12 15:12:30 +01:00
Giovanni Mascellani
7022bb57fc tests/shader_runner_metal: Implement explicit descriptor mapping. 2025-11-12 15:02:58 +01:00
Francisco Casas
5dc96ab8d6 tests/hlsl: Test which shader models allow FOG and PSIZE. 2025-11-10 15:54:18 +01:00
Shaun Ren
58d02da892 vkd3d-shader/hlsl: Use a bool type for "new_cond" in lower_conditional_block_discard_nz(). 
This fixes the assertion error

    "sm4_generate_vsir_instr_expr Failed assertion: dst_type->e.numeric.type == HLSL_TYPE_BOOL"

which occurs when compiling the following HLSL shader using the ps_4_0 target profile:

    uniform float4 x;
    uniform bool b;

    float4 main() : SV_Target
    {
        if (!b)
            clip(x.x);
        else
            clip(x.y);

        return x;
    }
 2025-11-10 15:51:26 +01:00
Henri Verbeet
74ebd4621f vkd3d-shader/msl: Implement VSIR_OP_FIRSTBIT_HI. 2025-11-04 14:59:38 +01:00
Henri Verbeet
c576a09d57 vkd3d-shader/msl: Implement VSIR_OP_FIRSTBIT_LO. 2025-11-04 14:59:38 +01:00
Henri Verbeet
08026880d6 vkd3d-shader/msl: Implement VSIR_OP_COUNTBITS. 2025-11-04 14:59:38 +01:00
Henri Verbeet
f431cddc9f vkd3d-shader/msl: Implement support for VKD3DSPR_IMMCONSTBUFFER registers. 2025-11-04 14:59:38 +01:00
Henri Verbeet
51cce61770 vkd3d-shader/msl: Implement VSIR_OP_SYNC. 2025-11-04 14:59:38 +01:00
Giovanni Mascellani
12c713bbfa tests/hlsl: Do not execute 64-bit wave bitwise operations on WARP. 
They are known to be buggy on the CI machine.
 2025-11-03 17:52:32 +01:00
Giovanni Mascellani
b835510010 tests/hlsl: Test shader model 6.2 denormal mode for 16-bit and 64-bit floats. 2025-10-30 19:12:39 +01:00
Giovanni Mascellani
69c109786b tests/hlsl: Test shader model 6.2 denormal mode for 32-bit floats. 2025-10-30 19:12:27 +01:00
Giovanni Mascellani
da6ce78c1c tests/shader_runner: Add support for testing explicit descriptor mapping. 
When no descriptor mapping is specified, the backend will just
build the usual default mapping. Otherwise the explicit mapping
is used.

Once all backends support the explicit mapping, we'll be able to
handle generating the default mapping in the shader runner core
rather than having each backend implement its own algorithm.

So far only the d3d12 backend supports explicit descriptor
mapping.
 2025-10-30 18:42:35 +01:00
Giovanni Mascellani
cc1db404b0 vkd3d-shader/msl: Implement support for VKD3DSPR_UNDEF registers. 
MSL doesn't seem to have any special handling for undefined values,
differently from SPIR-V. Thus we just emit zeros.

UNDEF registers are sometimes created by the DXIL parser,
for example in sm6_parser_emit_composite_construct().
 2025-10-30 18:18:14 +01:00
Shaun Ren
59b87c769a vkd3d-shader/hlsl: Flatten conditional blocks containing discard_neg instructions. 
For any `discard_neg c` instruction in a conditional block, we replace c with
    cond ? c : 0    in a then block,
and
    cond ? 0 : c    in an else block.
 2025-10-30 17:46:12 +01:00
Shaun Ren
787d49d6d8 vkd3d-shader/hlsl: Flatten conditional blocks containing discard_nz instructions. 
For any `discard_nz c` instruction in a conditional block, we replace c with
    (cond && c)     in a then block,
and
    (!cond && c)    in an else block.
 2025-10-30 17:46:12 +01:00
Shaun Ren
4d5a1528ab vkd3d-shader/hlsl: Flatten conditional branches containing stores. 
For an if block

    if (cond)
    {
        <then_block>
    }
    else
    {
        <else_block>
    }

We flatten it by first replacing any store instruction `v[[k]] = x`
in the then_block with the following:

    1: load(v[[k]])
    2: cond ? x : @1
    3: v[[k]] = @2

Similarly, we replace any store instruction `v[[k]] = x` in the
else_block with the following:

    1: load(v[[k]])
    2: cond ? @1 : x
    3: v[[k]] = @2

Then we can concatenate <then_block> and <else_block> together and
get rid of the if block.
 2025-10-30 17:46:12 +01:00
Shaun Ren
200e66ba4f vkd3d-shader/hlsl: Store the flatten type in struct hlsl_ir_if. 2025-10-30 17:46:12 +01:00
Shaun Ren
2ba53e06fa tests/hlsl: Add some conditional flattening tests. 2025-10-30 17:46:04 +01:00
Francisco Casas
32b622d7a5 vkd3d-shader/dxil: Also map destination write masks for system values. 
Currently, on what we consider normalized vsir, destination write masks
are not relative to the signature element's mask, even though source
swizzles are. Also for most instructions, the source swizzles are masked
by the destination write mask, as given by vsir_src_is_masked().

The DXIL parser however, is not derelativizing the destination write
masks for system value signature elements, so we fix that to make it
consistent with how other front-ends are handled.

For instance, when the test introduced in commit
ca5bc63e5e is compiled to DXIL using DXC,
and then parsed using vkd3d-compiler, we get the following store
instructions:

    vs_6_0
    .input
    .param POSITION.xyzw, v0.xyzw, float
    .output
    .param SV_Position.xyzw, o0.xyzw, float, POS
    .param SV_CullDistance.x, o1.x, float, CULLDST
    .param SV_ClipDistance.y, o1.y, float, CLIPDST
    .descriptors
    .text
    label l1
        ...
        mov o1.x <v4:f32>, sr1 <s:f32>
        mov o2.x <v4:f32>, sr2 <s:f32> // Note the .x write mask!
        ret

whereas, when compiling using FXC and parsing the TPF using
vkd3d-compiler we get:

    vs_4_0
    .input
    .param POSITION.xyzw, v0.xyzw, float
    .output
    .param SV_POSITION.xyzw, o0.xyzw, float, POS
    .param SV_CULLDISTANCE.x, o1.x, float, CULLDST
    .param SV_CLIPDISTANCE.y, o1.y, float, CLIPDST
    .descriptors
    .text
    label l1
        mov o0.xyzw <v4:f32>, v0.xyzw <v4:f32>
        mov o1.x <v4:f32>, v0.x <v4:f32>
        mov o2.y <v4:f32>, v0.y <v4:f32> // Note the .y write mask.
        ret

This only really matters for cases where we have a system value semantic
whose mask doesn't start at .x, which is very rare. For instance, it
requires the clip/cull distance combo, which share registers, so one of
them pushes the other to start on another component.

According to the tests, the only thing relying on this behaviour is the
handling of private variables for system value semantics on the SPIR-V
backend, which expects destination write masks as if the element started
at .x even though it might not. This is modified then.
 2025-10-29 13:14:54 +01:00
Francisco Casas
ca5bc63e5e tests/hlsl: Add a simpler clip/cull distance test. 2025-10-29 12:26:33 +01:00