Commit Graph

7728 Commits

Author SHA1 Message Date
Giovanni Mascellani
bda2be3423 vkd3d-shader/hlsl: Reject programs with group shared variables.
Currently the modifier is ignored and the program is miscompiled.
2025-06-05 15:50:04 +02:00
Giovanni Mascellani
0236308866 tests/hlsl: Test minimum precision IDXTEMP registers. 2025-06-05 15:50:01 +02:00
Giovanni Mascellani
f1b36edc07 ci: Enable testing with DXC again on macOS.
This was disabled by commit 653e4f47ac.
2025-06-04 13:07:17 +02:00
Giovanni Mascellani
a4c727ac40 tests: Mark some tests in calculate-lod.shader_test as buggy on MoltenVK < 1.2.11. 2025-06-04 13:04:53 +02:00
Giovanni Mascellani
c82d1aac4d tests: Mark some tests in arithmetic-int-uniform.shader_test as buggy on MoltenVK < 1.2.11.
The bug is already solved on recent MoltenVK versions, but the CI
is stuck with 1.2.9, so it's useful to filter these failures out.
2025-06-04 13:04:53 +02:00
Giovanni Mascellani
7f04060f33 vkd3d-shader/dxil: Handle 16-bit values uniformly in sm6_map_cast_op().
This makes the logic more transparent, and it eases handling
native 16-bit values once they will be supported.
2025-06-04 13:03:57 +02:00
Giovanni Mascellani
b9ce828451 vkd3d-shader/dxil: Validate that floating-point extension casts increase bit width. 2025-06-04 13:01:51 +02:00
Giovanni Mascellani
a91fb0523a vkd3d-shader/dxil: Validate that integer extension casts increase bit width. 2025-06-04 13:01:51 +02:00
Giovanni Mascellani
a90b74baaa vkd3d-shader/dxil: Validate that floating-point truncation casts decrease bit width.
Similarly to the integer case.
2025-06-04 13:01:45 +02:00
Giovanni Mascellani
0e006715d8 vkd3d-shader/dxil: Do not use field "reg" in of sm6_value when writing bitcasts.
It's going to be removed; the generated register data type is the
right thing to look at here.
2025-06-04 12:34:21 +02:00
Elizabeth Figura
9552dab5aa vkd3d-shader: Use the correct union members for raw and structured resources. 2025-06-04 12:10:39 +02:00
Henri Verbeet
85d2703c03 tests/shader_runner: Introduce a "tessellation-shader" cap.
Similar to how we have the "geometry-shader" cap. In principle shader
model 5+ implies support for tessellation shaders, but the Vulkan,
OpenGL, and Metal runners are able to support most of shader model 5+
without the underlying GPU (or API) necessarily supporting tessellation
shaders.
2025-06-04 12:10:10 +02:00
Shaun Ren
2b257caea9 vkd3d-shader/hlsl: Don't optimize semantic register allocations in SM1.
This matches the behaviour of fxc/d3dcompiler.
2025-06-02 20:53:00 +02:00
Nikolay Sivov
b6ef417e71 vkd3d-shader/fx: Handle bool types when parsing fx_2_0 assignment values. 2025-06-02 20:51:38 +02:00
Nikolay Sivov
c895f63a1c vkd3d-shader/fx: Fix a crash in fx -> d3d-asm when named values are not defined. 2025-06-02 20:51:38 +02:00
Nikolay Sivov
108f4fe47e vkd3d-shader/fx: Fix reading the assignment value base type when parsing fx_2_0. 2025-06-02 20:51:33 +02:00
Nikolay Sivov
4e2fefdfdf vkd3d-shader/fx: Use correct array sizes for the fx_2_0 states. 2025-06-02 20:43:44 +02:00
Nikolay Sivov
4ef4baa6bf vkd3d-shader/fx: Fix some typos in fx_2_0 state names. 2025-06-02 20:43:44 +02:00
Nikolay Sivov
68386f5180 vkd3d-shader/fx: Print packoffset() modifiers in fx -> d3d-asm output.
Signed-off-by: Nikolay Sivov <nsivov@codeweavers.com>
2025-06-02 20:43:44 +02:00
Nikolay Sivov
6b2800fa99 vkd3d-shader/fx: Print explicit buffer bind points in fx -> d3d-asm output.
Signed-off-by: Nikolay Sivov <nsivov@codeweavers.com>
2025-06-02 20:43:27 +02:00
Nikolay Sivov
e33189546a vkd3d-shader/fx: Use variable unpacked size when setting buffer sizes.
Signed-off-by: Nikolay Sivov <nsivov@codeweavers.com>
2025-06-02 20:41:37 +02:00
Giovanni Mascellani
9f0185f304 vkd3d-shader/msl: Support the ABSNEG source modifier. 2025-06-02 20:36:42 +02:00
Giovanni Mascellani
bc0dd891c3 vkd3d-shader/glsl: Support the ABSNEG source modifier. 2025-06-02 20:35:48 +02:00
Giovanni Mascellani
ed60dd5926 tests: Add a test for the ABSNEG source modifier. 2025-06-02 20:33:13 +02:00
Giovanni Mascellani
10be58a74f vkd3d-shader/msl: Ignore the PARTIALPRECISION destination modifier. 2025-06-02 20:33:01 +02:00