Commit Graph

4119 Commits

Author SHA1 Message Date
Giovanni Mascellani
1d88638bd3 vkd3d-shader/dxil: Rename VALUE_TYPE_ICB to VALUE_TYPE_DATA.
And other related identifiers similarly.

Currently we use VALUE_TYPE_ICB to indicate a raw chunk of data
(which can be used as an immediate constant buffer, but also for
initializing an indexable temporary) and VALUE_TYPE_REG with
register type VKD3DSPR_IMMCONSTBUFFER to indicate an actual ICB
register.

Since we are now switching to represent the register type directly
in the SM6 value, it seems sensible to use VALUE_TYPE_ICB for an
ICB register. Indeed, since what we're currently describing with
VALUE_TYPE_ICB is not necessarily related to an ICB register, it
makes sense to use a more general name, which is therefore being
introduced with this commit.
2025-05-12 15:24:23 +02:00
Nikolay Sivov
960244bf1e vkd3d-shader/fx: Use appropriate BlendState description when tracing.
Signed-off-by: Nikolay Sivov <nsivov@codeweavers.com>
2025-05-06 19:01:09 +02:00
Nikolay Sivov
5d5d892830 vkd3d-shader/fx: Use the same BlendState states description for both fx_4_1 and fx_5_0.
Signed-off-by: Nikolay Sivov <nsivov@codeweavers.com>
2025-05-06 18:58:03 +02:00
Giovanni Mascellani
fd1f74f44d vkd3d-shader/dxil: Generate INVALID values in sm6_parser_emit_unhandled(). 2025-05-06 18:55:19 +02:00
Giovanni Mascellani
44e0b17606 vkd3d-shader/dxil: Generate INVALID values in sm6_parser_constants_init(). 2025-05-06 18:55:18 +02:00
Giovanni Mascellani
7381598310 vkd3d-shader/dxil: Generate UNDEFINED values in sm6_parser_constants_init().
VALUE_TYPE_UNDEFINED means that a value is explicitly undefined,
equivalently to what was first represented with is_undefined.
VALUE_TYPE_INVALID will be introduced for values that arise from
invalid programs.
2025-05-06 18:55:18 +02:00
Giovanni Mascellani
e9e02884e5 vkd3d-shader/dxil: Generate SSA values in sm6_parser_emit_phi(). 2025-05-06 18:55:18 +02:00
Giovanni Mascellani
7c344bdfd0 vkd3d-shader/dxil: Generate SSA values in sm6_parser_emit_cmpxchg(). 2025-05-06 18:55:18 +02:00
Giovanni Mascellani
326f3624d9 vkd3d-shader/dxil: Generate SSA values in sm6_parser_emit_dx_sincos(). 2025-05-06 18:55:18 +02:00
Giovanni Mascellani
527c1518f2 vkd3d-shader/dxil: Generate SSA values in sm6_parser_emit_dx_atomic_binop(). 2025-05-06 18:55:18 +02:00
Giovanni Mascellani
4289ec60a1 vkd3d-shader/dxil: Do not encode the offset twice for structured TGSM loads.
Currently structured TGSM loads are encoded to something like this:

    ld_structured sr12 <s:float>, sr1 <s:uint>, l(0) <s:uint>, g0[sr1 <s:uint> + 0] <s:float>

Notice how the TGSM offset, expressed by sr1, is encoded twice in
the instruction. In TPF there is no expectation of two indices
in the resource source, so let's avoid producing it for DXIL as
well. The same instruction will therefore become:

    ld_structured sr12 <s:float>, sr1 <s:uint>, l(0) <s:uint>, g0 <s:float>
2025-05-05 15:14:26 +02:00
Giovanni Mascellani
9fdaee1529 vkd3d-shader/dxil: Generate SSA values in sm6_parser_emit_binop(). 2025-05-05 15:10:15 +02:00
Giovanni Mascellani
31f8ed1d1e vkd3d-shader/dxil: Generate SSA values in sm6_parser_emit_atomicrmw(). 2025-05-05 15:10:15 +02:00
Giovanni Mascellani
fae03b2ba5 vkd3d-shader/dxil: Generate SSA values in instruction_dst_param_init_ssa_scalar(). 2025-05-05 15:10:15 +02:00
Giovanni Mascellani
bd73de7198 vkd3d-shader/dxil: Generate SSA values in instruction_dst_param_init_ssa_vector(). 2025-05-05 15:10:14 +02:00
Giovanni Mascellani
b8c6092a16 vkd3d-shader/dxil: Generate SSA values in sm6_parser_get_value_idx_by_ref(). 2025-05-05 15:08:29 +02:00
Giovanni Mascellani
9e7ad75944 vkd3d-shader/dxil: Move the VSIR register in the SM6 value outside of the union.
It will eventually disappear, but while it's replaced with other
union members it shouldn't interfere with them.
2025-05-05 15:02:58 +02:00
Giovanni Mascellani
648a60d4c8 vkd3d-shader/dxil: Introduce a uniform interface to synthesize a register from a SM6 value. 2025-05-05 15:02:57 +02:00
Giovanni Mascellani
8b58ce9e85 vkd3d-shader/dxil: Have sm6_parser_emit_reg_composite_construct() accept an array of registers.
Rather than an array of pointers to registers. This makes it nicer
to use with registers that are synthesized on the fly, a situation
that already exists and is likely to become more common in future
commits.
2025-05-05 15:01:36 +02:00
Shaun Ren
5b06fe83df vkd3d-shader/hlsl: Generate vsir instructions for stream output operations. 2025-05-05 14:54:07 +02:00
Shaun Ren
c8c1e270e0 vkd3d-shader/hlsl: Validate maximum output size in geometry shaders. 2025-05-05 14:43:53 +02:00
Shaun Ren
729a3ac089 vkd3d-shader/hlsl: Append output copies for stream output Append() invocations. 2025-05-05 14:30:16 +02:00
Shaun Ren
34b4b34f2c vkd3d-shader/hlsl: Use a block in append_output_copy*(). 2025-05-05 14:30:16 +02:00
Francisco Casas
b89f0bc730 vkd3d-shader/hlsl: Generate vsir for HLSL_IR_SYNC operations.
The following table shows how each intrinsic maps to d3d assembly and the
flags that appear in the tpf bytecode, in binary.

    GroupMemoryBarrier()                   sync_g               0010
    GroupMemoryBarrierWithGroupSync()      sync_g_t             0011
    DeviceMemoryBarrier()                  sync_uglobal         1000
    DeviceMemoryBarrierWithGroupSync()     sync_uglobal_t       1001
    AllMemoryBarrier()                     sync_uglobal_g       1010
    AllMemoryBarrierWithGroupSync()        sync_uglobal_g_t     1011
2025-05-05 14:17:47 +02:00
Francisco Casas
a975c56695 vkd3d-shader/hlsl: Mark stores dirty on interlocked operation in vectorize_stores(). 2025-05-05 14:15:23 +02:00