Commit Graph

346 Commits

Author SHA1 Message Date
bd34ec1fb3 vkd3d-shader/hlsl: Emit the minimum-precision SFI0 flag. 2025-03-06 17:15:15 +01:00
6cdfe38319 vkd3d-shader/hlsl: Emit minimum-precision signatures. 2025-03-06 17:15:15 +01:00
665c29f0be vkd3d-shader/tpf: Allow I/O index ranges to not intersect a signature element for a given register.
The current TPF validator enforces that for each register involved
in a DCL_INDEX_RANGE instruction there must be a signature element
for that register and the DCL_INDEX_RANGE write mask. This is an
excessively strong request, and causes some shaders from The Falconeer
to be invalidly rejected.

The excessively strong check was needed to avoid triggering a bug
in the I/O normaliser. Since that bug is now solved, the check
can be relaxed.
2025-02-19 17:30:25 +01:00
f127f0849e vkd3d-shader/hlsl: Generate vsir signature entries for patch variables. 2025-02-03 16:04:21 +01:00
aa29d0a2e5 vkd3d-shader/tpf: Improve readability of compat mapping in sm4_sysval_semantic_from_semantic_name(). 2025-02-03 16:04:21 +01:00
802d7317cb vkd3d-shader/hlsl: Implement the InterlockedXor() intrinsic. 2025-01-20 15:42:45 +01:00
cbd504e888 vkd3d-shader/hlsl: Implement the InterlockedOr() intrinsic. 2025-01-20 15:42:45 +01:00
5b9634a7b7 vkd3d-shader/hlsl: Implement the InterlockedMin() intrinsic. 2025-01-20 15:42:43 +01:00
63fbe161f2 vkd3d-shader/hlsl: Implement the InterlockedMax() intrinsic. 2025-01-20 15:42:07 +01:00
b447fdce51 vkd3d-shader/hlsl: Implement the InterlockedExchange() intrinsic. 2025-01-20 15:41:07 +01:00
3fb47373a1 vkd3d-shader/hlsl: Implement the InterlockedCompareStore() intrinsic. 2025-01-20 15:41:07 +01:00
22ab08f4d8 vkd3d-shader/hlsl: Implement the InterlockedCompareExchange() intrinsic. 2025-01-20 15:41:07 +01:00
3b19a4aaf3 vkd3d-shader/hlsl: Implement the InterlockedAnd() intrinsic. 2025-01-20 15:41:07 +01:00
660a71ef22 vkd3d-shader/hlsl: Implement the InterlockedAdd() intrinsic. 2025-01-20 15:40:34 +01:00
4227858cfe vkd3d-shader/hlsl: Move RDEF generation to hlsl_codegen.c. 2025-01-10 20:03:14 +01:00
29bac62ba2 vkd3d-shader/hlsl: Move the "dimx" and "dimy" fields to the type-specific union. 2025-01-10 19:38:13 +01:00
1ff1a51e4b vkd3d-shader/hlsl: Avoid some uses of the default case when switching over hlsl_base_type.
Since we have -Wswitch, this forces the developer to update all relevant
switches when an enum case is added.

Places where the default is just a FIXME are left alone.
2025-01-10 19:24:10 +01:00
45d9a097e6 vkd3d-shader/hlsl: Move sm4_free_extern_resources() to hlsl_codegen.c. 2024-12-19 21:09:32 +01:00
b143754360 vkd3d-shader/hlsl: Move sm4_get_extern_resources() to hlsl_codegen.c. 2024-12-19 21:09:32 +01:00
f09ac4959e vkd3d-shader/hlsl: Implement the GatherCmp() methods. 2024-12-18 17:27:43 +01:00
64126a00c3 vkd3d-shader/ir: Give more meaningful names to I/O normalisation levels.
The previous names "not normalised" and "fully normalised" have meanings
which are likely to change with time. OTOH including a description of the
normalisation level in the enumerant seems excessive. Relating
normalisation levels to shader model versions might be a reasonable
compromise.
2024-12-12 17:21:49 +01:00
65b67e84a8 vkd3d-shader/tpf: Remove hlsl_ctx from tpf_compiler.
This completes the hlsl->vsir->tpf translation.
2024-12-10 15:52:52 +01:00
f22729461e vkd3d-shader/hlsl: Store hull and domain shader properties in vsir_program.
The alternative to adding the vsir_program->tess_output_primitive and
vsir_program->tess_partitioning fields would be to emit the vsir
DCL_TESSELLATOR_OUTPUT_PRIMITIVE and DCL_TESSELLATOR_PARTITIONING
instructions, like DXIL does, but I think that the preference is to store
these kind of data directly in the vsir_program.
2024-12-10 15:52:52 +01:00
ca9bb2e089 vkd3d-shader/hlsl: Generate RDEF outside tpf_compile(). 2024-12-10 15:52:52 +01:00
ecddc39b31 vkd3d-shader/hlsl: Store SM4 constant buffer declarations in vsir program. 2024-12-10 15:52:52 +01:00