Commit Graph

597 Commits

Author SHA1 Message Date
ec6b4ed4ff vkd3d-shader/hlsl: Generate vsir registers from patch variable derefs. 2025-02-03 16:36:16 +01:00
2a1e3b100b vkd3d-shader/hlsl: Allocate semantic registers for patch variables. 2025-02-03 16:15:11 +01:00
2ddbc69f1a vkd3d-shader/hlsl: Declare semantics for patch variables in vsir. 2025-02-03 16:15:03 +01:00
f127f0849e vkd3d-shader/hlsl: Generate vsir signature entries for patch variables. 2025-02-03 16:04:21 +01:00
29abe73918 vkd3d-shader/hlsl: Implement input semantic variable copies for patch variables.
The semantic variables from a patch parameter are split as usual, with
the difference being that the semantic variable being added is a patch
variable itself, with the type being the split variable type, and its
number of control points being equal to the original patch variable's
number of control points. It is then stored in the original patch
variable as follows:

  for (i = 0; i < n; ++i)
      patch[i][f] := <inputpatch-sem-var>[i]

where n is the number of control points of "patch", and f is the field
index in patch corresponding to "<inputpatch-sem-var>".

We use special prefixes, "inputpatch-" or "outputpatch-", when adding
the semantic patch variables, in order to distinguish them from
non-patch semantic variables of the same name.
2025-02-03 16:04:11 +01:00
f5d216835a vkd3d-shader/hlsl: Add an "is_patch_constant_func" field to struct hlsl_ctx.
In anticipation of the need for is_patch_constant_func in
sm4_generate_vsir_reg_from_deref(), in order to generate vsir
registers from InputPatch/OutputPatch dereferences.
2025-02-03 16:00:38 +01:00
f064a4022a vkd3d-shader/hlsl: Validate and record InputPatch/OutputPatch types. 2025-01-29 17:45:46 +01:00
f4d5e05d96 vkd3d-shader/hlsl: Parse InputPatch and OutputPatch objects. 2025-01-29 17:41:51 +01:00
c2e224c5fb vkd3d-shader/hlsl: Delay lowering complex casts until after parse time.
While so far it has been posible to do this at parse time, this must
happen after knowing if the complex cast is on the lhs or not.

The modified tests show that before this patch we are currently
miscompiling when this happens, because a complex lhs cast is transformed
into a load, and add_assigment() just stores to the generated "cast"
temp.
2025-01-22 14:34:19 +01:00
802d7317cb vkd3d-shader/hlsl: Implement the InterlockedXor() intrinsic. 2025-01-20 15:42:45 +01:00
cbd504e888 vkd3d-shader/hlsl: Implement the InterlockedOr() intrinsic. 2025-01-20 15:42:45 +01:00
5b9634a7b7 vkd3d-shader/hlsl: Implement the InterlockedMin() intrinsic. 2025-01-20 15:42:43 +01:00
63fbe161f2 vkd3d-shader/hlsl: Implement the InterlockedMax() intrinsic. 2025-01-20 15:42:07 +01:00
b447fdce51 vkd3d-shader/hlsl: Implement the InterlockedExchange() intrinsic. 2025-01-20 15:41:07 +01:00
3fb47373a1 vkd3d-shader/hlsl: Implement the InterlockedCompareStore() intrinsic. 2025-01-20 15:41:07 +01:00
22ab08f4d8 vkd3d-shader/hlsl: Implement the InterlockedCompareExchange() intrinsic. 2025-01-20 15:41:07 +01:00
3b19a4aaf3 vkd3d-shader/hlsl: Implement the InterlockedAnd() intrinsic. 2025-01-20 15:41:07 +01:00
660a71ef22 vkd3d-shader/hlsl: Implement the InterlockedAdd() intrinsic. 2025-01-20 15:40:34 +01:00
a082daeb56 vkd3d-shader/hlsl: Implement the isinf() intrinsic.
Signed-off-by: Nikolay Sivov <nsivov@codeweavers.com>
2025-01-16 19:25:02 +01:00
cf19b4da49 vkd3d-shader/hlsl: Specialize lowering SM1 casts to int for vertex shaders.
Vertex shaders do not have CMP, so we use SLT and MAD.

For example, this vertex shader:

    uniform float4 f;

    void main(inout float4 pos : position, out float4 t1 : TEXCOORD1)
    {
        t1 = (int4)f;
    }

results in:

    vs_2_0
    dcl_position v0
    slt r0, c0, -c0
    frc r1, c0
    add r2, -r1, c0
    slt r1, -r1, r1
    mad oT1, r0, r1, r2
    mov oPos, v0

while we have the lower_cmp() pass, each time it is applied many
instructions are generated, so this patch introduces a specialized
version of the cast-to-int lowering for efficiency.
2025-01-16 18:48:35 +01:00
2d91bd9200 vkd3d-shader/hlsl: Properly lower casts to int for negative numbers.
While it looks complicated, it is what fxc/d3dcompiler does.

A shader as simple as:

    float4 f;

    float4 main() : sv_target
    {
        return (int4)f;
    }

results in the following instructions:

    ps_2_0
    def c1, 0, 1, 0, 0
    frc r0, c0
    cmp r1, -r0, c1.x, c1.y
    add r0, -r0, c0
    mov r2, c0
    cmp r1, r2, c1.x, r1
    add r0, r0, r1
    mov oC0, r0
2025-01-16 18:46:49 +01:00
efd7f2e014 vkd3d-shader/hlsl: Don't lower separate samples with texel offsets. 2025-01-14 17:59:50 +01:00
0a5955372a vkd3d-shader/hlsl: Lower separate SampleGrad() for SM1. 2025-01-14 17:59:50 +01:00
4227858cfe vkd3d-shader/hlsl: Move RDEF generation to hlsl_codegen.c. 2025-01-10 20:03:14 +01:00
7b23cd4d3c vkd3d-shader: Avoid passing NULL to qsort(). (ubsan)
Otherwise ubsan reports runtime errors such as:

    libs/vkd3d-shader/ir.c:4731:5: runtime error: null pointer passed as argument 1, which is declared to never be null
2025-01-10 19:51:55 +01:00