vkd3d/tests/hlsl/uav-rwbuffer.shader_test

[require]
shader model >= 5.0

% UAVs are implicitly allocated starting from the highest render target slot.
% They cannot overlap render target slots, and also cannot be allocated any
% lower than the highest render target.
% This ceases to be true with shader model 5.1.

[rtv 1]
format r32g32b32a32-float
size (2d, 640, 480)

[pixel shader]
struct s
{
    float3 a;
};

RWBuffer<float4> u : register(u2);
RWBuffer<float> u1;
RWBuffer<float2x2> u2;
RWBuffer<struct s> u3;

float4 main() : sv_target1
{
    u[0] = float4(11.1, 12.2, 13.3, 14.4);
    return 0;
}

[pixel shader]
struct s
{
    float3 a;
};

RasterizerOrderedBuffer<float4> u : register(u2);
RasterizerOrderedBuffer<float> u1;
RasterizerOrderedBuffer<float2x2> u2;
RasterizerOrderedBuffer<struct s> u3;

float4 main() : sv_target1
{
    u[0] = float4(11.1, 12.2, 13.3, 14.4);
    return 0;
}

% Type size is too wide
[pixel shader fail]
struct s
{
    float3 a;
    float2 b;
};
RWBuffer<struct s> u;

float4 main() : sv_target1
{
    return 0;
}

[pixel shader fail(sm<6) todo]
RWBuffer<double3> u;

float4 main() : sv_target1
{
    return 0;
}

[pixel shader]
RWBuffer<double2> u;

float4 main() : sv_target1
{
    return 0;
}

[pixel shader fail]
struct s
{
    float3 a;
    float2 b;
};
RasterizerOrderedBuffer<struct s> u;

float4 main() : sv_target1
{
    return 0;
}

[pixel shader fail(sm<6) todo]
RasterizerOrderedBuffer<double3> u;

float4 main() : sv_target1
{
    return 0;
}

[pixel shader]
RasterizerOrderedBuffer<double2> u;

float4 main() : sv_target1
{
    return 0;
}

% Array type
[pixel shader fail(sm<6)]
typedef float arr[2];
RWBuffer<arr> u;

float4 main() : sv_target1
{
    return 0;
}

% Object types
[pixel shader fail(sm<6)]
RWBuffer<Texture2D> u;

float4 main() : sv_target1
{
    return 0;
}

[pixel shader fail]
struct s
{
    Texture2D t;
};
RWBuffer<struct s> u;

float4 main() : sv_target1
{
    return 0;
}

[pixel shader fail(sm<6)]
typedef float arr[2];
RasterizerOrderedBuffer<arr> u;

float4 main() : sv_target1
{
    return 0;
}

% Object types
[pixel shader fail(sm<6)]
RasterizerOrderedBuffer<Texture2D> u;

float4 main() : sv_target1
{
    return 0;
}

[pixel shader fail]
struct s
{
    Texture2D t;
};
RasterizerOrderedBuffer<struct s> u;

float4 main() : sv_target1
{
    return 0;
}


[require]
shader model >= 5.0

[uav 1]
format r32g32b32a32-sint
size (buffer, 2)
1 2 3 4 5 6 7 8

[pixel shader]
RWBuffer<int4> u : register(u1);

float4 main() : sv_target
{
    u[0] = int4(11, -12, 13, -14);
    u[1] = int4(-15, 16, -17, 18);
    return 0;
}

[test]
draw quad
probe uav 1 (0) i32(11, -12, 13, -14)
probe uav 1 (1) i32(-15, 16, -17, 18)

[uav 2]
format r32g32b32a32-float
size (buffer, 1)
0.1 0.2 0.3 0.4

[pixel shader]
RWBuffer<float4> u : register(u2);

float4 main() : sv_target1
{
    u[0] = float4(11.1, 12.2, 13.3, 14.4);
    return 0;
}

[test]
draw quad
probe uav 2 (0) f32(11.1, 12.2, 13.3, 14.4)

[require]
shader model >= 6.2
native-16-bit

[uav 1]
format r32g32b32a32-float
size (buffer, 1)
0 0 0 0

[compute shader]
uniform half4 h;
RWBuffer<float4> u : register(u1);

    [numthreads(1, 1, 1)]
void main()
{
    u[0] = h;
}

[test]
uniform 0 uint4 0x4a204990 0x4b404ab0 0 0
dispatch 1 1 1
probe uav 1 (0) f32(11.125, 12.25, 13.375, 14.5)

[compute shader]
uniform half4 h;
RWBuffer<half4> u : register(u1);

    [numthreads(1, 1, 1)]
void main()
{
    u[0] = h;
}

[test]
uniform 0 uint4 0x4a204990 0x4b404ab0 0 0
dispatch 1 1 1
probe uav 1 (0) f32(11.125, 12.25, 13.375, 14.5)

[compute shader]
uniform half h;
RWBuffer<half> u : register(u1);

    [numthreads(1, 1, 1)]
void main()
{
    u[0] = h;
}

[test]
uniform 0 uint 0x4990
dispatch 1 1 1
probe uav 1 (0) f32(11.125)

[uav 1]
format r32g32b32a32-uint
size (buffer, 1)
0 0 0 0

[compute shader]
uniform uint16_t4 h;
RWBuffer<uint16_t4> u : register(u1);

    [numthreads(1, 1, 1)]
void main()
{
    u[0] = h;
}

[test]
% Even if everything is defined as unsigned, implementations differ: WARP and
% NVIDIA zero-extend, while AMD sign-extends; therefore we test neither.
uniform 0 uint4 0x7ff4000b 0xe7ff3 0 0
dispatch 1 1 1
probe uav 1 (0) u32(0xb, 0x7ff4, 0x7ff3, 0xe)

[uav 1]
format r32g32b32a32-sint
size (buffer, 1)
0 0 0 0

[compute shader]
uniform int16_t4 h;
RWBuffer<int16_t4> u : register(u1);

    [numthreads(1, 1, 1)]
void main()
{
    u[0] = h;
}

[test]
% Again, implementations behave inconsistently for negative numbers.
uniform 0 uint4 0x7ff4000b 0xe7ff3 0 0
dispatch 1 1 1
probe uav 1 (0) i32(11, 0x7ff4, 0x7ff3, 14)

[uav 1]
format r32g32b32a32-sint
size (buffer, 1)
-100 -1 1 100

[pixel shader]
RWBuffer<int16_t4> u : register(u1);

int4 main() : sv_target
{
    return u[0];
}

[test]
draw quad
probe (0, 0) i32(-100, -1, 1, 100)

[uav 1]
format r32g32b32a32-uint
size (buffer, 1)
0 1 10 100

[pixel shader]
RWBuffer<uint16_t4> u : register(u1);

uint4 main() : sv_target
{
    return u[0];
}

[test]
draw quad
probe (0, 0) u32(0, 1, 10, 100)