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fix(iso14443b): add WDT_HIT and timeout to DMA receive loop

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In Get14443bAnswerFromTag(), the behindBy == 0 idle loop (waiting for
FPGA DMA samples) had no watchdog kick, no button check, and no
timeout. If the FPGA stops providing the SSC clock, this loop spins
infinitely until the hardware watchdog triggers a reboot.

Add WDT_HIT(), BUTTON_PRESS() check, and a 200ms failsafe timeout
using GetTickCountDelta() to prevent infinite spins.
This commit is contained in:
xNovyz
2026-03-10 23:06:28 +01:00
parent d27885cf43
commit 57f200d107
1 changed files with 13 additions and 0 deletions
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armsrc/iso14443b.c
+13
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@@ -1379,10 +1379,23 @@ static int Get14443bAnswerFromTag(uint8_t *response, uint16_t max_len, uint32_t
LED_D_ON();
FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_READER | FPGA_HF_READER_SUBCARRIER_848_KHZ | FPGA_HF_READER_MODE_RECEIVE_IQ);
uint32_t wait_start_time = GetTickCount();
for (;;) {
volatile uint16_t behindBy = ((uint16_t *)AT91C_BASE_PDC_SSC->PDC_RPR - upTo) & (DMA_BUFFER_SIZE - 1);
if (behindBy == 0) {
WDT_HIT();
if (BUTTON_PRESS()) {
ret = PM3_EOPABORTED;
break;
}
// Failsafe: if the FPGA SSC clock drops completely, DMA will freeze eternally.
// We use the ARM's main tick counter (1ms) instead of the SSP clock.
if (samples == 0 && GetTickCountDelta(wait_start_time) > 200) {
ret = PM3_ETIMEOUT;
break;
}
continue;
}