From 57f200d1072a84bb5785bbbe95cd0e130045484a Mon Sep 17 00:00:00 2001 From: xNovyz Date: Tue, 10 Mar 2026 23:06:28 +0100 Subject: [PATCH] fix(iso14443b): add WDT_HIT and timeout to DMA receive loop In Get14443bAnswerFromTag(), the behindBy == 0 idle loop (waiting for FPGA DMA samples) had no watchdog kick, no button check, and no timeout. If the FPGA stops providing the SSC clock, this loop spins infinitely until the hardware watchdog triggers a reboot. Add WDT_HIT(), BUTTON_PRESS() check, and a 200ms failsafe timeout using GetTickCountDelta() to prevent infinite spins. --- armsrc/iso14443b.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/armsrc/iso14443b.c b/armsrc/iso14443b.c index 54c455b38..ed726451c 100644 --- a/armsrc/iso14443b.c +++ b/armsrc/iso14443b.c @@ -1379,10 +1379,23 @@ static int Get14443bAnswerFromTag(uint8_t *response, uint16_t max_len, uint32_t LED_D_ON(); FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_READER | FPGA_HF_READER_SUBCARRIER_848_KHZ | FPGA_HF_READER_MODE_RECEIVE_IQ); + uint32_t wait_start_time = GetTickCount(); + for (;;) { volatile uint16_t behindBy = ((uint16_t *)AT91C_BASE_PDC_SSC->PDC_RPR - upTo) & (DMA_BUFFER_SIZE - 1); if (behindBy == 0) { + WDT_HIT(); + if (BUTTON_PRESS()) { + ret = PM3_EOPABORTED; + break; + } + // Failsafe: if the FPGA SSC clock drops completely, DMA will freeze eternally. + // We use the ARM's main tick counter (1ms) instead of the SSP clock. + if (samples == 0 && GetTickCountDelta(wait_start_time) > 200) { + ret = PM3_ETIMEOUT; + break; + } continue; }