Previously, if a pin was configured as ADAPTER_GPIO_INIT_STATE_INPUT and
its drive value was ADAPTER_GPIO_DRIVE_MODE_PUSH_PULL, initialize_gpio
would configure the pin as an output.
The set_gpio_value function is optimized to not set the direction for
pins configured as ADAPTER_GPIO_DRIVE_MODE_PUSH_PULL as it only needs to
be set once. When initialize_gpio performs this setup, it checked only
that the drive value was ADAPTER_GPIO_DRIVE_MODE_PUSH_PULL to set the
output direction but did not exclude input pins which have already had
their direction set.
Now, input pins are ignored when initialize_gpio checks for
ADAPTER_GPIO_DRIVE_MODE_PUSH_PULL to set the mode to output.
Change-Id: I4fc7a8132a6b00c7f213ec9fd05c7bbb37ee5f20
Fixes: 0dd969d83b ("drivers/bcm2835gpio: Migrate to adapter gpio commands")
Signed-off-by: Brandon Pupp <bpupp@xes-inc.com>
[vfazio: update commit message]
Signed-off-by: Vincent Fazio <vfazio@xes-inc.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7862
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
add new i2c bit-banging feature, we can now connect in JTAG with the SoC
target and in i2c with the main board components at the same time.
Change-Id: I8e4516fe1ad5238e0373444f1c3c9bc0814d0f52
Signed-off-by: Ahmed BOUDJELIDA <aboudjelida@nanoxplore.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7796
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
add a line that checks the returned value of set signals function
add two VIDs of other original boards (have onboard angie architecture)
so angie driver can connect to them and change their VID after
renumeration.
Change-Id: Ide4f1f6f38168a410191bf3ff75bcd59dcf7ef50
Signed-off-by: Ahmed BOUDJELIDA <aboudjelida@nanoxplore.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7795
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Introduce the ability to detect CPUs based on CP0 PRId register and
apply cpu specific quirks, which alter the default ejtag behavior.
First of those is EJTAG_QUIRK_PAD_DRET, which makes sure extra NOPs are
placed after the DRET instruction on exit from debug mode. This fixes
resume behavior on Ingenic JZ4780 SoC.
The proper detection of some (currently unsupported) CPUs becomes quite
complicated, so please consult the following Linux kernel code when
adding new CPUs:
* arch/mips/include/asm/cpu.h
* arch/mips/kernel/cpu-probe.c
Change-Id: I0f413d5096cd43ef346b02cea85024985b7face6
Signed-off-by: Artur Rojek <contact@artur-rojek.eu>
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Signed-off-by: Oleksij Rempel <linux@rempel-privat.de>
Reviewed-on: https://review.openocd.org/c/openocd/+/7859
Tested-by: jenkins
stlink v2 on Nucleo-64 board (e.g. NUCLEO-L476RG) has target SWO signal
connected to STM32F103CB'S PA10, which is UART1_RX. UART1 within this
MCU in theory can be configured to 4.5 Mbps baudrate, which means this
is the upper limit supported by HW. As a confirmation BMP (Black Magic
Probe) project also states in documentation that UART1 can be used with
up to 4.5 Mbps baudrate.
Tests have shown that configuring 4.5 Mbps baudrate on stlink v2
available on NUCLEO-L476RG board results in receiving corrupted data.
Using 2.25 Mbps however allows to successfully receive all data from
SWO. This makes sense in terms of STM32F103CB capabilities, since 2.25
Mbps is the next supported baudrate due to division by 2.
Increase supported stlink v2 SWO speed from 2 to 2.25 Mbps.
Tested with NUCLEO-L476RG:
$ stm32l4x.tpiu configure -protocol uart \
-traceclk 80000000 -pin-freq 2250000 \
-output /dev/stdout
$ stm32l4x.tpiu enable
2.25 Mbps speed confirmed with logic analyzer.
Signed-off-by: Marcin Niestroj <m.niestroj@emb.dev>
Change-Id: Icbec04585664aba8b217e8f9a75458e577f7617f
Reviewed-on: https://review.openocd.org/c/openocd/+/7848
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
This emulation mode supports software translation of an AP request
into an address mapped transaction that does not rely on physical AP
hardware. This is necessary in some hardware such as K3 SoCs since the
hardware architecture anticipates a potential race condition between
AP doing direct memory access generating transactions back to system
bus and firewalls that data path out.
This emulation mode allows direct memory driver to emulate CoreSight
Access Port (AP) and reuse the SoC configuration meant for JTAG
debuggers.
Since the address ranges are flat in nature, the requisite memory base
and size will need to be provided a-priori to the driver for mapping.
The other design alternative would be to map requested memory map for
every register operation, but, that would defeat our intent of getting
max debug performance.
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Jason Peck <jpeck@ti.com>
Change-Id: I2d3c5f7833f1973e90b4f6b247827f62fc2905d0
Reviewed-on: https://review.openocd.org/c/openocd/+/7089
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Direct memory driver support for CoreSight Access Port(AP).
Even though we emulate SWD (serial wire debug), we aren't actually
using swd. Instead, we are using a direct memory access to get to the
register set. This is similar in approach to other fast access native
drivers such as am335xgpio drivers.
Example operation on Texas Instrument's AM62x K3 SoC:
+-----------+
| OpenOCD | SoC mem map
| on |--------------+
| Cortex-A53| |
+-----------+ |
|
+-----------+ +-----v-----+
|Cortex-M4F |<───────| |
+-----------+ | |
| DebugSS |
+-----------+ | |
|Cortex-M4F |<───────| |
+-----------+ +-----------+
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Jason Peck <jpeck@ti.com>
Change-Id: I8470cb15348863dd844b2c0e3f63a9063cb032c6
Reviewed-on: https://review.openocd.org/c/openocd/+/7088
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
These cores are advertised as M23 and M33 compatible, but are identified
by the Realtek implementor id. These cores are found on the RTL872xD
family, at least.
Raw CPUIDs:
Real-M200 (KM0): 721cd200
Real-M300 (KM4): 721fd220
Change-Id: I4106ccb7e8c562f98072a71e9e818f57999d664e
Signed-off-by: Karl Palsson <karlp@tweak.au>
Reviewed-on: https://review.openocd.org/c/openocd/+/7846
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Presently, we only look at the Part Number field of the CPUID, and
completely ignore the Implmentor field, simply assuming it to be ARM.
Parts have since been found, with different implementors, that use
overlapping part numbers, causing detection to fail.
Expand the "part number" field to be a full implementor+part number,
excluding the revision/patch fields, to make checking more reliable.
Change-Id: Id81774f829104f57a0c105320d0d2e479fa01522
Signed-off-by: Karl Palsson <karlp@tweak.au>
Reviewed-on: https://review.openocd.org/c/openocd/+/7845
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Use blocks (64 KiB) instead of sectors (4 KiB) when erasing the zd25Q16
SPI flash memory (thanks to Tomas Vanek!)
Change-Id: I969a69ad35f51b84eb3e11b93f0d79db3e98613a
Signed-off-by: Nikolay Dimitrov <nikolay.dimitrov@retrohub.org>
Reviewed-on: https://review.openocd.org/c/openocd/+/7850
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Tested-by: jenkins
Add missing aarch64_poll() calls to ensure the event
TARGET_EVENT_HALTED is called when necessary.
This is needed with the poller update introduced in commit
95603fae18 ("openocd: revert workarounds for 'expr' syntax change")
Signed-off-by: Daniel Goehring <dgoehrin@os.amperecomputing.com>
Change-Id: I6e91f1b6bc1f0d16e6f0eb76fc67d20111e3afd2
Reviewed-on: https://review.openocd.org/c/openocd/+/7737
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
This commit provides startup files for the Synopsys DesignWare ARC
HSDK-4xD board. These have been adapted from the corresponding
snps_hsdk.cfg files, the only functional change being the JTAG IDs for
the new board's CPU cores.
Change-Id: I19a0cd13bc09de90cfe2a7cccf1239e459fd8077
Signed-off-by: Artemiy Volkov <artemiy@synopsys.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7829
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-by: Evgeniy Didin <didin@synopsys.com>
