Squash the history to reduce all the noise when rebasing.
Readme correction
Changes to support QUTS-openOCD
Changes to support QUTS-openOCD
Hexagon debug changes
License headers addition
config file update for lanai
Jimtcl submodule version correction
QUTS install instructions
Eud QPM version update in readme
EUD QPM name correction
Removed QUTS library code for EUD Service
Updated hexagon support
Added EUD submodule
Updated makefiles to compile EUD codebase with openocd
Use --enable-eud with configure command to compile with EUD
Added Qualcomm QCS6490 configuration file
Removed QUTS library code for EUD Service
Updated hexagon support
Added EUD submodule
Updated makefiles to compile EUD codebase with openocd if --enable-eud option is added with configure command
Added Qualcomm QCS6490 configuration file
Changes to read and print EUD Revision information
Signed-off-by: Ashi Gupta <quic_ashig@quicinc.com>
Added EUD Adapter option in qcs6490.cfg and updated license information
Signed-off-by: Ashi Gupta <quic_ashig@quicinc.com>
Updated the EUD submodule link and removed the newline character (\) from the target create command in the qcs6490.cfg configuration file
Signed-off-by: Ashi Gupta <quic_ashig@quicinc.com>
Add SWD multidrop setting.
Fix the name of AP #1 to AUX-AP
Set AUX-AP CSW Prot bit[0] to make RISC-V debug accessible on AUX-AP.
Change-Id: I496e07acfe90dd858e4403176a8330d8c1a0b560
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/8752
Tested-by: jenkins
Reviewed-by: zapb <dev@zapb.de>
AM261[1] is a optimized cutdown of AM263P SoC. The key difference is
the reduced number of R5F cores which is now dropped down to 2, and
the DIE ID is different from AM263p, but all other definitions are
compatible, so reuse the definition.
[1] https://www.ti.com/product/AM2612
Change-Id: Ib6ca0b59d0b8991df6e4ab349d371187438cb393
Signed-off-by: Shivasharan Nagalikar <shivasharan.nagalikar@ti.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8792
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-by: Nishanth Menon <nm@ti.com>
Tested-by: jenkins
AM263P[1] adds additional features to AM263 SoC. [2] provides a
detailed list of differences, however, the key difference from
processor usage perspective is the increased SRAM and Remote L2(RL2)
Cache for improved performance of R5F. To differentiate the DIE ID
is different, however rest of the processor description remain
compatible to AM263, hence reuse the definition.
[1] https://www.ti.com/product/AM263P4
[2] https://www.ti.com/lit/pdf/spradb3
Change-Id: If47935caf1f995d7e606547e0d6545c39544678a
Signed-off-by: Shivasharan Nagalikar <shivasharan.nagalikar@ti.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8770
Reviewed-by: Nishanth Menon <nm@ti.com>
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
TI K3 Debug systems have a Power Access Port (Power-AP) which allows
for functionality such as reset via debugger that using the SPREC
register. SoCs/Boards that do not have support for SRST or TRST can
make use of this to force a system reset via debug access.
Change-Id: Ic5f9cc7f7fba77b353b0c0b42d8afc02502251a0
Signed-off-by: Shivasharan Nagalikar <shivasharan.nagalikar@ti.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8769
Reviewed-by: Nishanth Menon <nm@ti.com>
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
BL602, BL702 and BL702L series of chips are sharing same architecture,
so they all need same software reset mechanism as well.
Only difference (in terms of configuration needed for JTAG) are TAP ID,
workarea address and size. This is addressed by creating bl602_common.cfg
tcl file, which contains all those common stuff between the chips.
The script is prefixed by bl602, as this was
first *publicly* available chip from Bouffalo with this architecture.
This patch also improves reset mechanism. Previous reset mechanism did not
worked properly when slower JTAG adapter was used (it attached too late).
New reset mechanism uses various methods to keep CPU in BootROM, until
the JTAG adapter does not attach again after reset. Additionally,
we trigger SW Reset by directly using DMI commands to write to register
with system bus method, to avoid getting error about unsuccessful write.
The new method works on both FT232H (8MHz JTAG clock) and
unnamed CMSIS-DAP dongle (1.5MHz JTAG clock).
Change-Id: I5be3694927793fd3f64c9ed4ee6ded2db0d25cae
Signed-off-by: Marek Kraus <gamelaster@outlook.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8593
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
To alleviate the need to bitbang SWD, I've written a SWD SPI
implementation. This code is inspired by the work of luppy@appkaki.com
as shown at github.com/lupyuen/openocd-spi but with the desire to be
more generic. This implementation makes use of the more common 4 wire
SPI port using full duplex transfers to be able to capture the SWD ACK
bits when a SWD TX operation is in progress.
TEST:
Connects successfully with the following combinations:
Hosts:
Raspberry Pi 4B
Unnamed Qualcomm SoC with QUPv3 based SPI port
Targets:
Raspberry Pi 2040
Nordic nRF52840
NXP RT500
Change-Id: Ic2f38a1806085d527e6f999a3d15aea6f32d1019
Signed-off-by: Richard Pasek <rpasek@google.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8645
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-by: zapb <dev@zapb.de>
Tested-by: jenkins
Previously, Linux assigned gpiochip numbers sequentially depending on
when the chip driver was probed. As RP1 is on the end of a PCIe link, it
is probed later than the on-board chips (including expanders connected
over SPI/I2C). This meant that RP1's gpiochip assignment was at an
offset that could potentially change.
A downstream kernel patch now assigns fixed offsets for RP1 and the
onboard gpiochips. Query the device tree to get proper GPIO_CHIP index.
Change-Id: I759978d4b3021c815a7d9febb41961cd1d3d185c
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/8650
Reviewed-by: Jonathan Bell <jonathan@raspberrypi.com>
Tested-by: jenkins
The RISC-V coprocessor is currently not supported. It is attached to the
DAP via AP#2 but the AP implementation is unknown.
The nRFL54L series uses resistive RAM (RRAM) as non-volatile memory
which can be programmed directly. Since it does not fit in the current
flash memory infrastructure of OpenOCD there is no NVM support so far.
Change-Id: I9934af4fd3bb8b7272954fc4b17638c7dabbbee0
Signed-off-by: Marc Schink <dev@zapb.de>
Reviewed-on: https://review.openocd.org/c/openocd/+/8609
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
In previous implementation, it was known that it does not perform
full reset, and that some peripherals, such as GLB core,
which handles among other stuff GPIOs, was not reset.
It was presumed, that full reset by software is not possible,
although, by accident, even when comment says that
CTRL_PWRON_RESET is set to 1, it is not
(value written into 0x40000018 supposed to be 0x7, not 0x6).
CTRL_PWRON_RESET indeed triggers full "power-on like" reset,
so this method is implemented in this commit.
There are some workarounds to make reset seamless, without any
error messages, which are described in comments of TCL script.
Only down-side of this reset is, that chip is halted after reset
bit later in BootROM than previous implementation,
but it's still good.
Change-Id: Ife2cdcc6a2d96a2e24039bfec149705baf046318
Signed-off-by: Marek Kraus <gamelaster@outlook.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8529
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Tested-by: jenkins
Provide cable specific configuration files like for the FTDI interface.
Depcrecate the old configuration files but keep them until the next
release for compatibility reasons.
Change-Id: I436bd60779a107120c9e1b1f0b8a69a39a240ad4
Signed-off-by: Marc Schink <dev@zapb.de>
Reviewed-on: https://review.openocd.org/c/openocd/+/8514
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Tested-by: jenkins
The STLink API that supports dap-direct is available from STLink
firmware v2j24, published in early 2015.
We can reasonably expect that any old STLink still in use today
has got at least one firmware update during the last 10 years.
Most of the board files in upstream OpenOCD still use the STLink
in HLA mode. This limits the test coverage of the dap-direct code,
which was introduced in OpenOCD v0.11.0.
- Rename interface/stlink.cfg as interface/stlink-hla.cfg to still
provide support for HLA, adding a deprecated message.
- Rename interface/stlink-dap.cfg as interface/stlink.cfg to make
dap-direct the default trasport.
- Add a redirect file interface/stlink-dap.cfg for users that have
out-of-tree custom board files.
- Update all the board files to the new setup.
- Remove STLink HLA mentions from the documentation, while adding
a reference to interface/stlink-hla.cfg
Checkpatch-ignore: LONG_LINE
Change-Id: I99366bb03cd3b83f8f408514e657f30e59813063
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8523
Tested-by: jenkins
Reviewed-by: Andrzej Sierżęga <asier70@gmail.com>
