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Linus Torvalds 4ee64205ff Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux 
Pull clk updates from Stephen Boyd:
 "We've finally gotten rid of the struct clk_ops::round_rate() code
  after months of effort from Brian Masney. Now the only option is to
  use determine_rate(), which is good because that takes a struct
  argument instead of just a couple unsigned longs, allowing us to
  easily modify the way we determine and set rates in the clk tree.

  Beyond that core framework change we've got the typical pile of new
  SoC clk driver additions, fixes for clk data and/or adding missing
  clks because the consumer driver using those clks wasn't ready, etc.
  The usual suspects are all here: Qualcomm, Samsung, Mediatek, and
  Rockchip along with some newcomers making RISC-V SoCs like ESWIN's
  eic700 and Tenstorrent's Atlantis. The clk driver side of this looks
  pretty normal.

  Core:
   - Remove the round_rate() clk op (yay!)

  New Drivers:
   - ESWIN eic700 SoC clk support
   - Econet EN751221 SoC clock/reset support
   - Global TCSR, RPMh, and display clock controller support for the
     Qualcomm Eliza platform
   - TCSR, the multiple global, and the RPMh clock controller support
     for the Qualcomm Nord platform
   - GPU clock controller support for Qualcomm SM8750
   - Video and GPU clock controller support for Qualcomm Glymur
   - Global clock controller support for Qualcomm IPQ5210
   - Axis ARTPEC-9: Add new PLL clocks and new drivers for eight clock
     controllers on the SoC
   - ExynosAutov920: Add G3D (GPU) clock controller
   - Clock driver for the Rockchip RV1103B SoC
   - Initial support for the Renesas RZ/G3L (R9A08G046) SoC
   - Clock and reset controllers (e.g. PRCM) in the Tenstorrent Atlantis SoC"

* tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (132 commits)
  clk: visconti: pll: initialize clk_init_data to zero
  clk: fsl-sai: Add MCLK generation support
  clk: fsl-sai: Extract clock setup into fsl_sai_clk_register()
  dt-bindings: clock: fsl-sai: Document clock-cells = <1> support
  clk: fsl-sai: Add i.MX8M support with 8 byte register offset
  clk: fsl-sai: Sort the headers
  dt-bindings: clock: fsl-sai: Document i.MX8M support
  clk: qcom: gcc: Add multiple global clock controller driver for Nord SoC
  clk: qcom: rpmh: Add support for Nord rpmh clocks
  clk: qcom: Add TCSR clock driver for Nord SoC
  dt-bindings: clock: qcom: Add Nord Global Clock Controller
  dt-bindings: clock: qcom-rpmhcc: Add support for Nord SoCs
  dt-bindings: clock: qcom: Document the Nord SoC TCSR Clock Controller
  clk: qcom: gcc-x1e80100: Keep GCC USB QTB clock always ON
  clk: qcom: Constify list of critical CBCR registers
  clk: qcom: Constify qcom_cc_driver_data
  clk: qcom: videocc-glymur: Constify qcom_cc_desc
  clk: qcom: Add a driver for SM8750 GPU clocks
  dt-bindings: clock: qcom: Add SM8750 GPU clocks
  clk: qcom: ipq-cmn-pll: Add IPQ8074 SoC support
  ...
 2026-04-21 08:33:26 -07:00
Linus Torvalds 31b43c079f Merge tag 'soc-drivers-7.1' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc 
Pull SoC driver updates from Arnd Bergmann:
 "The driver updates again are all over the place with many minor fixes
  going into platform specific code. The most notable changes are:

   - Support for Microchip pic64gx system controllers
   - Work on cleaning up devicetree bindings for SoC drivers, and
     converting them into the new format
   - Lots of smaller changes for Qualcomm SoC drivers, including support
     for a number of newly supported chips
   - reset controller API cleanups and a new driver for Cix Sky1
   - Reworks of the Tegra PMC and CBB drivers, along with a change to
     how individual Tegra SoCs get selected in Kconfig and BPMP firmware
     driver updates including a refresh of the ABI header to match the
     version used by firmware
   - STM32 updates to the firewall bus driver and support for the debug
     bus through OP-TEE
   - SCMI firmware driver improvements for reliability, in particular
     for dealing with broken firmware interrupts
   - Memory driver updates for Tegra, and a patch to remove the unused
     Baikal T1 driver"

* tag 'soc-drivers-7.1' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (193 commits)
  firmware: arm_ffa: Use the correct buffer size during RXTX_MAP
  firmware: qcom: scm: Allow QSEECOM on Lenovo IdeaCentre Mini X
  clk: spear: fix resource leak in clk_register_vco_pll()
  reset: rzv2h-usb2phy: Add support for VBUS mux controller registration
  reset: rzv2h-usb2phy: Convert to regmap API
  dt-bindings: reset: renesas,rzv2h-usb2phy: Document RZ/G3E USB2PHY reset
  dt-bindings: reset: renesas,rzv2h-usb2phy: Add '#mux-state-cells' property
  soc: microchip: add mpfs gpio interrupt mux driver
  dt-bindings: soc: microchip: document PolarFire SoC's gpio interrupt mux
  gpio: mpfs: Add interrupt support
  soc: qcom: ubwc: add helpers to get programmable values
  soc: qcom: ubwc: add helper to get min_acc length
  firmware: qcom: scm: Register gunyah watchdog device
  soc: qcom: socinfo: Add SoC ID for SA8650P
  dt-bindings: arm: qcom,ids: Add SoC ID for SA8650P
  firmware: qcom: scm: Allow QSEECOM on Mahua CRD
  soc: qcom: wcnss: simplify allocation of req
  soc: qcom: pd-mapper: Add support for Eliza
  soc: qcom: aoss: compare against normalized cooling state
  soc: qcom: llcc: fix v1 SB syndrome register offset
  ...
 2026-04-16 20:34:34 -07:00
Stephen Boyd 6b701fde9b Merge branches 'clk-samsung', 'clk-qcom', 'clk-round', 'clk-sai' and 'clk-cleanup' into clk-next 
* clk-samsung:
  clk: samsung: exynos850: Add APM-to-AP mailbox clock
  dt-bindings: clock: exynos850: Add APM_AP MAILBOX clock
  clk: samsung: Use %pe format to simplify
  clk: samsung: pll: Fix possible truncation in a9fraco recalc rate
  clk: samsung: exynosautov920: add block G3D clock support
  dt-bindings: clock: exynosautov920: add G3D clock definitions
  clk: samsung: gs101: harmonise symbol names (clock arrays)
  clk: samsung: artpec-9: Add initial clock support for ARTPEC-9 SoC
  clk: samsung: Add clock PLL support for ARTPEC-9 SoC
  dt-bindings: clock: Add ARTPEC-9 clock controller

* clk-qcom: (67 commits)
  clk: qcom: gcc: Add multiple global clock controller driver for Nord SoC
  clk: qcom: rpmh: Add support for Nord rpmh clocks
  clk: qcom: Add TCSR clock driver for Nord SoC
  dt-bindings: clock: qcom: Add Nord Global Clock Controller
  dt-bindings: clock: qcom-rpmhcc: Add support for Nord SoCs
  dt-bindings: clock: qcom: Document the Nord SoC TCSR Clock Controller
  clk: qcom: gcc-x1e80100: Keep GCC USB QTB clock always ON
  clk: qcom: Constify list of critical CBCR registers
  clk: qcom: Constify qcom_cc_driver_data
  clk: qcom: videocc-glymur: Constify qcom_cc_desc
  clk: qcom: Add a driver for SM8750 GPU clocks
  dt-bindings: clock: qcom: Add SM8750 GPU clocks
  clk: qcom: ipq-cmn-pll: Add IPQ8074 SoC support
  dt-bindings: clock: qcom: Add CMN PLL support for IPQ8074
  clk: qcom: ipq-cmn-pll: Add IPQ6018 SoC support
  dt-bindings: clock: qcom: Add CMN PLL support for IPQ6018
  clk: qcom: gdsc: Fix error path on registration of multiple pm subdomains
  dt-bindings: clock: qcom: Add missing power-domains property
  clk: qcom: gcc-eliza: Enable FORCE_MEM_CORE_ON for UFS AXI PHY clock
  clk: qcom: dispcc-sc7180: Add missing MDSS resets
  ...

* clk-round:
  clk: divider: remove divider_round_rate() and divider_round_rate_parent()
  clk: divider: remove divider_ro_round_rate_parent()
  clk: remove round_rate() clk ops
  clk: composite: convert from round_rate() to determine_rate()
  clk: test: remove references to clk_ops.round_rate

* clk-sai:
  clk: fsl-sai: Add MCLK generation support
  clk: fsl-sai: Extract clock setup into fsl_sai_clk_register()
  dt-bindings: clock: fsl-sai: Document clock-cells = <1> support
  clk: fsl-sai: Add i.MX8M support with 8 byte register offset
  clk: fsl-sai: Sort the headers
  dt-bindings: clock: fsl-sai: Document i.MX8M support

* clk-cleanup:
  clk: visconti: pll: initialize clk_init_data to zero
  clk: xgene: Fix mapping leak in xgene_pllclk_init()
  clk: Simplify clk_is_match()
  clk: baikal-t1: Remove not-going-to-be-supported code for Baikal SoC
  clk: mvebu: armada-37xx-periph: fix __iomem casts in structure init
  clk: qoriq: avoid format string warning
 2026-04-16 10:12:43 -07:00
Stephen Boyd 522a83abc3 Merge branches 'clk-tenstorrent', 'clk-rockchip', 'clk-imx' and 'clk-allwinner' into clk-next 
* clk-tenstorrent:
  clk: tenstorrent: Add Atlantis clock controller driver
  reset: tenstorrent: Add reset controller for Atlantis
  dt-bindings: clk: tenstorrent: Add tenstorrent,atlantis-prcm-rcpu

* clk-rockchip:
  clk: rockchip: rk3568: Add PCIe pipe clock gates
  clk: rockchip: Add clock controller for the RV1103B
  dt-bindings: clock: rockchip: Add RV1103B CRU support

* clk-imx:
  clk: imx8mq: Correct the CSI PHY sels
  clk: vf610: Add support for the Ethernet switch clocks
  dt-bindings: clock: vf610: Add definitions for MTIP L2 switch
  dt-bindings: clock: vf610: Drop VF610_CLK_END define
  clk: vf610: Move VF610_CLK_END define to clk-vf610 driver
  clk: imx: imx8-acm: fix flags for acm clocks
  clk: imx: imx6q: Fix device node reference leak in of_assigned_ldb_sels()
  clk: imx: imx6q: Fix device node reference leak in pll6_bypassed()
  clk: imx: fracn-gppll: Add 477.4MHz support
  clk: imx: fracn-gppll: Add 333.333333 MHz support
  clk: imx: pll14xx: Use unsigned format specifier
  dt-bindings: clock: imx6q[ul]-clock: add optional clock enet[1]_ref_pad

* clk-allwinner:
  clk: sunxi-ng: sun55i-a523-r: Add missing r-spi module clock
 2026-04-16 10:12:33 -07:00
Stephen Boyd 699646e684 Merge branches 'clk-fixes', 'clk-renesas', 'clk-rpi', 'clk-eswin' and 'clk-mediatek' into clk-next 
- ESWIN eic700 SoC clk support
 - Econet EN751221 SoC clock/reset support

* clk-fixes:
  clk: spacemit: ccu_mix: fix inverted condition in ccu_mix_trigger_fc()
  clk: microchip: mpfs-ccc: fix out of bounds access during output registration
  clk: qcom: dispcc-sm8450: use RCG2 ops for DPTX1 AUX clock source

* clk-renesas:
  clk: renesas: Add support for RZ/G3L SoC
  dt-bindings: clock: renesas,rzg2l-cpg: Document RZ/G3L SoC
  clk: renesas: rzg2l: Re-enable critical module clocks during resume
  clk: renesas: rzg2l: Add rzg2l_mod_clock_init_mstop_helper()
  clk: renesas: rzg2l: Add helper for mod clock enable/disable
  clk: renesas: r9a0{7g04[34],8g045}: Add critical reset entries
  clk: renesas: rzg2l: Add support for critical resets
  clk: renesas: r9a09g056: Remove entries for WDT{0,2,3}
  clk: renesas: r9a06g032: Enable watchdog reset sources
  clk: renesas: cpg-mssr: Use struct_size() helper
  clk: renesas: r9a09g047: Add PCIe clocks and reset
  clk: renesas: r9a09g057: Add PCIe clocks and reset
  clk: renesas: r9a09g056: Add PCIe clocks and reset
  clk: renesas: r9a09g047: Add entries for the RSPIs
  clk: renesas: r9a09g056: Add clock and reset entries for RTC
  clk: renesas: r9a09g057: Remove entries for WDT{0,2,3}
  clk: renesas: r9a09g056: Fix ordering of module clocks array
  clk: renesas: r9a09g057: Fix ordering of module clocks array

* clk-rpi:
  clk: bcm: rpi: Manage clock rate in prepare/unprepare callbacks

* clk-eswin:
  MAINTAINERS: Add entry for ESWIN EIC7700 clock driver
  clk: eswin: Add eic7700 clock driver
  clk: divider: Add devm_clk_hw_register_divider_parent_data
  dt-bindings: clock: eswin: Documentation for eic7700 SoC

* clk-mediatek:
  clk: airoha: Add econet EN751221 clock/reset support to en7523-scu
  dt-bindings: clock, reset: Add econet EN751221
 2026-04-16 10:07:47 -07:00
Marek VasutandStephen Boyd f293f885c4 dt-bindings: clock: fsl-sai: Document clock-cells = <1> support 
The driver now supports generation of both BCLK and MCLK, document
support for #clock-cells = <0> for legacy case and #clock-cells = <1>
for the new case which can differentiate between BCLK and MCLK.

Acked-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Marek Vasut <marex@nabladev.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 2026-04-11 17:32:38 -07:00
Marek VasutandStephen Boyd 29e64a3708 dt-bindings: clock: fsl-sai: Document i.MX8M support 
The i.MX8M/Mini/Nano/Plus variant of the SAI IP has control registers
shifted by +8 bytes and requires additional bus clock. Document support
for the i.MX8M variant of the IP with this register shift and additional
clock. Update the description slightly.

Acked-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Marek Vasut <marex@nabladev.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 2026-04-11 17:32:23 -07:00
Krzysztof Kozlowski 4177ec9d58 Merge tag 'v7.1-rockchip-dts32-2' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into soc/dt 
Support for the RV1103B SoC and the Onion Omega4 board using it.
While the RV1103B only got a B-extension to its name, the SoC internals
were reworked heavily. So likely it's mainly pin compatible to the
non-B variant.

The dt-binding for the RV1103B clock driver is shared with the clock-
driver branch going into the clock-tree.

* tag 'v7.1-rockchip-dts32-2' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
  ARM: dts: rockchip: Add Onion Omega4 Evaluation Board
  dt-bindings: arm: rockchip: Add Omega4 Evaluation board
  ARM: dts: rockchip: Add support for RV1103B
  dt-bindings: soc: rockchip: grf: Add RV1103B compatibles
  dt-bindings: clock: rockchip: Add RV1103B CRU support

Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
 2026-04-11 10:09:33 +02:00
Taniya DasandBjorn Andersson 06498d59bb dt-bindings: clock: qcom: Add Nord Global Clock Controller 
Add device tree bindings for the global clock controller on Qualcomm
Nord platform. The global clock controller on Nord SoC is divided into
multiple clock controllers (GCC,SE_GCC,NE_GCC and NW_GCC). Add each of
the bindings to define the clock controllers.

Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com>
Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260403-nord-clks-v1-3-018af14979fd@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2026-04-08 20:57:01 -05:00
Taniya DasandBjorn Andersson 8a10804724 dt-bindings: clock: qcom-rpmhcc: Add support for Nord SoCs 
Add bindings and update documentation compatible for RPMh clock
controller on Nord SoC.

Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com>
Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260403-nord-clks-v1-2-018af14979fd@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2026-04-08 20:57:01 -05:00
Taniya DasandBjorn Andersson 31fcf6995e dt-bindings: clock: qcom: Document the Nord SoC TCSR Clock Controller 
The Nord SoC TCSR block provides CLKREF clocks for DP, PCIe, UFS, SGMII
and USB.

Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com>
[Shawn: Use compatible qcom,nord-tcsrcc rather than qcom,nord-tcsr]
Signed-off-by: Shawn Guo <shengchao.guo@oss.qualcomm.com>
Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260403-nord-clks-v1-1-018af14979fd@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2026-04-08 20:57:01 -05:00
Arnd Bergmann 8366b60cbe Merge tag 'qcom-arm64-for-7.1' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into soc/dt 
Qualcomm Arm64 DeviceTree updates for v7.1

Introduce the Eliza, Glymur, Mahua, and IPQ5210 Qualcomm SoCs.

Introduce the Redmi 4A, Redmi Go, Arduino Monza (VENTUNO Q), Redmi Note
8T, Purwa EVK, ECS Liva QCS710, additional variants of the DB820c,
Ayaneo Pocket S2, Thundercomm AI Mini PC G1, Samsung Galaxy Core Prime
LTE Verizon Wireless, Wiko Pulp 4G, the Purwa-variant of ASUS Vivobook
S15, the Eliza MTP, and the Glymur and Mahua CRDs.

Introduce UFS support and flatten the DWC3 node on Hamoa. Enable UFS,
SDC, DisplayPort audio playback, and an EL2 overlay for the Hamoa IoT
EVK. Enable DisplayPort audio on the Hamoa CRD and add HDMI support on
the ASUS Zenbook A14. Reduce the duplication of thermal sensors across
Purwa and Hamoa.

Add the QPIC SPI NAND controller on IPQ5332 and IPQ9574. Describe and
enable the eMMC controller on IPQ9574.

Add display, audio/compute remoteprocs, QUP devices, thermal sensors,
display, and CoreSight on the Kaanapali platform. Enable audio, compute
display, PMIC, Bluetooth, and WiFi on the MTP. Describe PMIC, audio and
compute remoteprocs on QRD.

Add role-switching support for the tertiary USB controller on Lemans.
Enable the tertiary USB controller and the GPIO expander on the Lemans
EVK, and add an overlay for the IFP Mezzanine.

Add UFS, camera control interface, audio GPR, and FastRPC support on
Milos. Enable UFS, camera EEPROMs, and hall effect sensor on the
Fairphone FP6.

Add camera control interface and fix a variety of things on the Monaco
platform, add missing FastRPC compute banks. Add eMMC support, describe
the DisplayPort bridge and GPIO expander on the Monaco EVK. Add overlay
for EVK camera and the IFP mezzanine.

Add touchscreen to the Xiaomi Redmi 4A, 5A, and Go, and fix the board-id
on the 4A.

Add the ambient light and proximity sensor on the Asus ZenFone 2
Laser/Selfie.

On Kodiak-based boards, enable the ethernet and USB Type-A ports on the
Rb3Gen2, correct the LT9611 routing on the RubikPi3, add Bluetooth on
the IDP, and add front camera support on the Fairphone FP5.
Introduce an overlay for the Rb3Gen2 Industrial Mezzanine.

Describe DSI on the Monaco SoC and enable Bluetooth, WiFi and DSI/DP
bridge on the Ride board.

Describe the WiFi/BT combo chip properly on the QRB2210 RB1 and QRB4210.
The describe the DSI/DP bringde on the Arduino UnoQ.

01022af2d2 arm64: dts: qcom: sc7280-chrome-common: disable Venus

Introduce DSI display support on SC8280XP.

Add LLCC on SDM670 and another SPI controller on SDM630.

Properly describe the WiFi/BT chip on a variety of SDM845-based
devices. Introduce the "alert slider" on the OnePlus 6 and OnePlus 6T
devices.

Introduce the PRNG, describe the debug UART, and add the MDSS core reset
on SM6125. Enable the debug UART and fix various issues on the Xiaomi
Redmi Note 8. Describe the touchscreen on the Xiaomi Mi A3.

Properly describe the WiFi/BT combo chip in SM8150 HDK.

Improve the EAS properties on SM8550, in addition to various other
fixes. Introduce a new overlay for the HDK display card.

Introduce various smaller fixes across SM8450 and SM8650.

Add display support on SM8750 and enable DSI and DisplayPort on the MTP.
Also add tsens and thermal-zones.

Add ETR devices, flatten the USB controller node, and mark USB
controllers as wakeup-capable devices, on Talos.

Properly describe the IPA IMEM slice on a variety of platforms.

Drop redundant non-controllable regulator definitions from a variety of
boards.

Drop redundant VSYNC pin state definition from various platforms.

* tag 'qcom-arm64-for-7.1' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux: (254 commits)
  arm64: dts: qcom: sm8250: Add missing CPU7 3.09GHz OPP
  arm64: dts: qcom: sm8550-hdk: add support for the Display Card overlay
  arm64: dts: qcom: msm8916-samsung-coreprimeltevzw: add device tree
  dt-bindings: qcom: Document samsung,coreprimeltevzw
  arm64: dts: qcom: msm8916-samsung-fortuna: Move SM5504 from rossa and refactor MUIC
  arm64: dts: qcom: sdm670: add llcc
  arm64: dts: qcom: qcm6490-fairphone-fp5: Add front camera support
  arm64: dts: qcom: qcm6490-fairphone-fp5: Sort pinctrl nodes by pins
  arm64: dts: qcom: milos-fairphone-fp6: Add camera EEPROMs on CCI busses
  arm64: dts: qcom: milos: Add CCI busses
  arm64: dts: qcom: purwa-iot-evk: Enable UFS
  arm64: dts: qcom: eliza: Add thermal sensors
  arm64: dts: qcom: sc8280xp: Add dsi nodes on SC8280XP
  arm64: dts: qcom: sdm845-oneplus: Describe Wi-Fi/BT properly
  arm64: dts: qcom: sdm845-google: Describe Wi-Fi/BT properly
  arm64: dts: qcom: drop redundant zap-shader memory-region
  arm64: dts: qcom: fix remaining gpu_zap_shader labels
  arm64: dts: qcom: msm8996: fix indentation in sdhc2 node
  arm64: dts: qcom: monaco-evk: enable UART6 for robot expansion board
  arm64: dts: qcom: lemans-evk: enable UART0 for robot expansion board
  ...

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
 2026-04-03 00:08:34 +02:00
Arnd Bergmann cce3c4db86 Merge tag 'renesas-dts-for-v7.1-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into soc/dt 
Renesas DTS updates for v7.1 (take two)

  - Add DT overlay support for the MayQueen PixPaper display on the
    Yuridenki-Shokai Kakip board,
  - Add Ethernet PHY interrupt support for the RZ/T2H and RZ/N2H EVK
    boards,
  - Add SPI and PCIe support for the RZ/G3E SoC and the RZ/G3E SMARC EVK
    board,
  - Add DT overlay support for the WaveShare 13.3" 1920x1080 DSI
    Capacitive Touch Display and the Olimex MIPI-HDMI adapter on the
    Retronix Sparrow Hawk board,
  - Drop several superfluous C22 Ethernet PHY compatible strings,
  - Remove WDT nodes meant for other CPU cores on the RZ/V2N SoC,
  - Remove unavailable LVDS panel support for the Beacon ReneSoM base
    board,
  - Add initial support for the RZ/G3L (R9A08G046) SoC, and the RZ/G3L
    SMARC SoM and EVK boards,
  - Add Versa3 clock generator support for the RZ/V2H EVK development
    board,
  - Miscellaneous fixes and improvements.

* tag 'renesas-dts-for-v7.1-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel: (29 commits)
  ARM: dts: renesas: Drop KSZ8041 PHY C22 compatible strings
  ARM: dts: renesas: rza2mevb: Drop RTL8201F PHY C22 compatible string
  ARM: dts: renesas: r8a7742-iwg21d-q7-dbcm-ca: Drop KSZ8081 PHY C22 compatible string
  arm64: dts: renesas: Add initial device tree for RZ/G3L SMARC EVK board
  arm64: dts: renesas: renesas-smarc2: Move usb3 nodes to board DTS
  arm64: dts: renesas: Add initial support for RZ/G3L SMARC SoM
  arm64: dts: renesas: Add initial DTSI for RZ/G3L SoC
  arm64: dts: renesas: r9a09g057h44-rzv2h-evk: Add versa3 clock generator node
  dt-bindings: clock: renesas,rzg2l-cpg: Document RZ/G3L SoC
  arm64: dts: renesas: beacon-renesom: Remove LVDS Panel
  ARM: dts: r9a06g032: Add #address-cells to the GIC node
  arm64: dts: renesas: r9a09g056: Remove wdt{0,2,3} nodes
  arm64: dts: renesas: sparrow-hawk: Add overlay for Olimex MIPI-HDMI adapter
  arm64: dts: renesas: r9a09g047e57-smarc: Enable PCIe
  arm64: dts: renesas: r9a09g047e57-smarc-som: Add PCIe reference clock
  arm64: dts: renesas: r9a09g047: Add PCIe node
  arm64: dts: renesas: Fix KSZ9131 PHY bogus txdv-skew-psec properties
  arm64: dts: renesas: Drop KSZ9131 PHY C22 compatible strings
  arm64: dts: renesas: Drop RTL8211F PHY C22 compatible strings
  arm64: dts: renesas: Drop RTL8211E PHY C22 compatible strings
  ...

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
 2026-04-01 19:20:18 +02:00
Konrad DybcioandBjorn Andersson 4aeadf8a18 dt-bindings: clock: qcom: Add SM8750 GPU clocks 
The SM8750 features a "traditional" GPU_CC block, much of which is
controlled through the GMU microcontroller. GPU_CC block requires the MX
and CX rail control and thus add the corresponding power-domains and
require-opps. Additionally, there's an separate GX_CC block, where
the GX GDSC is moved.

Update the bindings to accommodate for SM8750 SoC.

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260305-gpucc_sm8750_v2-v5-1-78292b40b053@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2026-03-30 09:08:53 -05:00
John CrispinandBjorn Andersson 7156c65030 dt-bindings: clock: qcom: Add CMN PLL support for IPQ8074 
The CMN PLL block in the IPQ8074 SoC takes 48 MHz as the reference
input clock. Its output clocks are the bias_pll_cc_clk (300 MHz) and
bias_pll_nss_noc_clk (416.5 MHz) clocks used by the networking
subsystem.

Add the related compatible for IPQ8074 to the ipq9574-cmn-pll
generic schema.

Signed-off-by: John Crispin <john@phrozen.org>
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260311183942.10134-4-ansuelsmth@gmail.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2026-03-30 09:02:12 -05:00
John CrispinandBjorn Andersson a57666004f dt-bindings: clock: qcom: Add CMN PLL support for IPQ6018 
The CMN PLL block in the IPQ6018 SoC takes 48 MHz as the reference
input clock. Its output clocks are the bias_pll_cc_clk (300 MHz) and
bias_pll_nss_noc_clk (416.5 MHz) clocks used by the networking
subsystem.

Add the related compatible for IPQ6018 to the ipq9574-cmn-pll
generic schema.

Signed-off-by: John Crispin <john@phrozen.org>
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260311183942.10134-2-ansuelsmth@gmail.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2026-03-30 09:02:11 -05:00
Abel VesaandBjorn Andersson c412c6b13e dt-bindings: clock: qcom: Add missing power-domains property 
In order for the GCC votes on the GDSCs it provides to be propagated
to CX, CX needs to be declared as power domain of the GCC.

Document the missing power-domains property to that purpose.

Fixes: 95ba6820a6 ("dt-bindings: clock: qcom: document the Milos Global Clock Controller")
Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260327-dt-fix-milos-eliza-gcc-power-domains-v1-1-f14a22c73fe9@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2026-03-30 08:27:32 -05:00
Thierry Reding 6413bfc1f6 dt-bindings: clock: tegra124-dfll: Convert to json-schema 
Convert the Tegra124 (and later) DFLL bindings from the free-form text
format to json-schema.

Co-developed-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
 2026-03-27 16:25:44 +01:00
Biju DasandGeert Uytterhoeven b822fb8250 dt-bindings: clock: renesas,rzg2l-cpg: Document RZ/G3L SoC 
Document the device tree bindings for the Renesas RZ/G3L SoC Clock Pulse
Generator (CPG). RZ/G3L CPG is similar to RZ/G2L CPG but has 5 clocks
compared to 1 clock on other SoCs.

Also define RZ/G3L (R9A08G046) Clock Pulse Generator Core Clocks, as
listed in section 4.4.4.1 ("Block Diagram of the Clock System"), module
clock outputs, as listed in section 4.4.2 ("Clock List r1.00") and add
Reset definitions referring to registers CPG_RST_* in Section 4.4.3
("Register") of the RZ/G3L Hardware User's Manual (Rev.1.00 Oct, 2025).

Acked-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://patch.msgid.link/20260324114329.268249-2-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2026-03-26 19:44:48 +01:00
Bjorn Andersson 4d059454d3 Merge branch '20260318-ipq5210_boot_to_shell-v2-1-a87e27c37070@oss.qualcomm.com' into HEAD 
Merge the IPQ5210 global clock controller DeviceTree binding, in order
to gain access to the constants.
 2026-03-26 09:40:57 -05:00
Caleb James DeLisleandStephen Boyd 35af99f748 dt-bindings: clock, reset: Add econet EN751221 
Add clock and reset bindings for EN751221 as well as a "chip-scu" which is
an additional regmap that is used by the clock driver as well as others.
This split of the SCU across two register areas is the same as the Airoha
AN758x family.

Signed-off-by: Caleb James DeLisle <cjd@cjdns.fr>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 2026-03-24 21:55:41 -07:00
Xuyang DongandStephen Boyd 1fb8313260 dt-bindings: clock: eswin: Documentation for eic7700 SoC 
Add device tree binding documentation for the ESWIN eic7700
clock controller module.

Signed-off-by: Yifeng Huang <huangyifeng@eswincomputing.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Acked-by: Troy Mitchell <troy.mitchell@linux.dev>
Tested-by: Marcel Ziswiler <marcel@ziswiler.com> # ebc77
Signed-off-by: Xuyang Dong <dongxuyang@eswincomputing.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 2026-03-24 19:11:25 -07:00
Andy ShevchenkoandStephen Boyd 5d6c477687 clk: baikal-t1: Remove not-going-to-be-supported code for Baikal SoC 
As noticed in the discussion [1] the Baikal SoC and platforms
are not going to be finalized, hence remove stale code.

Reviewed-by: Brian Masney <bmasney@redhat.com>
Link: https://lore.kernel.org/lkml/22b92ddf-6321-41b5-8073-f9c7064d3432@infradead.org/ [1]
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Rob Herring (Arm) <robh@kernel.org>
Reviewed-by: Randy Dunlap <rdunlap@infradead.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 2026-03-23 17:17:59 -07:00
Bjorn Andersson 7f9ccf3b99 Merge branch '20260319-clk-qcom-dispcc-eliza-v3-1-d1f2b19a6e6b@oss.qualcomm.com' into clk-for-7.1 
Merge the Eliza display clock controller binding through a topic branch,
to allow the constants to be shared with the DeviceTree branch.
 2026-03-23 11:29:06 -05:00
Krzysztof KozlowskiandBjorn Andersson a4f78912ae dt-bindings: clock: qcom,eliza-dispcc: Add Eliza SoC display CC 
Add bindings for Qualcomm Eliza SoC display clock controller (dispcc),
which is very similar to one in SM8750, except new HDMI-related clocks
and additional clock input from HDMI PHY PLL.

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260319-clk-qcom-dispcc-eliza-v3-1-d1f2b19a6e6b@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2026-03-23 11:28:52 -05:00