mirror of
https://github.com/linux-msm/laptops-kernel.git
synced 2026-08-13 14:19:53 -07:00
Merge tag 'soc-drivers-7.1' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
Pull SoC driver updates from Arnd Bergmann:
"The driver updates again are all over the place with many minor fixes
going into platform specific code. The most notable changes are:
- Support for Microchip pic64gx system controllers
- Work on cleaning up devicetree bindings for SoC drivers, and
converting them into the new format
- Lots of smaller changes for Qualcomm SoC drivers, including support
for a number of newly supported chips
- reset controller API cleanups and a new driver for Cix Sky1
- Reworks of the Tegra PMC and CBB drivers, along with a change to
how individual Tegra SoCs get selected in Kconfig and BPMP firmware
driver updates including a refresh of the ABI header to match the
version used by firmware
- STM32 updates to the firewall bus driver and support for the debug
bus through OP-TEE
- SCMI firmware driver improvements for reliability, in particular
for dealing with broken firmware interrupts
- Memory driver updates for Tegra, and a patch to remove the unused
Baikal T1 driver"
* tag 'soc-drivers-7.1' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (193 commits)
firmware: arm_ffa: Use the correct buffer size during RXTX_MAP
firmware: qcom: scm: Allow QSEECOM on Lenovo IdeaCentre Mini X
clk: spear: fix resource leak in clk_register_vco_pll()
reset: rzv2h-usb2phy: Add support for VBUS mux controller registration
reset: rzv2h-usb2phy: Convert to regmap API
dt-bindings: reset: renesas,rzv2h-usb2phy: Document RZ/G3E USB2PHY reset
dt-bindings: reset: renesas,rzv2h-usb2phy: Add '#mux-state-cells' property
soc: microchip: add mpfs gpio interrupt mux driver
dt-bindings: soc: microchip: document PolarFire SoC's gpio interrupt mux
gpio: mpfs: Add interrupt support
soc: qcom: ubwc: add helpers to get programmable values
soc: qcom: ubwc: add helper to get min_acc length
firmware: qcom: scm: Register gunyah watchdog device
soc: qcom: socinfo: Add SoC ID for SA8650P
dt-bindings: arm: qcom,ids: Add SoC ID for SA8650P
firmware: qcom: scm: Allow QSEECOM on Mahua CRD
soc: qcom: wcnss: simplify allocation of req
soc: qcom: pd-mapper: Add support for Eliza
soc: qcom: aoss: compare against normalized cooling state
soc: qcom: llcc: fix v1 SB syndrome register offset
...
This commit is contained in:
Linus Torvalds
@@ -128,6 +128,9 @@ properties:
|
||||
"#address-cells":
|
||||
const: 1
|
||||
|
||||
access-controllers:
|
||||
maxItems: 1
|
||||
|
||||
patternProperties:
|
||||
'^trig-conns@([0-9]+)$':
|
||||
type: object
|
||||
|
||||
@@ -78,6 +78,9 @@ properties:
|
||||
description: Output connection to CoreSight Trace bus
|
||||
$ref: /schemas/graph.yaml#/properties/port
|
||||
|
||||
access-controllers:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
|
||||
@@ -118,6 +118,9 @@ properties:
|
||||
description: Output connection from the ETM to CoreSight Trace bus.
|
||||
$ref: /schemas/graph.yaml#/properties/port
|
||||
|
||||
access-controllers:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- clocks
|
||||
|
||||
@@ -73,6 +73,9 @@ properties:
|
||||
description: Output connection to the CoreSight Trace bus.
|
||||
$ref: /schemas/graph.yaml#/properties/port
|
||||
|
||||
access-controllers:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
|
||||
@@ -128,6 +128,9 @@ properties:
|
||||
- const: tracedata
|
||||
- const: metadata
|
||||
|
||||
access-controllers:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
|
||||
@@ -70,6 +70,9 @@ properties:
|
||||
description: Input connection from the CoreSight Trace bus.
|
||||
$ref: /schemas/graph.yaml#/properties/port
|
||||
|
||||
access-controllers:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
|
||||
@@ -0,0 +1,66 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/arm/atmel,at91rm9200-sdramc.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Microchip (Atmel) SDRAM / DDR Controller (RAMC / DDRAMC / UDDRC)
|
||||
|
||||
maintainers:
|
||||
- Nicolas Ferre <nicolas.ferre@microchip.com>
|
||||
- Claudiu Beznea <claudiu.beznea@tuxon.dev>
|
||||
|
||||
description:
|
||||
The SDRAM/DDR Controller (often called RAMC or DDRAMC) in various
|
||||
Atmel/Microchip ARM9 and Cortex-A5/A7 SoCs manages external
|
||||
SDRAM / DDR memory. It is typically exposed as a syscon node for
|
||||
register access from other drivers (e.g. for initialization or mode
|
||||
configuration). No interrupts or clocks are usually required in the
|
||||
binding.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
oneOf:
|
||||
- items:
|
||||
- const: atmel,at91rm9200-sdramc
|
||||
- const: syscon
|
||||
- items:
|
||||
- const: microchip,sama7d65-uddrc
|
||||
- const: microchip,sama7g5-uddrc
|
||||
- enum:
|
||||
- atmel,at91sam9260-sdramc
|
||||
- atmel,at91sam9g45-ddramc
|
||||
- atmel,sama5d3-ddramc
|
||||
- microchip,sam9x60-ddramc
|
||||
- microchip,sam9x7-ddramc
|
||||
- microchip,sama7g5-uddrc
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
minItems: 1
|
||||
maxItems: 2
|
||||
|
||||
clock-names:
|
||||
minItems: 1
|
||||
items:
|
||||
- const: ddrck
|
||||
- const: mpddr
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/at91.h>
|
||||
ramc@ffffe400 {
|
||||
compatible = "atmel,at91sam9g45-ddramc";
|
||||
reg = <0xffffe400 0x200>;
|
||||
clocks = <&pmc PMC_TYPE_SYSTEM 2>;
|
||||
clock-names = "ddrck";
|
||||
};
|
||||
...
|
||||
@@ -0,0 +1,69 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/arm/atmel,at91rm9200-st.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Atmel System Timer
|
||||
|
||||
maintainers:
|
||||
- Nicolas Ferre <nicolas.ferre@microchip.com>
|
||||
- Claudiu Beznea <claudiu.beznea@tuxon.dev>
|
||||
|
||||
description:
|
||||
The System Timer (ST) module in AT91RM9200 provides periodic tick and
|
||||
alarm capabilities. It is exposed as a simple multi-function device
|
||||
(simple-mfd + syscon) because it shares its register space and interrupt
|
||||
with other System Controller blocks.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
items:
|
||||
- const: atmel,at91rm9200-st
|
||||
- const: syscon
|
||||
- const: simple-mfd
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
maxItems: 1
|
||||
|
||||
"#address-cells":
|
||||
const: 1
|
||||
|
||||
"#size-cells":
|
||||
const: 1
|
||||
|
||||
patternProperties:
|
||||
"^watchdog@[0-9a-f]+$":
|
||||
$ref: /schemas/watchdog/atmel,at91rm9200-wdt.yaml#
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- interrupts
|
||||
- clocks
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
timer@fffffd00 {
|
||||
compatible = "atmel,at91rm9200-st", "syscon", "simple-mfd";
|
||||
reg = <0xfffffd00 0x100>;
|
||||
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
|
||||
clocks = <&slow_xtal>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
watchdog@fffffd40 {
|
||||
compatible = "atmel,at91rm9200-wdt";
|
||||
reg = <0xfffffd40 0x40>;
|
||||
};
|
||||
};
|
||||
...
|
||||
@@ -0,0 +1,49 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/arm/atmel,at91sam9260-pit.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Atmel AT91SAM9260 Periodic Interval Timer (PIT)
|
||||
|
||||
maintainers:
|
||||
- Nicolas Ferre <nicolas.ferre@microchip.com>
|
||||
- Claudiu Beznea <claudiu.beznea@tuxon.dev>
|
||||
|
||||
description:
|
||||
The Periodic Interval Timer (PIT) is part of the System Controller of
|
||||
various Microchip 32-bit ARM-based SoCs (formerly Atmel AT91 series).
|
||||
It is a simple down-counter timer used mainly as the kernel tick source.
|
||||
The PIT is clocked from the slow clock and shares a single IRQ line with
|
||||
other System Controller peripherals.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: atmel,at91sam9260-pit
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- interrupts
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
timer@fffffd30 {
|
||||
compatible = "atmel,at91sam9260-pit";
|
||||
reg = <0xfffffd30 0x10>;
|
||||
interrupts = <1 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk32k>;
|
||||
};
|
||||
...
|
||||
@@ -1,48 +0,0 @@
|
||||
Atmel system registers
|
||||
|
||||
Chipid required properties:
|
||||
- compatible: Should be "atmel,sama5d2-chipid" or "microchip,sama7g5-chipid"
|
||||
"microchip,sama7d65-chipid"
|
||||
- reg : Should contain registers location and length
|
||||
|
||||
PIT Timer required properties:
|
||||
- compatible: Should be "atmel,at91sam9260-pit"
|
||||
- reg: Should contain registers location and length
|
||||
- interrupts: Should contain interrupt for the PIT which is the IRQ line
|
||||
shared across all System Controller members.
|
||||
|
||||
PIT64B Timer required properties:
|
||||
- compatible: Should be "microchip,sam9x60-pit64b" or
|
||||
"microchip,sam9x7-pit64b", "microchip,sam9x60-pit64b"
|
||||
"microchip,sama7d65-pit64b", "microchip,sam9x60-pit64b"
|
||||
- reg: Should contain registers location and length
|
||||
- interrupts: Should contain interrupt for PIT64B timer
|
||||
- clocks: Should contain the available clock sources for PIT64B timer.
|
||||
|
||||
System Timer (ST) required properties:
|
||||
- compatible: Should be "atmel,at91rm9200-st", "syscon", "simple-mfd"
|
||||
- reg: Should contain registers location and length
|
||||
- interrupts: Should contain interrupt for the ST which is the IRQ line
|
||||
shared across all System Controller members.
|
||||
- clocks: phandle to input clock.
|
||||
Its subnodes can be:
|
||||
- watchdog: compatible should be "atmel,at91rm9200-wdt"
|
||||
|
||||
RAMC SDRAM/DDR Controller required properties:
|
||||
- compatible: Should be "atmel,at91rm9200-sdramc", "syscon" or
|
||||
"atmel,at91sam9260-sdramc" or
|
||||
"atmel,at91sam9g45-ddramc" or
|
||||
"atmel,sama5d3-ddramc" or
|
||||
"microchip,sam9x60-ddramc" or
|
||||
"microchip,sama7g5-uddrc" or
|
||||
"microchip,sama7d65-uddrc", "microchip,sama7g5-uddrc" or
|
||||
"microchip,sam9x7-ddramc", "atmel,sama5d3-ddramc".
|
||||
- reg: Should contain registers location and length
|
||||
|
||||
Examples:
|
||||
|
||||
ramc0: ramc@ffffe800 {
|
||||
compatible = "atmel,at91sam9g45-ddramc";
|
||||
reg = <0xffffe800 0x200>;
|
||||
};
|
||||
|
||||
@@ -28,6 +28,9 @@ properties:
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
|
||||
clocks:
|
||||
maxItems: 2
|
||||
|
||||
@@ -39,6 +42,7 @@ properties:
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- '#clock-cells'
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
@@ -47,4 +51,5 @@ examples:
|
||||
smc1@40410000 {
|
||||
compatible = "fsl,imx7ulp-smc1";
|
||||
reg = <0x40410000 0x1000>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
@@ -996,6 +996,14 @@ properties:
|
||||
- const: engicam,icore-mx8mm # i.MX8MM Engicam i.Core MX8M Mini SoM
|
||||
- const: fsl,imx8mm
|
||||
|
||||
- description: Ka-Ro Electronics TX8M-1610 based boards
|
||||
items:
|
||||
- enum:
|
||||
- gocontroll,moduline-iv-306-d
|
||||
- gocontroll,moduline-mini-111
|
||||
- const: karo,tx8m-1610
|
||||
- const: fsl,imx8mm
|
||||
|
||||
- description: Kontron BL i.MX8MM (N801X S) Board
|
||||
items:
|
||||
- const: kontron,imx8mm-bl
|
||||
@@ -1041,6 +1049,13 @@ properties:
|
||||
- const: phytec,imx8mm-phycore-som # phyCORE-i.MX8MM SoM
|
||||
- const: fsl,imx8mm
|
||||
|
||||
- description: SolidRun i.MX8MM SoM based boards
|
||||
items:
|
||||
- enum:
|
||||
- solidrun,imx8mm-hummingboard-ripple # SolidRun i.MX8MM SoM on HummingBoard Ripple
|
||||
- const: solidrun,imx8mm-sr-som
|
||||
- const: fsl,imx8mm
|
||||
|
||||
- description: Variscite VAR-SOM-MX8MM based boards
|
||||
items:
|
||||
- const: variscite,var-som-mx8mm-symphony
|
||||
@@ -1069,6 +1084,7 @@ properties:
|
||||
- fsl,imx8mn-ddr4-evk # i.MX8MN DDR4 EVK Board
|
||||
- fsl,imx8mn-evk # i.MX8MN LPDDR4 EVK Board
|
||||
- gw,imx8mn-gw7902 # i.MX8MM Gateworks Board
|
||||
- solidrun,solidsense-n8-compact # SolidRun SolidSense N8 Compact
|
||||
- const: fsl,imx8mn
|
||||
|
||||
- description: ifm i.MX8MN VHIP4 based boards
|
||||
@@ -1106,6 +1122,7 @@ properties:
|
||||
- beacon,imx8mp-beacon-kit # i.MX8MP Beacon Development Kit
|
||||
- dmo,imx8mp-data-modul-edm-sbc # i.MX8MP eDM SBC
|
||||
- emcraft,imx8mp-navqp # i.MX8MP Emcraft Systems NavQ+ Kit
|
||||
- fsl,imx8mp-ab2 # i.MX8MP Audio Board V2
|
||||
- fsl,imx8mp-evk # i.MX8MP EVK Board
|
||||
- fsl,imx8mp-evk-revb4 # i.MX8MP EVK Rev B4 Board
|
||||
- fsl,imx8mp-frdm # i.MX8MP Freedom Board
|
||||
@@ -1225,6 +1242,7 @@ properties:
|
||||
items:
|
||||
- enum:
|
||||
- solidrun,imx8mp-cubox-m # SolidRun i.MX8MP SoM on CuBox-M
|
||||
- solidrun,imx8mp-hummingboard-iiot # SolidRun i.MX8MP SoM on HummingBoard IIoT
|
||||
- solidrun,imx8mp-hummingboard-mate # SolidRun i.MX8MP SoM on HummingBoard Mate
|
||||
- solidrun,imx8mp-hummingboard-pro # SolidRun i.MX8MP SoM on HummingBoard Pro
|
||||
- solidrun,imx8mp-hummingboard-pulse # SolidRun i.MX8MP SoM on HummingBoard Pulse
|
||||
@@ -1420,6 +1438,16 @@ properties:
|
||||
- const: tq,imx8dxp-tqma8xdps # TQ-Systems GmbH TQMa8XDPS SOM
|
||||
- const: fsl,imx8dxp
|
||||
|
||||
- description:
|
||||
TQMa8x is a series of SOM featuring NXP i.MX8 system-on-chip
|
||||
variants. It is designed to be clicked on different carrier boards
|
||||
MBa8x is the starterkit
|
||||
items:
|
||||
- enum:
|
||||
- tq,imx8qm-tqma8qm-mba8x # TQ-Systems GmbH TQMa8QM SOM on MBa8x
|
||||
- const: tq,imx8qm-tqma8qm # TQ-Systems GmbH TQMa8QM SOM
|
||||
- const: fsl,imx8qm
|
||||
|
||||
- description: i.MX8ULP based Boards
|
||||
items:
|
||||
- enum:
|
||||
@@ -1432,6 +1460,7 @@ properties:
|
||||
- enum:
|
||||
- fsl,imx91-11x11-evk # i.MX91 11x11 EVK Board
|
||||
- fsl,imx91-11x11-frdm # FRDM i.MX91 Development Board
|
||||
- fsl,imx91-11x11-frdm-s # FRDM i.MX91S Development Board
|
||||
- const: fsl,imx91
|
||||
|
||||
- description: i.MX93 based Boards
|
||||
@@ -1441,6 +1470,7 @@ properties:
|
||||
- fsl,imx93-11x11-evk # i.MX93 11x11 EVK Board
|
||||
- fsl,imx93-11x11-frdm # i.MX93 11x11 FRDM Board
|
||||
- fsl,imx93-14x14-evk # i.MX93 14x14 EVK Board
|
||||
- fsl,imx93-wireless-evk # i.MX93 and IW610G WLCSP (Wi-Fi + BLE + 802.15.4) SiP EVK Board
|
||||
- const: fsl,imx93
|
||||
|
||||
- description: i.MX94 based Boards
|
||||
@@ -1477,6 +1507,36 @@ properties:
|
||||
- const: toradex,smarc-imx95 # Toradex SMARC iMX95 Module
|
||||
- const: fsl,imx95
|
||||
|
||||
- description: Toradex Boards with Verdin iMX95 Modules
|
||||
items:
|
||||
- enum:
|
||||
- toradex,verdin-imx95-nonwifi-dahlia # Verdin iMX95 Module on Dahlia
|
||||
- toradex,verdin-imx95-nonwifi-dev # Verdin iMX95 Module on Verdin Development Board
|
||||
- toradex,verdin-imx95-nonwifi-ivy # Verdin iMX95 Module on Ivy
|
||||
- toradex,verdin-imx95-nonwifi-mallow # Verdin iMX95 Module on Mallow
|
||||
- toradex,verdin-imx95-nonwifi-yavia # Verdin iMX95 Module on Yavia
|
||||
- const: toradex,verdin-imx95-nonwifi # Verdin iMX95 Module without Wi-Fi / BT
|
||||
- const: toradex,verdin-imx95 # Verdin iMX95 Module
|
||||
- const: fsl,imx95
|
||||
|
||||
- description: Toradex Boards with Verdin iMX95 Wi-Fi / BT Modules
|
||||
items:
|
||||
- enum:
|
||||
- toradex,verdin-imx95-wifi-dahlia # Verdin iMX95 Wi-Fi / BT Module on Dahlia
|
||||
- toradex,verdin-imx95-wifi-dev # Verdin iMX95 Wi-Fi / BT Module on Verdin Development B.
|
||||
- toradex,verdin-imx95-wifi-ivy # Verdin iMX95 Wi-Fi / BT Module on Ivy
|
||||
- toradex,verdin-imx95-wifi-mallow # Verdin iMX95 Wi-Fi / BT Module on Mallow
|
||||
- toradex,verdin-imx95-wifi-yavia # Verdin iMX95 Wi-Fi / BT Module on Yavia
|
||||
- const: toradex,verdin-imx95-wifi # Verdin iMX95 Wi-Fi / BT Module
|
||||
- const: toradex,verdin-imx95 # Verdin iMX95 Module
|
||||
- const: fsl,imx95
|
||||
|
||||
- description: Variscite DART-MX95 based Boards
|
||||
items:
|
||||
- const: variscite,var-dart-mx95-sonata # Variscite DART-MX95 SOM on Sonata Development Board
|
||||
- const: variscite,var-dart-mx95 # Variscite DART-MX95 SOM
|
||||
- const: fsl,imx95
|
||||
|
||||
- description: i.MXRT1050 based Boards
|
||||
items:
|
||||
- enum:
|
||||
@@ -1522,11 +1582,14 @@ properties:
|
||||
soldered on an adapter board or for the connector variant
|
||||
MBa93xxLA mainboard is a single board computer using the solderable
|
||||
SOM variant
|
||||
MBa93xxLA-MINI mainboard is a single board computer using the solderable
|
||||
SOM variant
|
||||
items:
|
||||
- enum:
|
||||
- tq,imx93-tqma9352-mba91xxca # TQ-Systems GmbH i.MX93 TQMa93xxCA/LA SOM on MBa91xxCA
|
||||
- tq,imx93-tqma9352-mba93xxca # TQ-Systems GmbH i.MX93 TQMa93xxCA/LA SOM on MBa93xxCA
|
||||
- tq,imx93-tqma9352-mba93xxla # TQ-Systems GmbH i.MX93 TQMa93xxLA SOM on MBa93xxLA SBC
|
||||
- tq,imx93-tqma9352-mba93xxla-mini # TQ-Systems GmbH i.MX93 TQMa93xxLA SOM on MBa93xxLA-MINI SBC
|
||||
- const: tq,imx93-tqma9352 # TQ-Systems GmbH i.MX93 TQMa93xxCA/LA SOM
|
||||
- const: fsl,imx93
|
||||
|
||||
@@ -1545,6 +1608,12 @@ properties:
|
||||
- const: phytec,imx93-phycore-som # phyCORE-i.MX93 SoM
|
||||
- const: fsl,imx93
|
||||
|
||||
- description: Variscite DART-MX91 based boards
|
||||
items:
|
||||
- const: variscite,var-dart-mx91-sonata # Variscite DART-MX91 on Sonata Development Board
|
||||
- const: variscite,var-dart-mx91 # Variscite DART-MX91 SOM
|
||||
- const: fsl,imx91
|
||||
|
||||
- description: Variscite VAR-SOM-MX93 based boards
|
||||
items:
|
||||
- const: variscite,var-som-mx93-symphony
|
||||
@@ -1557,6 +1626,17 @@ properties:
|
||||
- const: kontron,imx93-osm-s # Kontron OSM-S i.MX93 SoM
|
||||
- const: fsl,imx93
|
||||
|
||||
- description:
|
||||
TQMa95xxLA is a series of SOM featuring NXP i.MX95 SoC variants,
|
||||
designed to be soldered on different carrier boards.
|
||||
MBa95xxCA is a carrier reference design / starter kit that allows
|
||||
to use TQMa95xxLA via an adaper board.
|
||||
items:
|
||||
- enum:
|
||||
- tq,imx95-tqma9596la-mba95xxca # TQ-Systems GmbH i.MX95 TQMa95xxLA SOM on MBa95xxCA
|
||||
- const: tq,imx95-tqma9596la # TQ-Systems GmbH i.MX95 TQMa95xxLA SOM
|
||||
- const: fsl,imx95
|
||||
|
||||
- description:
|
||||
TQMa95xxSA is a series of SOM featuring NXP i.MX95 SoC variants.
|
||||
It has the SMARC form factor and is designed to be placed on
|
||||
@@ -1827,6 +1907,12 @@ properties:
|
||||
- fsl,s32v234-evb # S32V234-EVB2 Customer Evaluation Board
|
||||
- const: fsl,s32v234
|
||||
|
||||
- description: S32N79 based Boards
|
||||
items:
|
||||
- enum:
|
||||
- nxp,s32n79-rdb
|
||||
- const: nxp,s32n79
|
||||
|
||||
- description: Traverse LS1088A based Boards
|
||||
items:
|
||||
- enum:
|
||||
|
||||
@@ -0,0 +1,68 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/arm/microchip,sam9x60-pit64b.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Microchip PIT64B 64-bit Periodic Interval Timer
|
||||
|
||||
maintainers:
|
||||
- Nicolas Ferre <nicolas.ferre@microchip.com>
|
||||
- Claudiu Beznea <claudiu.beznea@tuxon.dev>
|
||||
|
||||
description:
|
||||
The Microchip PIT64B is a 64-bit periodic interval timer used in
|
||||
several modern Microchip ARM SoCs including SAM9X60, SAM9X7 and
|
||||
SAMA7D65 families. It provides extended timing range, flexible
|
||||
clock selection and supports both periodic and one-shot interrupt
|
||||
generation modes.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
oneOf:
|
||||
- const: microchip,sam9x60-pit64b
|
||||
- items:
|
||||
- enum:
|
||||
- microchip,sam9x7-pit64b
|
||||
- microchip,sama7d65-pit64b
|
||||
- microchip,sama7g5-pit64b
|
||||
- const: microchip,sam9x60-pit64b
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
minItems: 1
|
||||
maxItems: 2
|
||||
|
||||
clock-names:
|
||||
minItems: 1
|
||||
maxItems: 2
|
||||
items:
|
||||
enum:
|
||||
- pclk
|
||||
- gclk
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- interrupts
|
||||
- clocks
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
#include <dt-bindings/clock/at91.h>
|
||||
timer@f0028000 {
|
||||
compatible = "microchip,sama7g5-pit64b", "microchip,sam9x60-pit64b";
|
||||
reg = <0xf0028000 0x100>;
|
||||
interrupts = <37 IRQ_TYPE_LEVEL_HIGH 7>;
|
||||
clocks = <&pmc PMC_TYPE_PERIPHERAL 37>, <&pmc PMC_TYPE_GCK 37>;
|
||||
clock-names = "pclk", "gclk";
|
||||
};
|
||||
...
|
||||
@@ -0,0 +1,41 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/arm/microchip,sama7g5-chipid.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Atmel/Microchip RAMC SDRAM/DDR Controller
|
||||
|
||||
maintainers:
|
||||
- Nicolas Ferre <nicolas.ferre@microchip.com>
|
||||
- Claudiu Beznea <claudiu.beznea@tuxon.dev>
|
||||
|
||||
description:
|
||||
This binding describes the Atmel/Microchip Chip ID register block used
|
||||
for SoC identification and revision information. It requires compatible
|
||||
strings matching specific SoC families and a reg property defining the
|
||||
register address and size.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- atmel,sama5d2-chipid
|
||||
- microchip,sama7d65-chipid
|
||||
- microchip,sama7g5-chipid
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
chipid@fc069000 {
|
||||
compatible = "atmel,sama5d2-chipid";
|
||||
reg = <0xfc069000 0x8>;
|
||||
};
|
||||
...
|
||||
@@ -22,5 +22,27 @@ properties:
|
||||
- phytec,phy3250
|
||||
- const: nxp,lpc3250
|
||||
|
||||
- items:
|
||||
- enum:
|
||||
- ea,lpc4357-developers-kit
|
||||
- const: nxp,lpc4357
|
||||
- const: nxp,lpc4350
|
||||
|
||||
- items:
|
||||
- enum:
|
||||
- ciaa,lpc4337
|
||||
- const: nxp,lpc4337
|
||||
- const: nxp,lpc4350
|
||||
|
||||
- items:
|
||||
- enum:
|
||||
- hitex,lpc4350-eval-board
|
||||
- const: nxp,lpc4350
|
||||
|
||||
- items:
|
||||
- enum:
|
||||
- myir,myd-lpc4357
|
||||
- const: nxp,lpc4357
|
||||
|
||||
additionalProperties: true
|
||||
...
|
||||
|
||||
@@ -131,6 +131,33 @@ properties:
|
||||
- const: toradex,apalis-tk1-v1.2
|
||||
- const: toradex,apalis-tk1
|
||||
- const: nvidia,tegra124
|
||||
- items:
|
||||
- const: google,nyan-big-rev7
|
||||
- const: google,nyan-big-rev6
|
||||
- const: google,nyan-big-rev5
|
||||
- const: google,nyan-big-rev4
|
||||
- const: google,nyan-big-rev3
|
||||
- const: google,nyan-big-rev2
|
||||
- const: google,nyan-big-rev1
|
||||
- const: google,nyan-big-rev0
|
||||
- const: google,nyan-big
|
||||
- const: google,nyan
|
||||
- const: nvidia,tegra124
|
||||
- items:
|
||||
- const: google,nyan-blaze-rev10
|
||||
- const: google,nyan-blaze-rev9
|
||||
- const: google,nyan-blaze-rev8
|
||||
- const: google,nyan-blaze-rev7
|
||||
- const: google,nyan-blaze-rev6
|
||||
- const: google,nyan-blaze-rev5
|
||||
- const: google,nyan-blaze-rev4
|
||||
- const: google,nyan-blaze-rev3
|
||||
- const: google,nyan-blaze-rev2
|
||||
- const: google,nyan-blaze-rev1
|
||||
- const: google,nyan-blaze-rev0
|
||||
- const: google,nyan-blaze
|
||||
- const: google,nyan
|
||||
- const: nvidia,tegra124
|
||||
- items:
|
||||
- enum:
|
||||
- nvidia,norrin
|
||||
@@ -184,17 +211,35 @@ properties:
|
||||
- const: nvidia,tegra124
|
||||
- items:
|
||||
- enum:
|
||||
- nvidia,darcy
|
||||
- nvidia,p2371-0000
|
||||
- nvidia,p2371-2180
|
||||
- nvidia,p2571
|
||||
- nvidia,p2894-0050-a08
|
||||
- nvidia,p3450-0000
|
||||
- const: nvidia,tegra210
|
||||
- items:
|
||||
- const: nvidia,p3541-0000
|
||||
- const: nvidia,p3450-0000
|
||||
- const: nvidia,tegra210
|
||||
- description: NVIDIA Jetson Nano
|
||||
items:
|
||||
- const: nvidia,p3450-0000
|
||||
- const: nvidia,tegra210
|
||||
- description: NVIDIA Shield TV
|
||||
items:
|
||||
- const: nvidia,p2894-0050-a08
|
||||
- const: nvidia,darcy
|
||||
- const: nvidia,tegra210
|
||||
- description: Google Pixel C
|
||||
items:
|
||||
- const: google,smaug-rev8
|
||||
- const: google,smaug-rev7
|
||||
- const: google,smaug-rev6
|
||||
- const: google,smaug-rev5
|
||||
- const: google,smaug-rev4
|
||||
- const: google,smaug-rev3
|
||||
- const: google,smaug-rev2
|
||||
- const: google,smaug-rev1
|
||||
- const: google,smaug
|
||||
- const: nvidia,tegra210
|
||||
- description: Jetson TX2 Developer Kit
|
||||
items:
|
||||
- const: nvidia,p2771-0000
|
||||
@@ -268,5 +313,10 @@ properties:
|
||||
- const: nvidia,p3971-0089+p3834-0008
|
||||
- const: nvidia,p3834-0008
|
||||
- const: nvidia,tegra264
|
||||
- description: Jetson AGX Thor Developer Kit
|
||||
items:
|
||||
- const: nvidia,p4071-0000+p3834-0008
|
||||
- const: nvidia,p3834-0008
|
||||
- const: nvidia,tegra264
|
||||
|
||||
additionalProperties: true
|
||||
|
||||
@@ -48,6 +48,10 @@ properties:
|
||||
- nvidia,tegra234-dce-fabric
|
||||
- nvidia,tegra234-rce-fabric
|
||||
- nvidia,tegra234-sce-fabric
|
||||
- nvidia,tegra238-ape-fabric
|
||||
- nvidia,tegra238-aon-fabric
|
||||
- nvidia,tegra238-bpmp-fabric
|
||||
- nvidia,tegra238-cbb-fabric
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
@@ -0,0 +1,76 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/bus/st,stm32mp131-dbg-bus.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: STM32 Coresight bus
|
||||
|
||||
maintainers:
|
||||
- Gatien Chevallier <gatien.chevallier@foss.st.com>
|
||||
|
||||
description:
|
||||
The STM32 debug bus is in charge of checking the debug configuration
|
||||
of the platform before probing the peripheral drivers that rely on the debug
|
||||
domain.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
items:
|
||||
- enum:
|
||||
- st,stm32mp131-dbg-bus
|
||||
- st,stm32mp151-dbg-bus
|
||||
|
||||
"#address-cells":
|
||||
const: 1
|
||||
|
||||
"#size-cells":
|
||||
const: 1
|
||||
|
||||
ranges:
|
||||
minItems: 1
|
||||
maxItems: 2
|
||||
|
||||
"#access-controller-cells":
|
||||
const: 1
|
||||
description:
|
||||
Contains the debug profile necessary to access the peripheral.
|
||||
|
||||
patternProperties:
|
||||
"@[0-9a-f]+$":
|
||||
description: Debug related peripherals
|
||||
type: object
|
||||
|
||||
additionalProperties: true
|
||||
|
||||
required:
|
||||
- access-controllers
|
||||
|
||||
required:
|
||||
- "#access-controller-cells"
|
||||
- "#address-cells"
|
||||
- "#size-cells"
|
||||
- compatible
|
||||
- ranges
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/stm32mp1-clks.h>
|
||||
|
||||
dbg_bus: bus@50080000 {
|
||||
compatible = "st,stm32mp131-dbg-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
#access-controller-cells = <1>;
|
||||
ranges = <0x50080000 0x50080000 0x3f80000>;
|
||||
|
||||
cti@50094000 {
|
||||
compatible = "arm,coresight-cti", "arm,primecell";
|
||||
reg = <0x50094000 0x1000>;
|
||||
clocks = <&rcc CK_DBG>;
|
||||
clock-names = "apb_pclk";
|
||||
access-controllers = <&dbg_bus 0>;
|
||||
};
|
||||
};
|
||||
@@ -1,63 +0,0 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
# Copyright (C) 2020 BAIKAL ELECTRONICS, JSC
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/cache/baikal,bt1-l2-ctl.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Baikal-T1 L2-cache Control Block
|
||||
|
||||
maintainers:
|
||||
- Serge Semin <fancer.lancer@gmail.com>
|
||||
|
||||
description: |
|
||||
By means of the System Controller Baikal-T1 SoC exposes a few settings to
|
||||
tune the MIPS P5600 CM2 L2 cache performance up. In particular it's possible
|
||||
to change the Tag, Data and Way-select RAM access latencies. Baikal-T1
|
||||
L2-cache controller block is responsible for the tuning. Its DT node is
|
||||
supposed to be a child of the system controller.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: baikal,bt1-l2-ctl
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
baikal,l2-ws-latency:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
description: Cycles of latency for Way-select RAM accesses
|
||||
default: 0
|
||||
minimum: 0
|
||||
maximum: 3
|
||||
|
||||
baikal,l2-tag-latency:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
description: Cycles of latency for Tag RAM accesses
|
||||
default: 0
|
||||
minimum: 0
|
||||
maximum: 3
|
||||
|
||||
baikal,l2-data-latency:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
description: Cycles of latency for Data RAM accesses
|
||||
default: 1
|
||||
minimum: 0
|
||||
maximum: 3
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
required:
|
||||
- compatible
|
||||
|
||||
examples:
|
||||
- |
|
||||
l2@1f04d028 {
|
||||
compatible = "baikal,bt1-l2-ctl";
|
||||
reg = <0x1f04d028 0x004>;
|
||||
|
||||
baikal,l2-ws-latency = <1>;
|
||||
baikal,l2-tag-latency = <1>;
|
||||
baikal,l2-data-latency = <2>;
|
||||
};
|
||||
...
|
||||
@@ -33,6 +33,7 @@ properties:
|
||||
- qcom,sc7280-llcc
|
||||
- qcom,sc8180x-llcc
|
||||
- qcom,sc8280xp-llcc
|
||||
- qcom,sdm670-llcc
|
||||
- qcom,sdm845-llcc
|
||||
- qcom,sm6350-llcc
|
||||
- qcom,sm7150-llcc
|
||||
@@ -204,6 +205,7 @@ allOf:
|
||||
contains:
|
||||
enum:
|
||||
- qcom,sc7280-llcc
|
||||
- qcom,sdm670-llcc
|
||||
then:
|
||||
properties:
|
||||
reg:
|
||||
|
||||
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Reference in New Issue
Block a user