mirror of
https://github.com/linux-msm/laptops-kernel.git
synced 2026-08-13 14:19:53 -07:00
Merge branches 'clk-tenstorrent', 'clk-rockchip', 'clk-imx' and 'clk-allwinner' into clk-next
* clk-tenstorrent: clk: tenstorrent: Add Atlantis clock controller driver reset: tenstorrent: Add reset controller for Atlantis dt-bindings: clk: tenstorrent: Add tenstorrent,atlantis-prcm-rcpu * clk-rockchip: clk: rockchip: rk3568: Add PCIe pipe clock gates clk: rockchip: Add clock controller for the RV1103B dt-bindings: clock: rockchip: Add RV1103B CRU support * clk-imx: clk: imx8mq: Correct the CSI PHY sels clk: vf610: Add support for the Ethernet switch clocks dt-bindings: clock: vf610: Add definitions for MTIP L2 switch dt-bindings: clock: vf610: Drop VF610_CLK_END define clk: vf610: Move VF610_CLK_END define to clk-vf610 driver clk: imx: imx8-acm: fix flags for acm clocks clk: imx: imx6q: Fix device node reference leak in of_assigned_ldb_sels() clk: imx: imx6q: Fix device node reference leak in pll6_bypassed() clk: imx: fracn-gppll: Add 477.4MHz support clk: imx: fracn-gppll: Add 333.333333 MHz support clk: imx: pll14xx: Use unsigned format specifier dt-bindings: clock: imx6q[ul]-clock: add optional clock enet[1]_ref_pad * clk-allwinner: clk: sunxi-ng: sun55i-a523-r: Add missing r-spi module clock
This commit is contained in:
Stephen Boyd
@@ -29,20 +29,24 @@ properties:
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const: 1
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clocks:
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minItems: 5
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items:
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- description: 24m osc
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- description: 32k osc
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- description: ckih1 clock input
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- description: anaclk1 clock input
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- description: anaclk2 clock input
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- description: clock input from enet ref pad
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clock-names:
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minItems: 5
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items:
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- const: osc
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- const: ckil
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- const: ckih1
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- const: anaclk1
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- const: anaclk2
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- const: enet_ref_pad
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fsl,pmic-stby-poweroff:
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$ref: /schemas/types.yaml#/definitions/flag
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@@ -29,18 +29,22 @@ properties:
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const: 1
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clocks:
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minItems: 4
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items:
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- description: 32k osc
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- description: 24m osc
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- description: ipp_di0 clock input
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- description: ipp_di1 clock input
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- description: clock input from enet1 ref pad
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clock-names:
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minItems: 4
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items:
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- const: ckil
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- const: osc
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- const: ipp_di0
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- const: ipp_di1
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- const: enet1_ref_pad
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required:
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- compatible
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@@ -17,6 +17,7 @@ description:
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properties:
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compatible:
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enum:
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- rockchip,rv1103b-cru
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- rockchip,rv1126b-cru
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reg:
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@@ -0,0 +1,54 @@
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/tenstorrent,atlantis-prcm-rcpu.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Tenstorrent Atlantis PRCM (Power, Reset, Clock Management) Module
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maintainers:
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- Anirudh Srinivasan <asrinivasan@oss.tenstorrent.com>
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description:
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Multifunctional register block found in Tenstorrent Atlantis SoC whose main
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function is to control clocks and resets. This block is instantiated multiple
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times in the SoC, each block controls clock and resets for a different
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subsystem. RCPU prcm serves low speed IO interfaces.
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properties:
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compatible:
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enum:
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- tenstorrent,atlantis-prcm-rcpu
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reg:
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maxItems: 1
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clocks:
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maxItems: 1
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"#clock-cells":
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const: 1
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description:
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See <dt-bindings/clock/tenstorrent,atlantis-prcm-rcpu.h> for valid indices.
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"#reset-cells":
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const: 1
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required:
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- compatible
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- reg
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- clocks
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- "#clock-cells"
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- "#reset-cells"
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additionalProperties: false
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examples:
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- |
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clock-controller@a8000000 {
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compatible = "tenstorrent,atlantis-prcm-rcpu";
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reg = <0xa8000000 0x10000>;
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clocks = <&osc_24m>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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@@ -22812,8 +22812,12 @@ M: Joel Stanley <jms@oss.tenstorrent.com>
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L: linux-riscv@lists.infradead.org
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S: Maintained
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T: git https://github.com/tenstorrent/linux.git
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F: Documentation/devicetree/bindings/clock/tenstorrent,atlantis-prcm-rcpu.yaml
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F: Documentation/devicetree/bindings/riscv/tenstorrent.yaml
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F: arch/riscv/boot/dts/tenstorrent/
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F: drivers/clk/tenstorrent/
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F: drivers/reset/reset-tenstorrent-atlantis.c
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F: include/dt-bindings/clock/tenstorrent,atlantis-prcm-rcpu.h
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RISC-V THEAD SoC SUPPORT
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M: Drew Fustini <fustini@kernel.org>
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@@ -532,6 +532,7 @@ source "drivers/clk/starfive/Kconfig"
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source "drivers/clk/sunxi/Kconfig"
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source "drivers/clk/sunxi-ng/Kconfig"
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source "drivers/clk/tegra/Kconfig"
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source "drivers/clk/tenstorrent/Kconfig"
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source "drivers/clk/thead/Kconfig"
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source "drivers/clk/stm32/Kconfig"
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source "drivers/clk/ti/Kconfig"
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@@ -156,6 +156,7 @@ obj-y += starfive/
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obj-$(CONFIG_ARCH_SUNXI) += sunxi/
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obj-y += sunxi-ng/
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obj-$(CONFIG_ARCH_TEGRA) += tegra/
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obj-y += tenstorrent/
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obj-$(CONFIG_ARCH_THEAD) += thead/
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obj-y += ti/
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obj-$(CONFIG_CLK_UNIPHIER) += uniphier/
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@@ -85,9 +85,11 @@ static const struct imx_fracn_gppll_rate_table fracn_tbl[] = {
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PLL_FRACN_GP(519750000U, 173, 25, 100, 1, 8),
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PLL_FRACN_GP(498000000U, 166, 0, 1, 0, 8),
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PLL_FRACN_GP(484000000U, 121, 0, 1, 0, 6),
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PLL_FRACN_GP(477400000U, 119, 35, 100, 0, 6),
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PLL_FRACN_GP(445333333U, 167, 0, 1, 0, 9),
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PLL_FRACN_GP(400000000U, 200, 0, 1, 0, 12),
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PLL_FRACN_GP(393216000U, 163, 84, 100, 0, 10),
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PLL_FRACN_GP(333333333U, 125, 0, 1, 1, 9),
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PLL_FRACN_GP(332600000U, 138, 584, 1000, 0, 10),
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PLL_FRACN_GP(300000000U, 150, 0, 1, 0, 12),
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PLL_FRACN_GP(241900000U, 201, 584, 1000, 0, 20),
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@@ -188,9 +188,11 @@ static void of_assigned_ldb_sels(struct device_node *node,
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}
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if (clkspec.np != node || clkspec.args[0] >= IMX6QDL_CLK_END) {
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pr_err("ccm: parent clock %d not in ccm\n", index);
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of_node_put(clkspec.np);
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return;
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}
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parent = clkspec.args[0];
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of_node_put(clkspec.np);
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rc = of_parse_phandle_with_args(node, "assigned-clocks",
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"#clock-cells", index, &clkspec);
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@@ -198,9 +200,11 @@ static void of_assigned_ldb_sels(struct device_node *node,
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return;
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if (clkspec.np != node || clkspec.args[0] >= IMX6QDL_CLK_END) {
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pr_err("ccm: child clock %d not in ccm\n", index);
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of_node_put(clkspec.np);
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return;
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}
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child = clkspec.args[0];
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of_node_put(clkspec.np);
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if (child != IMX6QDL_CLK_LDB_DI0_SEL &&
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child != IMX6QDL_CLK_LDB_DI1_SEL)
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@@ -238,8 +242,11 @@ static bool pll6_bypassed(struct device_node *node)
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return false;
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if (clkspec.np == node &&
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clkspec.args[0] == IMX6QDL_PLL6_BYPASS)
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clkspec.args[0] == IMX6QDL_PLL6_BYPASS) {
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of_node_put(clkspec.np);
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break;
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}
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of_node_put(clkspec.np);
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}
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/* PLL6 bypass is not part of the assigned clock list */
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@@ -249,6 +256,9 @@ static bool pll6_bypassed(struct device_node *node)
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ret = of_parse_phandle_with_args(node, "assigned-clock-parents",
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"#clock-cells", index, &clkspec);
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if (!ret)
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of_node_put(clkspec.np);
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if (clkspec.args[0] != IMX6QDL_CLK_PLL6)
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return true;
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@@ -371,7 +371,8 @@ static int imx8_acm_clk_probe(struct platform_device *pdev)
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for (i = 0; i < priv->soc_data->num_sels; i++) {
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hws[sels[i].clkid] = devm_clk_hw_register_mux_parent_data_table(dev,
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sels[i].name, sels[i].parents,
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sels[i].num_parents, 0,
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sels[i].num_parents,
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CLK_SET_RATE_NO_REPARENT,
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base + sels[i].reg,
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sels[i].shift, sels[i].width,
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0, NULL, NULL);
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@@ -237,7 +237,7 @@ static const char * const imx8mq_dsi_esc_sels[] = {"osc_25m", "sys2_pll_100m", "
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static const char * const imx8mq_csi1_core_sels[] = {"osc_25m", "sys1_pll_266m", "sys2_pll_250m", "sys1_pll_800m",
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"sys2_pll_1000m", "sys3_pll_out", "audio_pll2_out", "video_pll1_out", };
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static const char * const imx8mq_csi1_phy_sels[] = {"osc_25m", "sys2_pll_125m", "sys2_pll_100m", "sys1_pll_800m",
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static const char * const imx8mq_csi1_phy_sels[] = {"osc_25m", "sys2_pll_333m", "sys2_pll_100m", "sys1_pll_800m",
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"sys2_pll_1000m", "clk_ext2", "audio_pll2_out", "video_pll1_out", };
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static const char * const imx8mq_csi1_esc_sels[] = {"osc_25m", "sys2_pll_100m", "sys1_pll_80m", "sys1_pll_800m",
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@@ -246,7 +246,7 @@ static const char * const imx8mq_csi1_esc_sels[] = {"osc_25m", "sys2_pll_100m",
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static const char * const imx8mq_csi2_core_sels[] = {"osc_25m", "sys1_pll_266m", "sys2_pll_250m", "sys1_pll_800m",
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"sys2_pll_1000m", "sys3_pll_out", "audio_pll2_out", "video_pll1_out", };
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static const char * const imx8mq_csi2_phy_sels[] = {"osc_25m", "sys2_pll_125m", "sys2_pll_100m", "sys1_pll_800m",
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static const char * const imx8mq_csi2_phy_sels[] = {"osc_25m", "sys2_pll_333m", "sys2_pll_100m", "sys1_pll_800m",
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"sys2_pll_1000m", "clk_ext2", "audio_pll2_out", "video_pll1_out", };
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static const char * const imx8mq_csi2_esc_sels[] = {"osc_25m", "sys2_pll_100m", "sys1_pll_80m", "sys1_pll_800m",
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@@ -151,7 +151,7 @@ static void imx_pll14xx_calc_settings(struct clk_pll14xx *pll, unsigned long rat
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/* First try if we can get the desired rate from one of the static entries */
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tt = imx_get_pll_settings(pll, rate);
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if (tt) {
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pr_debug("%s: in=%ld, want=%ld, Using PLL setting from table\n",
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pr_debug("%s: in=%lu, want=%lu, Using PLL setting from table\n",
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clk_hw_get_name(&pll->hw), prate, rate);
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t->rate = tt->rate;
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t->mdiv = tt->mdiv;
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@@ -173,7 +173,7 @@ static void imx_pll14xx_calc_settings(struct clk_pll14xx *pll, unsigned long rat
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if (rate >= rate_min && rate <= rate_max) {
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kdiv = pll1443x_calc_kdiv(mdiv, pdiv, sdiv, rate, prate);
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pr_debug("%s: in=%ld, want=%ld Only adjust kdiv %ld -> %d\n",
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pr_debug("%s: in=%lu, want=%lu Only adjust kdiv %ld -> %d\n",
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clk_hw_get_name(&pll->hw), prate, rate,
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FIELD_GET(KDIV_MASK, pll_div_ctl1), kdiv);
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fout = pll14xx_calc_rate(pll, mdiv, pdiv, sdiv, kdiv, prate);
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@@ -211,7 +211,7 @@ static void imx_pll14xx_calc_settings(struct clk_pll14xx *pll, unsigned long rat
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}
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}
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found:
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pr_debug("%s: in=%ld, want=%ld got=%d (pdiv=%d sdiv=%d mdiv=%d kdiv=%d)\n",
|
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pr_debug("%s: in=%lu, want=%lu got=%u (pdiv=%d sdiv=%d mdiv=%d kdiv=%d)\n",
|
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clk_hw_get_name(&pll->hw), prate, rate, t->rate, t->pdiv, t->sdiv,
|
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t->mdiv, t->kdiv);
|
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}
|
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|
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@@ -11,6 +11,13 @@
|
||||
|
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#include "clk.h"
|
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|
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/*
|
||||
* The VF610_CLK_END corresponds to ones defined in
|
||||
* include/dt-bindings/clock/vf610-clock.h
|
||||
* It shall be the value of the last defined clock +1
|
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*/
|
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#define VF610_CLK_END 196
|
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|
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#define CCM_CCR (ccm_base + 0x00)
|
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#define CCM_CSR (ccm_base + 0x04)
|
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#define CCM_CCSR (ccm_base + 0x08)
|
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@@ -313,6 +320,11 @@ static void __init vf610_clocks_init(struct device_node *ccm_node)
|
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clk[VF610_CLK_ENET_TS] = imx_clk_gate("enet_ts", "enet_ts_sel", CCM_CSCDR1, 23);
|
||||
clk[VF610_CLK_ENET0] = imx_clk_gate2("enet0", "ipg_bus", CCM_CCGR9, CCM_CCGRx_CGn(0));
|
||||
clk[VF610_CLK_ENET1] = imx_clk_gate2("enet1", "ipg_bus", CCM_CCGR9, CCM_CCGRx_CGn(1));
|
||||
clk[VF610_CLK_ESW] = imx_clk_gate2("esw", "ipg_bus", CCM_CCGR10, CCM_CCGRx_CGn(8));
|
||||
clk[VF610_CLK_ESW_MAC_TAB0] = imx_clk_gate2("esw_tab0", "ipg_bus", CCM_CCGR10, CCM_CCGRx_CGn(12));
|
||||
clk[VF610_CLK_ESW_MAC_TAB1] = imx_clk_gate2("esw_tab1", "ipg_bus", CCM_CCGR10, CCM_CCGRx_CGn(13));
|
||||
clk[VF610_CLK_ESW_MAC_TAB2] = imx_clk_gate2("esw_tab2", "ipg_bus", CCM_CCGR10, CCM_CCGRx_CGn(14));
|
||||
clk[VF610_CLK_ESW_MAC_TAB3] = imx_clk_gate2("esw_tab3", "ipg_bus", CCM_CCGR10, CCM_CCGRx_CGn(15));
|
||||
|
||||
clk[VF610_CLK_PIT] = imx_clk_gate2("pit", "ipg_bus", CCM_CCGR1, CCM_CCGRx_CGn(7));
|
||||
|
||||
|
||||
@@ -16,6 +16,13 @@ config CLK_PX30
|
||||
help
|
||||
Build the driver for PX30 Clock Driver.
|
||||
|
||||
config CLK_RV1103B
|
||||
bool "Rockchip RV1103B clock controller support"
|
||||
depends on ARM || COMPILE_TEST
|
||||
default y
|
||||
help
|
||||
Build the driver for RV1103B Clock Driver.
|
||||
|
||||
config CLK_RV110X
|
||||
bool "Rockchip RV110x clock controller support"
|
||||
depends on ARM || COMPILE_TEST
|
||||
|
||||
@@ -18,6 +18,7 @@ clk-rockchip-y += gate-link.o
|
||||
clk-rockchip-$(CONFIG_RESET_CONTROLLER) += softrst.o
|
||||
|
||||
obj-$(CONFIG_CLK_PX30) += clk-px30.o
|
||||
obj-$(CONFIG_CLK_RV1103B) += clk-rv1103b.o
|
||||
obj-$(CONFIG_CLK_RV110X) += clk-rv1108.o
|
||||
obj-$(CONFIG_CLK_RV1126) += clk-rv1126.o
|
||||
obj-$(CONFIG_CLK_RV1126B) += clk-rv1126b.o rst-rv1126b.o
|
||||
|
||||
@@ -827,6 +827,8 @@ static struct rockchip_clk_branch rk3568_clk_branches[] __initdata = {
|
||||
RK3568_CLKGATE_CON(12), 3, GFLAGS),
|
||||
GATE(CLK_PCIE20_AUX_NDFT, "clk_pcie20_aux_ndft", "xin24m", 0,
|
||||
RK3568_CLKGATE_CON(12), 4, GFLAGS),
|
||||
GATE(CLK_PCIE20_PIPE_DFT, "clk_pcie20_pipe_dft", "aclk_pipe", CLK_IGNORE_UNUSED,
|
||||
RK3568_CLKGATE_CON(12), 5, GFLAGS),
|
||||
GATE(ACLK_PCIE30X1_MST, "aclk_pcie30x1_mst", "aclk_pipe", 0,
|
||||
RK3568_CLKGATE_CON(12), 8, GFLAGS),
|
||||
GATE(ACLK_PCIE30X1_SLV, "aclk_pcie30x1_slv", "aclk_pipe", 0,
|
||||
@@ -837,6 +839,8 @@ static struct rockchip_clk_branch rk3568_clk_branches[] __initdata = {
|
||||
RK3568_CLKGATE_CON(12), 11, GFLAGS),
|
||||
GATE(CLK_PCIE30X1_AUX_NDFT, "clk_pcie30x1_aux_ndft", "xin24m", 0,
|
||||
RK3568_CLKGATE_CON(12), 12, GFLAGS),
|
||||
GATE(CLK_PCIE30X1_PIPE_DFT, "clk_pcie30x1_pipe_dft", "aclk_pipe", CLK_IGNORE_UNUSED,
|
||||
RK3568_CLKGATE_CON(12), 13, GFLAGS),
|
||||
GATE(ACLK_PCIE30X2_MST, "aclk_pcie30x2_mst", "aclk_pipe", 0,
|
||||
RK3568_CLKGATE_CON(13), 0, GFLAGS),
|
||||
GATE(ACLK_PCIE30X2_SLV, "aclk_pcie30x2_slv", "aclk_pipe", 0,
|
||||
@@ -847,6 +851,8 @@ static struct rockchip_clk_branch rk3568_clk_branches[] __initdata = {
|
||||
RK3568_CLKGATE_CON(13), 3, GFLAGS),
|
||||
GATE(CLK_PCIE30X2_AUX_NDFT, "clk_pcie30x2_aux_ndft", "xin24m", 0,
|
||||
RK3568_CLKGATE_CON(13), 4, GFLAGS),
|
||||
GATE(CLK_PCIE30X2_PIPE_DFT, "clk_pcie30x2_pipe_dft", "aclk_pipe", CLK_IGNORE_UNUSED,
|
||||
RK3568_CLKGATE_CON(13), 5, GFLAGS),
|
||||
GATE(ACLK_SATA0, "aclk_sata0", "aclk_pipe", 0,
|
||||
RK3568_CLKGATE_CON(11), 0, GFLAGS),
|
||||
GATE(CLK_SATA0_PMALIVE, "clk_sata0_pmalive", "gpll_20m", 0,
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -66,6 +66,55 @@ struct clk;
|
||||
#define PX30_PMU_CLKGATE_CON(x) ((x) * 0x4 + 0x80)
|
||||
#define PX30_PMU_MODE 0x0020
|
||||
|
||||
#define RV1103B_TOPCRU_BASE 0x60000
|
||||
#define RV1103B_PERICRU_BASE 0x0
|
||||
#define RV1103B_VICRU_BASE 0x30000
|
||||
#define RV1103B_NPUCRU_BASE 0x20000
|
||||
#define RV1103B_CORECRU_BASE 0x40000
|
||||
#define RV1103B_VEPUCRU_BASE 0x10000
|
||||
#define RV1103B_DDRCRU_BASE 0x50000
|
||||
#define RV1103B_SUBDDRCRU_BASE 0x58000
|
||||
#define RV1103B_PMUCRU_BASE 0x70000
|
||||
#define RV1103B_PMU1CRU_BASE 0x80000
|
||||
|
||||
#define RV1103B_PMUCLKSEL_CON(x) ((x) * 0x4 + 0x300 + RV1103B_PMUCRU_BASE)
|
||||
#define RV1103B_PMUCLKGATE_CON(x) ((x) * 0x4 + 0x800 + RV1103B_PMUCRU_BASE)
|
||||
#define RV1103B_PMUSOFTRST_CON(x) ((x) * 0x4 + 0xa00 + RV1103B_PMUCRU_BASE)
|
||||
#define RV1103B_PMU1CLKSEL_CON(x) ((x) * 0x4 + 0x300 + RV1103B_PMU1CRU_BASE)
|
||||
#define RV1103B_PMU1CLKGATE_CON(x) ((x) * 0x4 + 0x800 + RV1103B_PMU1CRU_BASE)
|
||||
#define RV1103B_PMU1SOFTRST_CON(x) ((x) * 0x4 + 0xa00 + RV1103B_PMU1CRU_BASE)
|
||||
#define RV1103B_PLL_CON(x) ((x) * 0x4 + RV1103B_TOPCRU_BASE)
|
||||
#define RV1103B_MODE_CON (0x280 + RV1103B_TOPCRU_BASE)
|
||||
#define RV1103B_CLKSEL_CON(x) ((x) * 0x4 + 0x300 + RV1103B_TOPCRU_BASE)
|
||||
#define RV1103B_CLKGATE_CON(x) ((x) * 0x4 + 0x800 + RV1103B_TOPCRU_BASE)
|
||||
#define RV1103B_SOFTRST_CON(x) ((x) * 0x4 + 0xa00 + RV1103B_TOPCRU_BASE)
|
||||
#define RV1103B_GLB_SRST_FST (0xc08 + RV1103B_TOPCRU_BASE)
|
||||
#define RV1103B_GLB_SRST_SND (0xc0c + RV1103B_TOPCRU_BASE)
|
||||
#define RV1103B_CLK_SAI_FRAC_DIV_HIGH (0xcc0 + RV1103B_TOPCRU_BASE)
|
||||
#define RV1103B_PERICLKSEL_CON(x) ((x) * 0x4 + 0x300 + RV1103B_PERICRU_BASE)
|
||||
#define RV1103B_PERICLKGATE_CON(x) ((x) * 0x4 + 0x800 + RV1103B_PERICRU_BASE)
|
||||
#define RV1103B_PERISOFTRST_CON(x) ((x) * 0x4 + 0xa00 + RV1103B_PERICRU_BASE)
|
||||
#define RV1103B_PERICRU_IP_CON (0xc08 + RV1103B_PERICRU_BASE)
|
||||
#define RV1103B_VICLKSEL_CON(x) ((x) * 0x4 + 0x300 + RV1103B_VICRU_BASE)
|
||||
#define RV1103B_VICLKGATE_CON(x) ((x) * 0x4 + 0x800 + RV1103B_VICRU_BASE)
|
||||
#define RV1103B_VISOFTRST_CON(x) ((x) * 0x4 + 0xa00 + RV1103B_VICRU_BASE)
|
||||
#define RV1103B_NPUCLKSEL_CON(x) ((x) * 0x4 + 0x300 + RV1103B_NPUCRU_BASE)
|
||||
#define RV1103B_NPUCLKGATE_CON(x) ((x) * 0x4 + 0x800 + RV1103B_NPUCRU_BASE)
|
||||
#define RV1103B_NPUSOFTRST_CON(x) ((x) * 0x4 + 0xa00 + RV1103B_NPUCRU_BASE)
|
||||
#define RV1103B_CORECLKSEL_CON(x) ((x) * 0x4 + 0x300 + RV1103B_CORECRU_BASE)
|
||||
#define RV1103B_CORECLKGATE_CON(x) ((x) * 0x4 + 0x800 + RV1103B_CORECRU_BASE)
|
||||
#define RV1103B_CORESOFTRST_CON(x) ((x) * 0x4 + 0xa00 + RV1103B_CORECRU_BASE)
|
||||
#define RV1103B_VEPUCLKSEL_CON(x) ((x) * 0x4 + 0x300 + RV1103B_VEPUCRU_BASE)
|
||||
#define RV1103B_VEPUCLKGATE_CON(x) ((x) * 0x4 + 0x800 + RV1103B_VEPUCRU_BASE)
|
||||
#define RV1103B_VEPUSOFTRST_CON(x) ((x) * 0x4 + 0xa00 + RV1103B_VEPUCRU_BASE)
|
||||
#define RV1103B_DDRCLKSEL_CON(x) ((x) * 0x4 + 0x300 + RV1103B_DDRCRU_BASE)
|
||||
#define RV1103B_DDRCLKGATE_CON(x) ((x) * 0x4 + 0x800 + RV1103B_DDRCRU_BASE)
|
||||
#define RV1103B_DDRSOFTRST_CON(x) ((x) * 0x4 + 0xa00 + RV1103B_DDRCRU_BASE)
|
||||
#define RV1103B_SUBDDRCLKSEL_CON(x) ((x) * 0x4 + 0x300 + RV1103B_SUBDDRCRU_BASE)
|
||||
#define RV1103B_SUBDDRCLKGATE_CON(x) ((x) * 0x4 + 0x800 + RV1103B_SUBDDRCRU_BASE)
|
||||
#define RV1103B_SUBDDRSOFTRST_CON(x) ((x) * 0x4 + 0xa00 + RV1103B_SUBDDRCRU_BASE)
|
||||
#define RV1103B_SUBDDRMODE_CON (0x280 + RV1103B_SUBDDRCRU_BASE)
|
||||
|
||||
#define RV1108_PLL_CON(x) ((x) * 0x4)
|
||||
#define RV1108_CLKSEL_CON(x) ((x) * 0x4 + 0x60)
|
||||
#define RV1108_CLKGATE_CON(x) ((x) * 0x4 + 0x120)
|
||||
|
||||
@@ -83,9 +83,22 @@ static SUNXI_CCU_MUX_DATA_WITH_GATE(r_pwmctrl_clk, "r-pwmctrl",
|
||||
static SUNXI_CCU_GATE_HW(bus_r_pwmctrl_clk, "bus-r-pwmctrl",
|
||||
&r_apb0_clk.common.hw, 0x13c, BIT(0), 0);
|
||||
|
||||
/* SPI clock is /M/N (same as new MMC?) */
|
||||
static const struct clk_parent_data r_spi_parents[] = {
|
||||
{ .fw_name = "hosc" },
|
||||
{ .fw_name = "pll-periph" },
|
||||
{ .name = "pll-periph0-300M" },
|
||||
{ .name = "pll-periph1-300M" },
|
||||
{ .name = "pll-audio" },
|
||||
};
|
||||
static SUNXI_CCU_DUALDIV_MUX_GATE(r_spi_clk, "r-spi", r_spi_parents, 0x150,
|
||||
0, 5, /* M */
|
||||
8, 5, /* P */
|
||||
24, 3, /* mux */
|
||||
BIT(31), /* gate */
|
||||
0);
|
||||
static SUNXI_CCU_GATE_HW(bus_r_spi_clk, "bus-r-spi",
|
||||
&r_ahb_clk.common.hw, 0x15c, BIT(0), 0);
|
||||
|
||||
static SUNXI_CCU_GATE_HW(bus_r_spinlock_clk, "bus-r-spinlock",
|
||||
&r_ahb_clk.common.hw, 0x16c, BIT(0), 0);
|
||||
static SUNXI_CCU_GATE_HW(bus_r_msgbox_clk, "bus-r-msgbox",
|
||||
@@ -138,6 +151,7 @@ static struct ccu_common *sun55i_a523_r_ccu_clks[] = {
|
||||
&bus_r_twd_clk.common,
|
||||
&r_pwmctrl_clk.common,
|
||||
&bus_r_pwmctrl_clk.common,
|
||||
&r_spi_clk.common,
|
||||
&bus_r_spi_clk.common,
|
||||
&bus_r_spinlock_clk.common,
|
||||
&bus_r_msgbox_clk.common,
|
||||
@@ -169,6 +183,7 @@ static struct clk_hw_onecell_data sun55i_a523_r_hw_clks = {
|
||||
[CLK_BUS_R_TWD] = &bus_r_twd_clk.common.hw,
|
||||
[CLK_R_PWMCTRL] = &r_pwmctrl_clk.common.hw,
|
||||
[CLK_BUS_R_PWMCTRL] = &bus_r_pwmctrl_clk.common.hw,
|
||||
[CLK_R_SPI] = &r_spi_clk.common.hw,
|
||||
[CLK_BUS_R_SPI] = &bus_r_spi_clk.common.hw,
|
||||
[CLK_BUS_R_SPINLOCK] = &bus_r_spinlock_clk.common.hw,
|
||||
[CLK_BUS_R_MSGBOX] = &bus_r_msgbox_clk.common.hw,
|
||||
|
||||
@@ -0,0 +1,14 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only
|
||||
|
||||
config TENSTORRENT_ATLANTIS_PRCM
|
||||
tristate "Support for Tenstorrent Atlantis PRCM Clock Controller"
|
||||
depends on ARCH_TENSTORRENT || COMPILE_TEST
|
||||
default ARCH_TENSTORRENT
|
||||
select REGMAP_MMIO
|
||||
select AUXILIARY_BUS
|
||||
select MFD_SYSCON
|
||||
help
|
||||
Say yes here to support the different clock
|
||||
controllers found in the Tenstorrent Atlantis SoC.
|
||||
This includes the clocks from the RCPU, HSIO, MMIO
|
||||
and PCIE domain.
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user