mirror of
https://github.com/linux-msm/laptops-kernel.git
synced 2026-08-13 14:19:53 -07:00
Merge branch 'for-next' of https://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl.git
This commit is contained in:
Mark Brown
@@ -20,6 +20,8 @@ properties:
|
||||
- items:
|
||||
- enum:
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||||
- apple,t6020-pinctrl
|
||||
- apple,t6030-pinctrl
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||||
- apple,t6031-pinctrl
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||||
- apple,t8122-pinctrl
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||||
- const: apple,t8103-pinctrl
|
||||
- items:
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||||
|
||||
@@ -356,6 +356,7 @@ patternProperties:
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||||
- I3C8
|
||||
- I3C9
|
||||
- JTAGM1
|
||||
- JTAGM1TRST
|
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- LPC0
|
||||
- LPC1
|
||||
- LTPI
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|
||||
@@ -0,0 +1,190 @@
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/pinctrl/mediatek,mt6858-pinctrl.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: MediaTek MT6858 Pin Controller
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||||
|
||||
maintainers:
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||||
- Nikolai Burov <nikolai.burov@jolla.com>
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||||
|
||||
description:
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The MediaTek's MT6858 Pin controller is used to control SoC pins.
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|
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properties:
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compatible:
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const: mediatek,mt6858-pinctrl
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reg:
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items:
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- description: gpio base
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- description: lm group IO
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- description: rb group IO
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- description: bm2 group IO
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- description: bm group IO
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- description: bm1 group IO
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- description: lt group IO
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- description: lt1 group IO
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||||
- description: rt group IO
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- description: rt1 group IO
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- description: eint south group IO
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- description: eint west group IO
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- description: eint east group IO
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||||
- description: eint center group IO
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reg-names:
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items:
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- const: base
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- const: lm
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- const: rb
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- const: bm2
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- const: bm
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- const: bm1
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- const: lt
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- const: lt1
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- const: rt
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- const: rt1
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- const: eint0
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- const: eint1
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- const: eint2
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- const: eint3
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||||
interrupts:
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maxItems: 1
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interrupt-controller: true
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'#interrupt-cells':
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const: 2
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gpio-controller: true
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'#gpio-cells':
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const: 2
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gpio-ranges:
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maxItems: 1
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||||
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gpio-line-names: true
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||||
# PIN CONFIGURATION NODES
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patternProperties:
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'-pins$':
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type: object
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additionalProperties: false
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patternProperties:
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||||
'^pins':
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type: object
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$ref: /schemas/pinctrl/pincfg-node.yaml
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additionalProperties: false
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description:
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A pinctrl node should contain at least one subnodes representing the
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pinctrl groups available on the machine. Each subnode will list the
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pins it needs, and how they should be configured, with regard to muxer
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configuration, pullups, drive strength, input enable/disable and input
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schmitt.
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properties:
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pinmux:
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description:
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Integer array, represents gpio pin number and mux setting.
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||||
Supported pin number and mux varies for different SoCs, and are
|
||||
defined as macros in arch/arm64/boot/dts/mediatek/mt6858-pinfunc.h
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for this SoC.
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||||
drive-strength:
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||||
enum: [2, 4, 6, 8, 10, 12, 14, 16]
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bias-pull-down:
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oneOf:
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- type: boolean
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||||
description: normal pull down.
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||||
- enum: [100, 101, 102, 103]
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||||
description: PUPD/R1/R0 pull down type. See MTK_PUPD_SET_R1R0_
|
||||
defines in dt-bindings/pinctrl/mt65xx.h.
|
||||
- enum: [200, 201, 202, 203]
|
||||
description: RSEL pull down type. See MTK_PULL_SET_RSEL_ defines
|
||||
in dt-bindings/pinctrl/mt65xx.h.
|
||||
|
||||
bias-pull-up:
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||||
oneOf:
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||||
- type: boolean
|
||||
description: normal pull up.
|
||||
- enum: [100, 101, 102, 103]
|
||||
description: PUPD/R1/R0 pull up type. See MTK_PUPD_SET_R1R0_
|
||||
defines in dt-bindings/pinctrl/mt65xx.h.
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||||
- enum: [200, 201, 202, 203]
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||||
description: RSEL pull up type. See MTK_PULL_SET_RSEL_ defines
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||||
in dt-bindings/pinctrl/mt65xx.h.
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bias-disable: true
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output-high: true
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output-low: true
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input-enable: true
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input-disable: true
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input-schmitt-enable: true
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||||
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||||
input-schmitt-disable: true
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||||
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||||
required:
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||||
- pinmux
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||||
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||||
required:
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||||
- compatible
|
||||
- reg
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||||
- interrupts
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||||
- interrupt-controller
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||||
- '#interrupt-cells'
|
||||
- gpio-controller
|
||||
- '#gpio-cells'
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||||
- gpio-ranges
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
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||||
- |
|
||||
#include <dt-bindings/pinctrl/mt65xx.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#define PINMUX_GPIO149__FUNC_SCL5 (MTK_PIN_NO(149) | 1)
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#define PINMUX_GPIO150__FUNC_SDA5 (MTK_PIN_NO(150) | 1)
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pio: pinctrl@10005000 {
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compatible = "mediatek,mt6858-pinctrl";
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reg = <0x10005000 0x1000>,
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||||
<0x11b20000 0x1000>,
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||||
<0x11c10000 0x1000>,
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||||
<0x11d10000 0x1000>,
|
||||
<0x11d30000 0x1000>,
|
||||
<0x11d40000 0x1000>,
|
||||
<0x11e20000 0x1000>,
|
||||
<0x11e30000 0x1000>,
|
||||
<0x11ed0000 0x1000>,
|
||||
<0x11ee0000 0x1000>,
|
||||
<0x11b00000 0x1000>,
|
||||
<0x11e60000 0x1000>,
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||||
<0x11e80000 0x1000>,
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||||
<0x1c01e000 0x1000>;
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||||
reg-names = "base", "lm", "rb", "bm2", "bm", "bm1", "lt", "lt1",
|
||||
"rt", "rt1", "eint0", "eint1", "eint2", "eint3";
|
||||
gpio-controller;
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#gpio-cells = <2>;
|
||||
gpio-ranges = <&pio 0 0 197>;
|
||||
interrupt-controller;
|
||||
interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
#interrupt-cells = <2>;
|
||||
|
||||
i2c5-pins {
|
||||
pins {
|
||||
pinmux = <PINMUX_GPIO149__FUNC_SCL5>,
|
||||
<PINMUX_GPIO150__FUNC_SDA5>;
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
};
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@@ -65,6 +65,11 @@ then:
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||||
- "#interrupt-cells"
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||||
|
||||
patternProperties:
|
||||
"-hog(-[0-9]+)?$":
|
||||
type: object
|
||||
required:
|
||||
- gpio-hog
|
||||
|
||||
'-pins(-[a-z]+)?$':
|
||||
type: object
|
||||
additionalProperties: false
|
||||
|
||||
@@ -1,5 +1,5 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
# Copyright 2022 NXP
|
||||
# Copyright 2022, 2026 NXP
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/pinctrl/nxp,s32g2-siul2-pinctrl.yaml#
|
||||
@@ -17,8 +17,10 @@ description: |
|
||||
SIUL2_0 @ 0x4009c000
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||||
SIUL2_1 @ 0x44010000
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||||
|
||||
Every SIUL2 region has multiple register types, and here only MSCR and
|
||||
IMCR registers need to be revealed for kernel to configure pinmux.
|
||||
Every SIUL2 region has multiple register types. MSCR and IMCR registers
|
||||
need to be revealed for kernel to configure pinmux. PGPDO and PGPDI
|
||||
registers are used for GPIO output/input operations. EIRQ registers
|
||||
are used for external interrupt configuration.
|
||||
|
||||
Please note that some register indexes are reserved in S32G2, such as
|
||||
MSCR102-MSCR111, MSCR123-MSCR143, IMCR84-IMCR118 and IMCR398-IMCR429.
|
||||
@@ -29,14 +31,22 @@ properties:
|
||||
- nxp,s32g2-siul2-pinctrl
|
||||
|
||||
reg:
|
||||
minItems: 6
|
||||
description: |
|
||||
A list of MSCR/IMCR register regions to be reserved.
|
||||
A list of MSCR/IMCR/PGPDO/PGPDI/EIRQ register regions to be reserved.
|
||||
- MSCR (Multiplexed Signal Configuration Register)
|
||||
An MSCR register can configure the associated pin as either a GPIO pin
|
||||
or a function output pin depends on the selected signal source.
|
||||
- IMCR (Input Multiplexed Signal Configuration Register)
|
||||
An IMCR register can configure the associated pin as function input
|
||||
pin depends on the selected signal source.
|
||||
- PGPDO (Parallel GPIO Pad Data Out Register)
|
||||
A PGPDO register is used to set the output value of a GPIO pin.
|
||||
- PGPDI (Parallel GPIO Pad Data In Register)
|
||||
A PGPDI register is used to read the input value of a GPIO pin.
|
||||
- EIRQ (External Interrupt Request)
|
||||
EIRQ registers are used to configure and manage external interrupts.
|
||||
|
||||
items:
|
||||
- description: MSCR registers group 0 in SIUL2_0
|
||||
- description: MSCR registers group 1 in SIUL2_1
|
||||
@@ -44,6 +54,28 @@ properties:
|
||||
- description: IMCR registers group 0 in SIUL2_0
|
||||
- description: IMCR registers group 1 in SIUL2_1
|
||||
- description: IMCR registers group 2 in SIUL2_1
|
||||
- description: PGPDO registers in SIUL2_0
|
||||
- description: PGPDI registers in SIUL2_0
|
||||
- description: PGPDO registers in SIUL2_1
|
||||
- description: PGPDI registers in SIUL2_1
|
||||
- description: EIRQ registers in SIUL2_1
|
||||
|
||||
gpio-controller: true
|
||||
|
||||
"#gpio-cells":
|
||||
const: 2
|
||||
|
||||
gpio-ranges:
|
||||
minItems: 1
|
||||
maxItems: 4
|
||||
|
||||
interrupt-controller: true
|
||||
|
||||
"#interrupt-cells":
|
||||
const: 2
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
patternProperties:
|
||||
'-pins$':
|
||||
@@ -86,11 +118,38 @@ required:
|
||||
- compatible
|
||||
- reg
|
||||
|
||||
oneOf:
|
||||
- description: Legacy pinctrl-only node
|
||||
properties:
|
||||
reg:
|
||||
maxItems: 6
|
||||
|
||||
gpio-controller: false
|
||||
"#gpio-cells": false
|
||||
gpio-ranges: false
|
||||
interrupt-controller: false
|
||||
"#interrupt-cells": false
|
||||
interrupts: false
|
||||
|
||||
- description: Pinctrl node with GPIO and external interrupt support
|
||||
required:
|
||||
- gpio-controller
|
||||
- "#gpio-cells"
|
||||
- gpio-ranges
|
||||
- interrupt-controller
|
||||
- "#interrupt-cells"
|
||||
- interrupts
|
||||
properties:
|
||||
reg:
|
||||
minItems: 11
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
pinctrl@4009c240 {
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
|
||||
pinctrl: pinctrl@4009c240 {
|
||||
compatible = "nxp,s32g2-siul2-pinctrl";
|
||||
|
||||
/* MSCR0-MSCR101 registers on siul2_0 */
|
||||
@@ -104,7 +163,26 @@ examples:
|
||||
/* IMCR119-IMCR397 registers on siul2_1 */
|
||||
<0x44010c1c 0x45c>,
|
||||
/* IMCR430-IMCR495 registers on siul2_1 */
|
||||
<0x440110f8 0x108>;
|
||||
<0x440110f8 0x108>,
|
||||
/* PGPDO registers on siul2_0 */
|
||||
<0x4009d700 0x10>,
|
||||
/* PGPDI registers on siul2_0 */
|
||||
<0x4009d740 0x10>,
|
||||
/* PGPDO registers on siul2_1 */
|
||||
<0x44011700 0x18>,
|
||||
/* PGPDI registers on siul2_1 */
|
||||
<0x44011740 0x18>,
|
||||
/* EIRQ registers on siul2_1 */
|
||||
<0x44010010 0x34>;
|
||||
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
gpio-ranges = <&pinctrl 0 0 102>,
|
||||
<&pinctrl 112 112 79>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
||||
llce-can0-pins {
|
||||
llce-can0-grp0 {
|
||||
|
||||
@@ -1175,7 +1175,7 @@ Possible standard state names are: "default", "init", "sleep" and "idle".
|
||||
selected after the driver probe.
|
||||
|
||||
- the ``sleep`` and ``idle`` states are for power management and can only
|
||||
be selected with the PM API bellow.
|
||||
be selected with the PM API below.
|
||||
|
||||
PM interfaces
|
||||
=================
|
||||
|
||||
@@ -22500,6 +22500,13 @@ L: linux-arm-msm@vger.kernel.org
|
||||
S: Maintained
|
||||
F: drivers/firmware/qcom/qcom_qseecom_uefisecapp.c
|
||||
|
||||
QUALCOMM PINCTRL DRIVERS
|
||||
M: Bartosz Golaszewski <brgl@kernel.org>
|
||||
L: linux-arm-msm@vger.kernel.org
|
||||
S: Supported
|
||||
F: Documentation/devicetree/bindings/pinctrl/qcom,*.yaml
|
||||
F: drivers/pinctrl/qcom/
|
||||
|
||||
QUALCOMM RMNET DRIVER
|
||||
M: Subash Abhinov Kasiviswanathan <subash.a.kasiviswanathan@oss.qualcomm.com>
|
||||
M: Sean Tranchetti <sean.tranchetti@oss.qualcomm.com>
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -4,17 +4,18 @@
|
||||
*
|
||||
* Copyright (C) 2008 - 2010 Paul Mundt
|
||||
*/
|
||||
#include <linux/err.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/types.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/smsc911x.h>
|
||||
#include <linux/input.h>
|
||||
#include <linux/gpio.h>
|
||||
#include <linux/gpio_keys.h>
|
||||
#include <linux/leds.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/gpio/machine.h>
|
||||
#include <linux/gpio/property.h>
|
||||
#include <asm/machvec.h>
|
||||
#include <asm/io.h>
|
||||
#include <cpu/pfc.h>
|
||||
#include <cpu/sh7203.h>
|
||||
|
||||
static struct smsc911x_platform_config smsc911x_config = {
|
||||
@@ -37,101 +38,236 @@ static struct resource smsc911x_resources[] = {
|
||||
},
|
||||
};
|
||||
|
||||
static struct platform_device smsc911x_device = {
|
||||
.name = "smsc911x",
|
||||
.id = -1,
|
||||
.num_resources = ARRAY_SIZE(smsc911x_resources),
|
||||
.resource = smsc911x_resources,
|
||||
.dev = {
|
||||
.platform_data = &smsc911x_config,
|
||||
static const struct software_node rsk7203_gpio_leds_node = {
|
||||
.name = "rsk7203-gpio-leds",
|
||||
};
|
||||
|
||||
static const struct software_node rsk7203_green_led_node = {
|
||||
.name = "green",
|
||||
.parent = &rsk7203_gpio_leds_node,
|
||||
.properties = (const struct property_entry[]) {
|
||||
PROPERTY_ENTRY_STRING("label", "green"),
|
||||
PROPERTY_ENTRY_GPIO("gpios", &pfc_gpiochip_node,
|
||||
GPIO_PE10, GPIO_ACTIVE_LOW),
|
||||
{ }
|
||||
},
|
||||
};
|
||||
|
||||
static struct gpio_led rsk7203_gpio_leds[] = {
|
||||
static const struct software_node rsk7203_orange_led_node = {
|
||||
.name = "orange",
|
||||
.parent = &rsk7203_gpio_leds_node,
|
||||
.properties = (const struct property_entry[]) {
|
||||
PROPERTY_ENTRY_STRING("label", "orange"),
|
||||
PROPERTY_ENTRY_STRING("linux,default-trigger", "nand-disk"),
|
||||
PROPERTY_ENTRY_GPIO("gpios", &pfc_gpiochip_node,
|
||||
GPIO_PE12, GPIO_ACTIVE_LOW),
|
||||
{ }
|
||||
},
|
||||
};
|
||||
|
||||
static const struct software_node rsk7203_red1_led_node = {
|
||||
.name = "red:timer",
|
||||
.parent = &rsk7203_gpio_leds_node,
|
||||
.properties = (const struct property_entry[]) {
|
||||
PROPERTY_ENTRY_STRING("label", "red:timer"),
|
||||
PROPERTY_ENTRY_STRING("linux,default-trigger", "timer"),
|
||||
PROPERTY_ENTRY_GPIO("gpios", &pfc_gpiochip_node,
|
||||
GPIO_PC14, GPIO_ACTIVE_LOW),
|
||||
{ }
|
||||
},
|
||||
};
|
||||
|
||||
static const struct software_node rsk7203_red2_led_node = {
|
||||
.name = "red:heartbeat",
|
||||
.parent = &rsk7203_gpio_leds_node,
|
||||
.properties = (const struct property_entry[]) {
|
||||
PROPERTY_ENTRY_STRING("label", "red:heartbeat"),
|
||||
PROPERTY_ENTRY_STRING("linux,default-trigger", "heartbeat"),
|
||||
PROPERTY_ENTRY_GPIO("gpios", &pfc_gpiochip_node,
|
||||
GPIO_PE11, GPIO_ACTIVE_LOW),
|
||||
{ }
|
||||
},
|
||||
};
|
||||
|
||||
static const struct software_node rsk7203_gpio_keys_node = {
|
||||
.name = "rsk7203-gpio-keys",
|
||||
.properties = (const struct property_entry[]) {
|
||||
PROPERTY_ENTRY_U32("poll-interval", 50),
|
||||
{ }
|
||||
},
|
||||
};
|
||||
|
||||
static const struct software_node rsk7203_sw1_key_node = {
|
||||
.parent = &rsk7203_gpio_keys_node,
|
||||
.properties = (const struct property_entry[]) {
|
||||
PROPERTY_ENTRY_U32("linux,code", BTN_0),
|
||||
PROPERTY_ENTRY_GPIO("gpios", &pfc_gpiochip_node,
|
||||
GPIO_PB0, GPIO_ACTIVE_LOW),
|
||||
PROPERTY_ENTRY_STRING("label", "SW1"),
|
||||
{ }
|
||||
},
|
||||
};
|
||||
|
||||
static const struct software_node rsk7203_sw2_key_node = {
|
||||
.parent = &rsk7203_gpio_keys_node,
|
||||
.properties = (const struct property_entry[]) {
|
||||
PROPERTY_ENTRY_U32("linux,code", BTN_1),
|
||||
PROPERTY_ENTRY_GPIO("gpios", &pfc_gpiochip_node,
|
||||
GPIO_PB1, GPIO_ACTIVE_LOW),
|
||||
PROPERTY_ENTRY_STRING("label", "SW2"),
|
||||
{ }
|
||||
},
|
||||
};
|
||||
|
||||
static const struct software_node rsk7203_sw3_key_node = {
|
||||
.parent = &rsk7203_gpio_keys_node,
|
||||
.properties = (const struct property_entry[]) {
|
||||
PROPERTY_ENTRY_U32("linux,code", BTN_2),
|
||||
PROPERTY_ENTRY_GPIO("gpios", &pfc_gpiochip_node,
|
||||
GPIO_PB2, GPIO_ACTIVE_LOW),
|
||||
PROPERTY_ENTRY_STRING("label", "SW3"),
|
||||
{ }
|
||||
},
|
||||
};
|
||||
|
||||
/* The base of the function GPIOs in the flat enum */
|
||||
#define SH7203_FN_BASE GPIO_FN_PINT7_PB
|
||||
|
||||
static const struct software_node rsk7203_pfc_functions_node = {
|
||||
.name = "functions",
|
||||
.parent = &pfc_gpiochip_node,
|
||||
};
|
||||
|
||||
static const struct software_node rsk7203_txd0_hog_node = {
|
||||
.name = "txd0-hog",
|
||||
.parent = &rsk7203_pfc_functions_node,
|
||||
.properties = (const struct property_entry[]) {
|
||||
PROPERTY_ENTRY_BOOL("gpio-hog"),
|
||||
PROPERTY_ENTRY_U32_ARRAY("gpios", ((u32[]){
|
||||
GPIO_FN_TXD0 - SH7203_FN_BASE, GPIO_ACTIVE_HIGH
|
||||
})),
|
||||
PROPERTY_ENTRY_BOOL("input"),
|
||||
PROPERTY_ENTRY_STRING("line-name", "TXD0"),
|
||||
{ }
|
||||
},
|
||||
};
|
||||
|
||||
static const struct software_node rsk7203_rxd0_hog_node = {
|
||||
.name = "rxd0-hog",
|
||||
.parent = &rsk7203_pfc_functions_node,
|
||||
.properties = (const struct property_entry[]) {
|
||||
PROPERTY_ENTRY_BOOL("gpio-hog"),
|
||||
PROPERTY_ENTRY_U32_ARRAY("gpios", ((u32[]){
|
||||
GPIO_FN_RXD0 - SH7203_FN_BASE, GPIO_ACTIVE_HIGH
|
||||
})),
|
||||
PROPERTY_ENTRY_BOOL("input"),
|
||||
PROPERTY_ENTRY_STRING("line-name", "RXD0"),
|
||||
{ }
|
||||
},
|
||||
};
|
||||
|
||||
static const struct software_node rsk7203_irq0_hog_node = {
|
||||
.name = "irq0-hog",
|
||||
.parent = &rsk7203_pfc_functions_node,
|
||||
.properties = (const struct property_entry[]) {
|
||||
PROPERTY_ENTRY_BOOL("gpio-hog"),
|
||||
PROPERTY_ENTRY_U32_ARRAY("gpios", ((u32[]){
|
||||
GPIO_FN_IRQ0_PB - SH7203_FN_BASE, GPIO_ACTIVE_HIGH
|
||||
})),
|
||||
PROPERTY_ENTRY_BOOL("input"),
|
||||
PROPERTY_ENTRY_STRING("line-name", "IRQ0_PB"),
|
||||
{ }
|
||||
},
|
||||
};
|
||||
|
||||
static const struct software_node * const rsk7203_swnodes[] __initconst = {
|
||||
&rsk7203_gpio_leds_node,
|
||||
&rsk7203_green_led_node,
|
||||
&rsk7203_orange_led_node,
|
||||
&rsk7203_red1_led_node,
|
||||
&rsk7203_red2_led_node,
|
||||
&rsk7203_gpio_keys_node,
|
||||
&rsk7203_sw1_key_node,
|
||||
&rsk7203_sw2_key_node,
|
||||
&rsk7203_sw3_key_node,
|
||||
&rsk7203_pfc_functions_node,
|
||||
&rsk7203_txd0_hog_node,
|
||||
&rsk7203_rxd0_hog_node,
|
||||
&rsk7203_irq0_hog_node,
|
||||
NULL
|
||||
};
|
||||
|
||||
static const struct platform_device_info rsk7203_devices[] __initconst = {
|
||||
{
|
||||
.name = "green",
|
||||
.gpio = GPIO_PE10,
|
||||
.active_low = 1,
|
||||
}, {
|
||||
.name = "orange",
|
||||
.default_trigger = "nand-disk",
|
||||
.gpio = GPIO_PE12,
|
||||
.active_low = 1,
|
||||
}, {
|
||||
.name = "red:timer",
|
||||
.default_trigger = "timer",
|
||||
.gpio = GPIO_PC14,
|
||||
.active_low = 1,
|
||||
}, {
|
||||
.name = "red:heartbeat",
|
||||
.default_trigger = "heartbeat",
|
||||
.gpio = GPIO_PE11,
|
||||
.active_low = 1,
|
||||
.name = "smsc911x",
|
||||
.id = PLATFORM_DEVID_NONE,
|
||||
.res = smsc911x_resources,
|
||||
.num_res = ARRAY_SIZE(smsc911x_resources),
|
||||
.data = &smsc911x_config,
|
||||
.size_data = sizeof(smsc911x_config),
|
||||
},
|
||||
};
|
||||
|
||||
static struct gpio_led_platform_data rsk7203_gpio_leds_info = {
|
||||
.leds = rsk7203_gpio_leds,
|
||||
.num_leds = ARRAY_SIZE(rsk7203_gpio_leds),
|
||||
};
|
||||
|
||||
static struct platform_device led_device = {
|
||||
.name = "leds-gpio",
|
||||
.id = -1,
|
||||
.dev = {
|
||||
.platform_data = &rsk7203_gpio_leds_info,
|
||||
},
|
||||
};
|
||||
|
||||
static struct gpio_keys_button rsk7203_gpio_keys_table[] = {
|
||||
{
|
||||
.code = BTN_0,
|
||||
.gpio = GPIO_PB0,
|
||||
.active_low = 1,
|
||||
.desc = "SW1",
|
||||
}, {
|
||||
.code = BTN_1,
|
||||
.gpio = GPIO_PB1,
|
||||
.active_low = 1,
|
||||
.desc = "SW2",
|
||||
}, {
|
||||
.code = BTN_2,
|
||||
.gpio = GPIO_PB2,
|
||||
.active_low = 1,
|
||||
.desc = "SW3",
|
||||
.name = "leds-gpio",
|
||||
.id = PLATFORM_DEVID_NONE,
|
||||
.swnode = &rsk7203_gpio_leds_node,
|
||||
},
|
||||
{
|
||||
.name = "gpio-keys-polled",
|
||||
.id = PLATFORM_DEVID_NONE,
|
||||
.swnode = &rsk7203_gpio_keys_node,
|
||||
},
|
||||
};
|
||||
|
||||
static struct gpio_keys_platform_data rsk7203_gpio_keys_info = {
|
||||
.buttons = rsk7203_gpio_keys_table,
|
||||
.nbuttons = ARRAY_SIZE(rsk7203_gpio_keys_table),
|
||||
.poll_interval = 50, /* default to 50ms */
|
||||
};
|
||||
/*
|
||||
* The pfc-sh7203 device is registered at arch_initcall level, and the
|
||||
* sh-pfc driver (registered at postcore_initcall level) probes as soon
|
||||
* as the device is created.
|
||||
*
|
||||
* We need to register our software nodes at postcore_initcall level so
|
||||
* they are already present in the system when the driver probes and
|
||||
* tries to apply GPIO hogs.
|
||||
*/
|
||||
static int __init rsk7203_sw_nodes_setup(void)
|
||||
{
|
||||
int error;
|
||||
|
||||
static struct platform_device keys_device = {
|
||||
.name = "gpio-keys-polled",
|
||||
.dev = {
|
||||
.platform_data = &rsk7203_gpio_keys_info,
|
||||
},
|
||||
};
|
||||
error = software_node_register(&pfc_gpiochip_node);
|
||||
if (error && error != -EEXIST) {
|
||||
pr_err("RSK7203: failed to register PFC software node: %d\n",
|
||||
error);
|
||||
return error;
|
||||
}
|
||||
|
||||
static struct platform_device *rsk7203_devices[] __initdata = {
|
||||
&smsc911x_device,
|
||||
&led_device,
|
||||
&keys_device,
|
||||
};
|
||||
error = software_node_register_node_group(rsk7203_swnodes);
|
||||
if (error) {
|
||||
pr_err("RSK7203: failed to register board software nodes: %d\n",
|
||||
error);
|
||||
return error;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
postcore_initcall(rsk7203_sw_nodes_setup);
|
||||
|
||||
static int __init rsk7203_devices_setup(void)
|
||||
{
|
||||
/* Select pins for SCIF0 */
|
||||
gpio_request(GPIO_FN_TXD0, NULL);
|
||||
gpio_request(GPIO_FN_RXD0, NULL);
|
||||
struct platform_device *pd;
|
||||
int error;
|
||||
int i;
|
||||
|
||||
/* Setup LAN9118: CS1 in 16-bit Big Endian Mode, IRQ0 at Port B */
|
||||
__raw_writel(0x36db0400, 0xfffc0008); /* CS1BCR */
|
||||
gpio_request(GPIO_FN_IRQ0_PB, NULL);
|
||||
|
||||
return platform_add_devices(rsk7203_devices,
|
||||
ARRAY_SIZE(rsk7203_devices));
|
||||
for (i = 0; i < ARRAY_SIZE(rsk7203_devices); i++) {
|
||||
pd = platform_device_register_full(&rsk7203_devices[i]);
|
||||
error = PTR_ERR_OR_ZERO(pd);
|
||||
if (error) {
|
||||
pr_err("failed to create platform device %s: %d\n",
|
||||
rsk7203_devices[i].name, error);
|
||||
return error;
|
||||
}
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
device_initcall(rsk7203_devices_setup);
|
||||
|
||||
@@ -11,6 +11,9 @@
|
||||
#include <linux/types.h>
|
||||
|
||||
struct resource;
|
||||
struct software_node;
|
||||
|
||||
extern const struct software_node pfc_gpiochip_node;
|
||||
|
||||
int sh_pfc_register(const char *name,
|
||||
struct resource *resource, u32 num_resources);
|
||||
|
||||
@@ -5,21 +5,29 @@
|
||||
* Copyright (C) 2012 Renesas Solutions Corp.
|
||||
*/
|
||||
|
||||
#include <linux/err.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/property.h>
|
||||
|
||||
#include <cpu/pfc.h>
|
||||
|
||||
static struct platform_device sh_pfc_device = {
|
||||
.id = -1,
|
||||
const struct software_node pfc_gpiochip_node = {
|
||||
.name = "sh-pfc",
|
||||
};
|
||||
|
||||
int __init sh_pfc_register(const char *name,
|
||||
struct resource *resource, u32 num_resources)
|
||||
{
|
||||
sh_pfc_device.name = name;
|
||||
sh_pfc_device.num_resources = num_resources;
|
||||
sh_pfc_device.resource = resource;
|
||||
struct platform_device_info pdev_info = {
|
||||
.name = name,
|
||||
.id = PLATFORM_DEVID_NONE,
|
||||
.res = resource,
|
||||
.num_res = num_resources,
|
||||
.swnode = &pfc_gpiochip_node,
|
||||
};
|
||||
struct platform_device *pdev;
|
||||
|
||||
return platform_device_register(&sh_pfc_device);
|
||||
pdev = platform_device_register_full(&pdev_info);
|
||||
return PTR_ERR_OR_ZERO(pdev);
|
||||
}
|
||||
|
||||
@@ -488,6 +488,7 @@ config PINCTRL_PIC32
|
||||
depends on MACH_PIC32 || COMPILE_TEST
|
||||
select PINMUX
|
||||
select GENERIC_PINCONF
|
||||
select GPIOLIB
|
||||
select GPIOLIB_IRQCHIP
|
||||
help
|
||||
This is the pin controller and gpio driver for Microchip PIC32
|
||||
@@ -564,6 +565,7 @@ config PINCTRL_STMFX
|
||||
depends on I2C
|
||||
depends on HAS_IOMEM
|
||||
select GENERIC_PINCONF
|
||||
select GPIOLIB
|
||||
select GPIOLIB_IRQCHIP
|
||||
select MFD_STMFX
|
||||
help
|
||||
|
||||
@@ -2519,10 +2519,8 @@ static int airoha_pinctrl_add_gpiochip(struct airoha_pinctrl *pinctrl,
|
||||
|
||||
err = devm_request_irq(dev, irq, airoha_irq_handler, IRQF_SHARED,
|
||||
dev_name(dev), pinctrl);
|
||||
if (err) {
|
||||
dev_err(dev, "error requesting irq %d: %d\n", irq, err);
|
||||
if (err)
|
||||
return err;
|
||||
}
|
||||
|
||||
return devm_gpiochip_add_data(dev, gc, pinctrl);
|
||||
}
|
||||
|
||||
@@ -1018,7 +1018,8 @@ PIN_GROUP(I3C6, AA22, AB20);
|
||||
PIN_GROUP(I3C7, AF18, AE19);
|
||||
PIN_GROUP(I3C8, AD20, AC20);
|
||||
PIN_GROUP(I3C9, AA21, AB21);
|
||||
PIN_GROUP(JTAGM1, D12, F10, E11, F11, F13);
|
||||
PIN_GROUP(JTAGM1, F10, E11, F11, F13);
|
||||
PIN_GROUP(JTAGM1TRST, D12);
|
||||
PIN_GROUP(LPC0, AF26, AF25, B16, D14, B15, B14, C17, B13, E14, C15);
|
||||
PIN_GROUP(LPC1, C16, C14, C11, D9, F14, D10, C12, C13, AE16, AE17);
|
||||
PIN_GROUP(LTPI, U25, U26, Y26, AA24);
|
||||
@@ -1263,6 +1264,7 @@ static const struct pingroup aspeed_g7_soc1_groups[] = {
|
||||
GROUP(I3C8),
|
||||
GROUP(I3C9),
|
||||
GROUP(JTAGM1),
|
||||
GROUP(JTAGM1TRST),
|
||||
GROUP(LPC0),
|
||||
GROUP(LPC1),
|
||||
GROUP(LTPI),
|
||||
@@ -1528,7 +1530,7 @@ static const struct aspeed_g7_soc1_function aspeed_g7_soc1_functions[] = {
|
||||
FUNC(I3C7, (1), "I3C7"),
|
||||
FUNC(I3C8, (1), "I3C8"),
|
||||
FUNC(I3C9, (1), "I3C9"),
|
||||
FUNC(JTAGM1, (1), "JTAGM1"),
|
||||
FUNC(JTAGM1, (1, 1), "JTAGM1", "JTAGM1TRST"),
|
||||
FUNC(LPC0, (2), "LPC0"),
|
||||
FUNC(LPC1, (2), "LPC1"),
|
||||
FUNC(LTPI, (2), "LTPI"),
|
||||
|
||||
@@ -121,6 +121,7 @@ source "drivers/pinctrl/bcm/Kconfig.stb"
|
||||
config PINCTRL_IPROC_GPIO
|
||||
bool "Broadcom iProc GPIO (with PINCONF) driver"
|
||||
depends on ARCH_BCM_IPROC || COMPILE_TEST
|
||||
select GPIOLIB
|
||||
select GPIOLIB_IRQCHIP
|
||||
select PINCONF
|
||||
select GENERIC_PINCONF
|
||||
@@ -186,6 +187,7 @@ config PINCTRL_NS
|
||||
config PINCTRL_NSP_GPIO
|
||||
bool "Broadcom NSP GPIO (with PINCONF) driver"
|
||||
depends on ARCH_BCM_NSP || COMPILE_TEST
|
||||
select GPIOLIB
|
||||
select GPIOLIB_IRQCHIP
|
||||
select PINCONF
|
||||
select GENERIC_PINCONF
|
||||
|
||||
@@ -1350,7 +1350,6 @@ static int bcm2835_pinctrl_probe(struct platform_device *pdev)
|
||||
pc->pctl_desc = *pdata->pctl_desc;
|
||||
pc->pctl_dev = devm_pinctrl_register(dev, &pc->pctl_desc, pc);
|
||||
if (IS_ERR(pc->pctl_dev)) {
|
||||
gpiochip_remove(&pc->gpio_chip);
|
||||
return PTR_ERR(pc->pctl_dev);
|
||||
}
|
||||
|
||||
|
||||
@@ -671,11 +671,8 @@ static int nsp_gpio_probe(struct platform_device *pdev)
|
||||
/* Install ISR for this GPIO controller. */
|
||||
ret = devm_request_irq(dev, irq, nsp_gpio_irq_handler,
|
||||
IRQF_SHARED, "gpio-a", &chip->gc);
|
||||
if (ret) {
|
||||
dev_err(&pdev->dev, "Unable to request IRQ%d: %d\n",
|
||||
irq, ret);
|
||||
if (ret)
|
||||
return ret;
|
||||
}
|
||||
|
||||
girq = &chip->gc.irq;
|
||||
gpio_irq_chip_set_chip(girq, &nsp_gpio_irq_chip);
|
||||
|
||||
@@ -547,14 +547,11 @@ static int imx1_pinctrl_parse_functions(struct device_node *np,
|
||||
*/
|
||||
static bool imx1_pinctrl_dt_is_flat_functions(struct device_node *np)
|
||||
{
|
||||
struct device_node *function_np;
|
||||
struct device_node *pinctrl_np;
|
||||
|
||||
for_each_child_of_node(np, function_np) {
|
||||
for_each_child_of_node_scoped(np, function_np) {
|
||||
if (of_property_present(function_np, "fsl,pins"))
|
||||
return true;
|
||||
|
||||
for_each_child_of_node(function_np, pinctrl_np) {
|
||||
for_each_child_of_node_scoped(function_np, pinctrl_np) {
|
||||
if (of_property_present(pinctrl_np, "fsl,pins"))
|
||||
return false;
|
||||
}
|
||||
|
||||
@@ -11,7 +11,7 @@ config EINT_MTK
|
||||
default PINCTRL_MTK_PARIS
|
||||
|
||||
config PINCTRL_MTK
|
||||
bool
|
||||
tristate
|
||||
depends on OF
|
||||
select PINMUX
|
||||
select GENERIC_PINCONF
|
||||
@@ -22,13 +22,13 @@ config PINCTRL_MTK_V2
|
||||
tristate
|
||||
|
||||
config PINCTRL_MTK_MTMIPS
|
||||
bool
|
||||
tristate
|
||||
depends on RALINK
|
||||
select PINMUX
|
||||
select GENERIC_PINCONF
|
||||
|
||||
config PINCTRL_MTK_MOORE
|
||||
bool
|
||||
tristate
|
||||
depends on OF
|
||||
select GENERIC_PINCONF
|
||||
select GENERIC_PINCTRL_GROUPS
|
||||
@@ -48,42 +48,42 @@ config PINCTRL_MTK_PARIS
|
||||
|
||||
# For MIPS SoCs
|
||||
config PINCTRL_MT7620
|
||||
bool "MediaTek MT7620 pin control"
|
||||
tristate "MediaTek MT7620 pin control"
|
||||
depends on SOC_MT7620 || COMPILE_TEST
|
||||
depends on RALINK
|
||||
default SOC_MT7620
|
||||
select PINCTRL_MTK_MTMIPS
|
||||
|
||||
config PINCTRL_MT7621
|
||||
bool "MediaTek MT7621 pin control"
|
||||
tristate "MediaTek MT7621 pin control"
|
||||
depends on SOC_MT7621 || COMPILE_TEST
|
||||
depends on RALINK
|
||||
default SOC_MT7621
|
||||
select PINCTRL_MTK_MTMIPS
|
||||
|
||||
config PINCTRL_MT76X8
|
||||
bool "MediaTek MT76X8 pin control"
|
||||
tristate "MediaTek MT76X8 pin control"
|
||||
depends on SOC_MT7620 || COMPILE_TEST
|
||||
depends on RALINK
|
||||
default SOC_MT7620
|
||||
select PINCTRL_MTK_MTMIPS
|
||||
|
||||
config PINCTRL_RT2880
|
||||
bool "Ralink RT2880 pin control"
|
||||
tristate "Ralink RT2880 pin control"
|
||||
depends on SOC_RT288X || COMPILE_TEST
|
||||
depends on RALINK
|
||||
default SOC_RT288X
|
||||
select PINCTRL_MTK_MTMIPS
|
||||
|
||||
config PINCTRL_RT305X
|
||||
bool "Ralink RT305X pin control"
|
||||
tristate "Ralink RT305X pin control"
|
||||
depends on SOC_RT305X || COMPILE_TEST
|
||||
depends on RALINK
|
||||
default SOC_RT305X
|
||||
select PINCTRL_MTK_MTMIPS
|
||||
|
||||
config PINCTRL_RT3883
|
||||
bool "Ralink RT3883 pin control"
|
||||
tristate "Ralink RT3883 pin control"
|
||||
depends on SOC_RT3883 || COMPILE_TEST
|
||||
depends on RALINK
|
||||
default SOC_RT3883
|
||||
@@ -91,35 +91,35 @@ config PINCTRL_RT3883
|
||||
|
||||
# For ARMv7 SoCs
|
||||
config PINCTRL_MT2701
|
||||
bool "MediaTek MT2701 pin control"
|
||||
tristate "MediaTek MT2701 pin control"
|
||||
depends on MACH_MT7623 || MACH_MT2701 || COMPILE_TEST
|
||||
depends on OF
|
||||
default MACH_MT2701
|
||||
select PINCTRL_MTK
|
||||
|
||||
config PINCTRL_MT7623
|
||||
bool "MediaTek MT7623 pin control with generic binding"
|
||||
tristate "MediaTek MT7623 pin control with generic binding"
|
||||
depends on MACH_MT7623 || COMPILE_TEST
|
||||
depends on OF
|
||||
default MACH_MT7623
|
||||
select PINCTRL_MTK_MOORE
|
||||
|
||||
config PINCTRL_MT7629
|
||||
bool "MediaTek MT7629 pin control"
|
||||
tristate "MediaTek MT7629 pin control"
|
||||
depends on MACH_MT7629 || COMPILE_TEST
|
||||
depends on OF
|
||||
default MACH_MT7629
|
||||
select PINCTRL_MTK_MOORE
|
||||
|
||||
config PINCTRL_MT8135
|
||||
bool "MediaTek MT8135 pin control"
|
||||
tristate "MediaTek MT8135 pin control"
|
||||
depends on MACH_MT8135 || COMPILE_TEST
|
||||
depends on OF
|
||||
default MACH_MT8135
|
||||
select PINCTRL_MTK
|
||||
|
||||
config PINCTRL_MT8127
|
||||
bool "MediaTek MT8127 pin control"
|
||||
tristate "MediaTek MT8127 pin control"
|
||||
depends on MACH_MT8127 || COMPILE_TEST
|
||||
depends on OF
|
||||
default MACH_MT8127
|
||||
@@ -127,7 +127,7 @@ config PINCTRL_MT8127
|
||||
|
||||
# For ARMv8 SoCs
|
||||
config PINCTRL_MT2712
|
||||
bool "MediaTek MT2712 pin control"
|
||||
tristate "MediaTek MT2712 pin control"
|
||||
depends on OF
|
||||
depends on ARM64 || COMPILE_TEST
|
||||
default ARM64 && ARCH_MEDIATEK
|
||||
@@ -153,21 +153,31 @@ config PINCTRL_MT6779
|
||||
map specific eint which doesn't have real gpio pin.
|
||||
|
||||
config PINCTRL_MT6795
|
||||
bool "MediaTek MT6795 pin control"
|
||||
tristate "MediaTek MT6795 pin control"
|
||||
depends on OF
|
||||
depends on ARM64 || COMPILE_TEST
|
||||
default ARM64 && ARCH_MEDIATEK
|
||||
select PINCTRL_MTK_PARIS
|
||||
|
||||
config PINCTRL_MT6797
|
||||
bool "MediaTek MT6797 pin control"
|
||||
tristate "MediaTek MT6797 pin control"
|
||||
depends on OF
|
||||
depends on ARM64 || COMPILE_TEST
|
||||
default ARM64 && ARCH_MEDIATEK
|
||||
select PINCTRL_MTK_PARIS
|
||||
|
||||
config PINCTRL_MT6858
|
||||
tristate "MediaTek MT6858 pin control"
|
||||
depends on OF
|
||||
depends on ARM64 || COMPILE_TEST
|
||||
default ARM64 && ARCH_MEDIATEK
|
||||
select PINCTRL_MTK_PARIS
|
||||
help
|
||||
Say yes here to support pin controller and gpio driver
|
||||
on the MediaTek MT6858 SoC.
|
||||
|
||||
config PINCTRL_MT6878
|
||||
bool "MediaTek MT6878 pin control"
|
||||
tristate "MediaTek MT6878 pin control"
|
||||
depends on OF
|
||||
depends on ARM64 || COMPILE_TEST
|
||||
default ARM64 && ARCH_MEDIATEK
|
||||
@@ -177,7 +187,7 @@ config PINCTRL_MT6878
|
||||
on the MediaTek MT6878 SoC.
|
||||
|
||||
config PINCTRL_MT6893
|
||||
bool "MediaTek Dimensity MT6893 pin control"
|
||||
tristate "MediaTek Dimensity MT6893 pin control"
|
||||
depends on OF
|
||||
depends on ARM64 || COMPILE_TEST
|
||||
default ARM64 && ARCH_MEDIATEK
|
||||
@@ -187,63 +197,63 @@ config PINCTRL_MT6893
|
||||
on the MediaTek Dimensity 1200 MT6893 Smartphone SoC.
|
||||
|
||||
config PINCTRL_MT7622
|
||||
bool "MediaTek MT7622 pin control"
|
||||
tristate "MediaTek MT7622 pin control"
|
||||
depends on OF
|
||||
depends on ARM64 || COMPILE_TEST
|
||||
default ARM64 && ARCH_MEDIATEK
|
||||
select PINCTRL_MTK_MOORE
|
||||
|
||||
config PINCTRL_MT7981
|
||||
bool "MediaTek MT7981 pin control"
|
||||
tristate "MediaTek MT7981 pin control"
|
||||
depends on OF
|
||||
depends on ARM64 || COMPILE_TEST
|
||||
default ARM64 && ARCH_MEDIATEK
|
||||
select PINCTRL_MTK_MOORE
|
||||
|
||||
config PINCTRL_MT7986
|
||||
bool "MediaTek MT7986 pin control"
|
||||
tristate "MediaTek MT7986 pin control"
|
||||
depends on OF
|
||||
depends on ARM64 || COMPILE_TEST
|
||||
default ARM64 && ARCH_MEDIATEK
|
||||
select PINCTRL_MTK_MOORE
|
||||
|
||||
config PINCTRL_MT7988
|
||||
bool "Mediatek MT7988 pin control"
|
||||
tristate "Mediatek MT7988 pin control"
|
||||
depends on OF
|
||||
depends on ARM64 || COMPILE_TEST
|
||||
default ARM64 && ARCH_MEDIATEK
|
||||
select PINCTRL_MTK_MOORE
|
||||
|
||||
config PINCTRL_MT8167
|
||||
bool "MediaTek MT8167 pin control"
|
||||
tristate "MediaTek MT8167 pin control"
|
||||
depends on OF
|
||||
depends on ARM64 || COMPILE_TEST
|
||||
default ARM64 && ARCH_MEDIATEK
|
||||
select PINCTRL_MTK
|
||||
|
||||
config PINCTRL_MT8173
|
||||
bool "MediaTek MT8173 pin control"
|
||||
tristate "MediaTek MT8173 pin control"
|
||||
depends on OF
|
||||
depends on ARM64 || COMPILE_TEST
|
||||
default ARM64 && ARCH_MEDIATEK
|
||||
select PINCTRL_MTK
|
||||
|
||||
config PINCTRL_MT8183
|
||||
bool "MediaTek MT8183 pin control"
|
||||
tristate "MediaTek MT8183 pin control"
|
||||
depends on OF
|
||||
depends on ARM64 || COMPILE_TEST
|
||||
default ARM64 && ARCH_MEDIATEK
|
||||
select PINCTRL_MTK_PARIS
|
||||
|
||||
config PINCTRL_MT8186
|
||||
bool "MediaTek MT8186 pin control"
|
||||
tristate "MediaTek MT8186 pin control"
|
||||
depends on OF
|
||||
depends on ARM64 || COMPILE_TEST
|
||||
default ARM64 && ARCH_MEDIATEK
|
||||
select PINCTRL_MTK_PARIS
|
||||
|
||||
config PINCTRL_MT8188
|
||||
bool "MediaTek MT8188 pin control"
|
||||
tristate "MediaTek MT8188 pin control"
|
||||
depends on OF
|
||||
depends on ARM64 || COMPILE_TEST
|
||||
default ARM64 && ARCH_MEDIATEK
|
||||
@@ -255,7 +265,7 @@ config PINCTRL_MT8188
|
||||
map specific eint which doesn't have real gpio pin.
|
||||
|
||||
config PINCTRL_MT8189
|
||||
bool "MediaTek MT8189 pin control"
|
||||
tristate "MediaTek MT8189 pin control"
|
||||
depends on OF
|
||||
depends on ARM64 || COMPILE_TEST
|
||||
default ARM64 && ARCH_MEDIATEK
|
||||
@@ -267,21 +277,21 @@ config PINCTRL_MT8189
|
||||
map specific eint which doesn't have real gpio pin.
|
||||
|
||||
config PINCTRL_MT8192
|
||||
bool "MediaTek MT8192 pin control"
|
||||
tristate "MediaTek MT8192 pin control"
|
||||
depends on OF
|
||||
depends on ARM64 || COMPILE_TEST
|
||||
default ARM64 && ARCH_MEDIATEK
|
||||
select PINCTRL_MTK_PARIS
|
||||
|
||||
config PINCTRL_MT8195
|
||||
bool "MediaTek MT8195 pin control"
|
||||
tristate "MediaTek MT8195 pin control"
|
||||
depends on OF
|
||||
depends on ARM64 || COMPILE_TEST
|
||||
default ARM64 && ARCH_MEDIATEK
|
||||
select PINCTRL_MTK_PARIS
|
||||
|
||||
config PINCTRL_MT8196
|
||||
bool "MediaTek MT8196 pin control"
|
||||
tristate "MediaTek MT8196 pin control"
|
||||
depends on OF
|
||||
depends on ARM64 || COMPILE_TEST
|
||||
default ARM64 && ARCH_MEDIATEK
|
||||
@@ -293,14 +303,14 @@ config PINCTRL_MT8196
|
||||
map specific eint which doesn't have real gpio pin.
|
||||
|
||||
config PINCTRL_MT8365
|
||||
bool "MediaTek MT8365 pin control"
|
||||
tristate "MediaTek MT8365 pin control"
|
||||
depends on OF
|
||||
depends on ARM64 || COMPILE_TEST
|
||||
default ARM64 && ARCH_MEDIATEK
|
||||
select PINCTRL_MTK
|
||||
|
||||
config PINCTRL_MT8516
|
||||
bool "MediaTek MT8516 pin control"
|
||||
tristate "MediaTek MT8516 pin control"
|
||||
depends on OF
|
||||
depends on ARM64 || COMPILE_TEST
|
||||
default ARM64 && ARCH_MEDIATEK
|
||||
@@ -308,7 +318,7 @@ config PINCTRL_MT8516
|
||||
|
||||
# For PMIC
|
||||
config PINCTRL_MT6397
|
||||
bool "MediaTek MT6397 pin control"
|
||||
tristate "MediaTek MT6397 pin control"
|
||||
depends on MFD_MT6397 || COMPILE_TEST
|
||||
depends on OF
|
||||
default MFD_MT6397
|
||||
|
||||
@@ -22,6 +22,7 @@ obj-$(CONFIG_PINCTRL_MT6765) += pinctrl-mt6765.o
|
||||
obj-$(CONFIG_PINCTRL_MT6779) += pinctrl-mt6779.o
|
||||
obj-$(CONFIG_PINCTRL_MT6795) += pinctrl-mt6795.o
|
||||
obj-$(CONFIG_PINCTRL_MT6797) += pinctrl-mt6797.o
|
||||
obj-$(CONFIG_PINCTRL_MT6858) += pinctrl-mt6858.o
|
||||
obj-$(CONFIG_PINCTRL_MT6878) += pinctrl-mt6878.o
|
||||
obj-$(CONFIG_PINCTRL_MT6893) += pinctrl-mt6893.o
|
||||
obj-$(CONFIG_PINCTRL_MT7622) += pinctrl-mt7622.o
|
||||
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user