diff --git a/Documentation/devicetree/bindings/pinctrl/apple,pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/apple,pinctrl.yaml index 41073176bc69..f08d2c4f5784 100644 --- a/Documentation/devicetree/bindings/pinctrl/apple,pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/apple,pinctrl.yaml @@ -20,6 +20,8 @@ properties: - items: - enum: - apple,t6020-pinctrl + - apple,t6030-pinctrl + - apple,t6031-pinctrl - apple,t8122-pinctrl - const: apple,t8103-pinctrl - items: diff --git a/Documentation/devicetree/bindings/pinctrl/aspeed,ast2700-soc1-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/aspeed,ast2700-soc1-pinctrl.yaml index 76944fd14e2c..fe7cef4fef6a 100644 --- a/Documentation/devicetree/bindings/pinctrl/aspeed,ast2700-soc1-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/aspeed,ast2700-soc1-pinctrl.yaml @@ -356,6 +356,7 @@ patternProperties: - I3C8 - I3C9 - JTAGM1 + - JTAGM1TRST - LPC0 - LPC1 - LTPI diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,mt6858-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt6858-pinctrl.yaml new file mode 100644 index 000000000000..9b834e87afde --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt6858-pinctrl.yaml @@ -0,0 +1,190 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/mediatek,mt6858-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek MT6858 Pin Controller + +maintainers: + - Nikolai Burov + +description: + The MediaTek's MT6858 Pin controller is used to control SoC pins. + +properties: + compatible: + const: mediatek,mt6858-pinctrl + + reg: + items: + - description: gpio base + - description: lm group IO + - description: rb group IO + - description: bm2 group IO + - description: bm group IO + - description: bm1 group IO + - description: lt group IO + - description: lt1 group IO + - description: rt group IO + - description: rt1 group IO + - description: eint south group IO + - description: eint west group IO + - description: eint east group IO + - description: eint center group IO + + reg-names: + items: + - const: base + - const: lm + - const: rb + - const: bm2 + - const: bm + - const: bm1 + - const: lt + - const: lt1 + - const: rt + - const: rt1 + - const: eint0 + - const: eint1 + - const: eint2 + - const: eint3 + + interrupts: + maxItems: 1 + + interrupt-controller: true + + '#interrupt-cells': + const: 2 + + gpio-controller: true + + '#gpio-cells': + const: 2 + + gpio-ranges: + maxItems: 1 + + gpio-line-names: true + +# PIN CONFIGURATION NODES +patternProperties: + '-pins$': + type: object + additionalProperties: false + + patternProperties: + '^pins': + type: object + $ref: /schemas/pinctrl/pincfg-node.yaml + additionalProperties: false + description: + A pinctrl node should contain at least one subnodes representing the + pinctrl groups available on the machine. Each subnode will list the + pins it needs, and how they should be configured, with regard to muxer + configuration, pullups, drive strength, input enable/disable and input + schmitt. + + properties: + pinmux: + description: + Integer array, represents gpio pin number and mux setting. + Supported pin number and mux varies for different SoCs, and are + defined as macros in arch/arm64/boot/dts/mediatek/mt6858-pinfunc.h + for this SoC. + + drive-strength: + enum: [2, 4, 6, 8, 10, 12, 14, 16] + + bias-pull-down: + oneOf: + - type: boolean + description: normal pull down. + - enum: [100, 101, 102, 103] + description: PUPD/R1/R0 pull down type. See MTK_PUPD_SET_R1R0_ + defines in dt-bindings/pinctrl/mt65xx.h. + - enum: [200, 201, 202, 203] + description: RSEL pull down type. See MTK_PULL_SET_RSEL_ defines + in dt-bindings/pinctrl/mt65xx.h. + + bias-pull-up: + oneOf: + - type: boolean + description: normal pull up. + - enum: [100, 101, 102, 103] + description: PUPD/R1/R0 pull up type. See MTK_PUPD_SET_R1R0_ + defines in dt-bindings/pinctrl/mt65xx.h. + - enum: [200, 201, 202, 203] + description: RSEL pull up type. See MTK_PULL_SET_RSEL_ defines + in dt-bindings/pinctrl/mt65xx.h. + + bias-disable: true + + output-high: true + + output-low: true + + input-enable: true + + input-disable: true + + input-schmitt-enable: true + + input-schmitt-disable: true + + required: + - pinmux + +required: + - compatible + - reg + - interrupts + - interrupt-controller + - '#interrupt-cells' + - gpio-controller + - '#gpio-cells' + - gpio-ranges + +additionalProperties: false + +examples: + - | + #include + #include + #define PINMUX_GPIO149__FUNC_SCL5 (MTK_PIN_NO(149) | 1) + #define PINMUX_GPIO150__FUNC_SDA5 (MTK_PIN_NO(150) | 1) + + pio: pinctrl@10005000 { + compatible = "mediatek,mt6858-pinctrl"; + reg = <0x10005000 0x1000>, + <0x11b20000 0x1000>, + <0x11c10000 0x1000>, + <0x11d10000 0x1000>, + <0x11d30000 0x1000>, + <0x11d40000 0x1000>, + <0x11e20000 0x1000>, + <0x11e30000 0x1000>, + <0x11ed0000 0x1000>, + <0x11ee0000 0x1000>, + <0x11b00000 0x1000>, + <0x11e60000 0x1000>, + <0x11e80000 0x1000>, + <0x1c01e000 0x1000>; + reg-names = "base", "lm", "rb", "bm2", "bm", "bm1", "lt", "lt1", + "rt", "rt1", "eint0", "eint1", "eint2", "eint3"; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pio 0 0 197>; + interrupt-controller; + interrupts = ; + #interrupt-cells = <2>; + + i2c5-pins { + pins { + pinmux = , + ; + bias-disable; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,mt7622-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt7622-pinctrl.yaml index 6b925c5099cc..021307b6d801 100644 --- a/Documentation/devicetree/bindings/pinctrl/mediatek,mt7622-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt7622-pinctrl.yaml @@ -65,6 +65,11 @@ then: - "#interrupt-cells" patternProperties: + "-hog(-[0-9]+)?$": + type: object + required: + - gpio-hog + '-pins(-[a-z]+)?$': type: object additionalProperties: false diff --git a/Documentation/devicetree/bindings/pinctrl/nxp,s32g2-siul2-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/nxp,s32g2-siul2-pinctrl.yaml index a24286e4def6..36f2393fa406 100644 --- a/Documentation/devicetree/bindings/pinctrl/nxp,s32g2-siul2-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/nxp,s32g2-siul2-pinctrl.yaml @@ -1,5 +1,5 @@ # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) -# Copyright 2022 NXP +# Copyright 2022, 2026 NXP %YAML 1.2 --- $id: http://devicetree.org/schemas/pinctrl/nxp,s32g2-siul2-pinctrl.yaml# @@ -17,8 +17,10 @@ description: | SIUL2_0 @ 0x4009c000 SIUL2_1 @ 0x44010000 - Every SIUL2 region has multiple register types, and here only MSCR and - IMCR registers need to be revealed for kernel to configure pinmux. + Every SIUL2 region has multiple register types. MSCR and IMCR registers + need to be revealed for kernel to configure pinmux. PGPDO and PGPDI + registers are used for GPIO output/input operations. EIRQ registers + are used for external interrupt configuration. Please note that some register indexes are reserved in S32G2, such as MSCR102-MSCR111, MSCR123-MSCR143, IMCR84-IMCR118 and IMCR398-IMCR429. @@ -29,14 +31,22 @@ properties: - nxp,s32g2-siul2-pinctrl reg: + minItems: 6 description: | - A list of MSCR/IMCR register regions to be reserved. + A list of MSCR/IMCR/PGPDO/PGPDI/EIRQ register regions to be reserved. - MSCR (Multiplexed Signal Configuration Register) An MSCR register can configure the associated pin as either a GPIO pin or a function output pin depends on the selected signal source. - IMCR (Input Multiplexed Signal Configuration Register) An IMCR register can configure the associated pin as function input pin depends on the selected signal source. + - PGPDO (Parallel GPIO Pad Data Out Register) + A PGPDO register is used to set the output value of a GPIO pin. + - PGPDI (Parallel GPIO Pad Data In Register) + A PGPDI register is used to read the input value of a GPIO pin. + - EIRQ (External Interrupt Request) + EIRQ registers are used to configure and manage external interrupts. + items: - description: MSCR registers group 0 in SIUL2_0 - description: MSCR registers group 1 in SIUL2_1 @@ -44,6 +54,28 @@ properties: - description: IMCR registers group 0 in SIUL2_0 - description: IMCR registers group 1 in SIUL2_1 - description: IMCR registers group 2 in SIUL2_1 + - description: PGPDO registers in SIUL2_0 + - description: PGPDI registers in SIUL2_0 + - description: PGPDO registers in SIUL2_1 + - description: PGPDI registers in SIUL2_1 + - description: EIRQ registers in SIUL2_1 + + gpio-controller: true + + "#gpio-cells": + const: 2 + + gpio-ranges: + minItems: 1 + maxItems: 4 + + interrupt-controller: true + + "#interrupt-cells": + const: 2 + + interrupts: + maxItems: 1 patternProperties: '-pins$': @@ -86,11 +118,38 @@ required: - compatible - reg +oneOf: + - description: Legacy pinctrl-only node + properties: + reg: + maxItems: 6 + + gpio-controller: false + "#gpio-cells": false + gpio-ranges: false + interrupt-controller: false + "#interrupt-cells": false + interrupts: false + + - description: Pinctrl node with GPIO and external interrupt support + required: + - gpio-controller + - "#gpio-cells" + - gpio-ranges + - interrupt-controller + - "#interrupt-cells" + - interrupts + properties: + reg: + minItems: 11 + additionalProperties: false examples: - | - pinctrl@4009c240 { + #include + + pinctrl: pinctrl@4009c240 { compatible = "nxp,s32g2-siul2-pinctrl"; /* MSCR0-MSCR101 registers on siul2_0 */ @@ -104,7 +163,26 @@ examples: /* IMCR119-IMCR397 registers on siul2_1 */ <0x44010c1c 0x45c>, /* IMCR430-IMCR495 registers on siul2_1 */ - <0x440110f8 0x108>; + <0x440110f8 0x108>, + /* PGPDO registers on siul2_0 */ + <0x4009d700 0x10>, + /* PGPDI registers on siul2_0 */ + <0x4009d740 0x10>, + /* PGPDO registers on siul2_1 */ + <0x44011700 0x18>, + /* PGPDI registers on siul2_1 */ + <0x44011740 0x18>, + /* EIRQ registers on siul2_1 */ + <0x44010010 0x34>; + + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl 0 0 102>, + <&pinctrl 112 112 79>; + + interrupt-controller; + #interrupt-cells = <2>; + interrupts = ; llce-can0-pins { llce-can0-grp0 { diff --git a/Documentation/driver-api/pin-control.rst b/Documentation/driver-api/pin-control.rst index 1f585ecca63c..80106e44a368 100644 --- a/Documentation/driver-api/pin-control.rst +++ b/Documentation/driver-api/pin-control.rst @@ -1175,7 +1175,7 @@ Possible standard state names are: "default", "init", "sleep" and "idle". selected after the driver probe. - the ``sleep`` and ``idle`` states are for power management and can only - be selected with the PM API bellow. + be selected with the PM API below. PM interfaces ================= diff --git a/MAINTAINERS b/MAINTAINERS index 0e6de5c39165..6db2662c0bec 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -22500,6 +22500,13 @@ L: linux-arm-msm@vger.kernel.org S: Maintained F: drivers/firmware/qcom/qcom_qseecom_uefisecapp.c +QUALCOMM PINCTRL DRIVERS +M: Bartosz Golaszewski +L: linux-arm-msm@vger.kernel.org +S: Supported +F: Documentation/devicetree/bindings/pinctrl/qcom,*.yaml +F: drivers/pinctrl/qcom/ + QUALCOMM RMNET DRIVER M: Subash Abhinov Kasiviswanathan M: Sean Tranchetti diff --git a/arch/arm64/boot/dts/mediatek/mt6858-pinfunc.h b/arch/arm64/boot/dts/mediatek/mt6858-pinfunc.h new file mode 100644 index 000000000000..a229b2578a16 --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt6858-pinfunc.h @@ -0,0 +1,1335 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2025 MediaTek Inc. + * Author: Alice Chao + */ + +#ifndef __MT6858_PINFUNC_H +#define __MT6858_PINFUNC_H + +#include + +#define PINMUX_GPIO0__FUNC_GPIO0 (MTK_PIN_NO(0) | 0) +#define PINMUX_GPIO0__FUNC_TP_GPIO0_AO (MTK_PIN_NO(0) | 1) +#define PINMUX_GPIO0__FUNC_MD_INT0 (MTK_PIN_NO(0) | 3) +#define PINMUX_GPIO0__FUNC_SCP_SCL4 (MTK_PIN_NO(0) | 5) +#define PINMUX_GPIO0__FUNC_DBG_MON_A0 (MTK_PIN_NO(0) | 7) +#define PINMUX_GPIO0__FUNC_IOBIST0 (MTK_PIN_NO(0) | 8) + +#define PINMUX_GPIO1__FUNC_GPIO1 (MTK_PIN_NO(1) | 0) +#define PINMUX_GPIO1__FUNC_TP_GPIO1_AO (MTK_PIN_NO(1) | 1) +#define PINMUX_GPIO1__FUNC_SRCLKENA2 (MTK_PIN_NO(1) | 2) +#define PINMUX_GPIO1__FUNC_MD_INT3 (MTK_PIN_NO(1) | 3) +#define PINMUX_GPIO1__FUNC_SCP_DMIC_CLK (MTK_PIN_NO(1) | 4) +#define PINMUX_GPIO1__FUNC_DMIC_CLK (MTK_PIN_NO(1) | 5) +#define PINMUX_GPIO1__FUNC_SCP_SCL5 (MTK_PIN_NO(1) | 6) +#define PINMUX_GPIO1__FUNC_DBG_MON_A1 (MTK_PIN_NO(1) | 7) +#define PINMUX_GPIO1__FUNC_IOBIST1 (MTK_PIN_NO(1) | 8) + +#define PINMUX_GPIO2__FUNC_GPIO2 (MTK_PIN_NO(2) | 0) +#define PINMUX_GPIO2__FUNC_TP_GPIO2_AO (MTK_PIN_NO(2) | 1) +#define PINMUX_GPIO2__FUNC_MD_INT4 (MTK_PIN_NO(2) | 3) +#define PINMUX_GPIO2__FUNC_SCP_DMIC_DAT (MTK_PIN_NO(2) | 4) +#define PINMUX_GPIO2__FUNC_DMIC_DAT (MTK_PIN_NO(2) | 5) +#define PINMUX_GPIO2__FUNC_SCP_SDA5 (MTK_PIN_NO(2) | 6) +#define PINMUX_GPIO2__FUNC_DBG_MON_A2 (MTK_PIN_NO(2) | 7) +#define PINMUX_GPIO2__FUNC_IOBIST2 (MTK_PIN_NO(2) | 8) + +#define PINMUX_GPIO3__FUNC_GPIO3 (MTK_PIN_NO(3) | 0) +#define PINMUX_GPIO3__FUNC_TP_GPIO3_AO (MTK_PIN_NO(3) | 1) +#define PINMUX_GPIO3__FUNC_SPI7_CLK (MTK_PIN_NO(3) | 2) +#define PINMUX_GPIO3__FUNC_TP_UTXD2_VLP (MTK_PIN_NO(3) | 3) +#define PINMUX_GPIO3__FUNC_SSPM_UTXD_AO_VLP (MTK_PIN_NO(3) | 4) +#define PINMUX_GPIO3__FUNC_MD_MCIF_UTXD0 (MTK_PIN_NO(3) | 5) +#define PINMUX_GPIO3__FUNC_IOBIST3 (MTK_PIN_NO(3) | 8) + +#define PINMUX_GPIO4__FUNC_GPIO4 (MTK_PIN_NO(4) | 0) +#define PINMUX_GPIO4__FUNC_TP_GPIO4_AO (MTK_PIN_NO(4) | 1) +#define PINMUX_GPIO4__FUNC_SPI7_CSB (MTK_PIN_NO(4) | 2) +#define PINMUX_GPIO4__FUNC_TP_URXD2_VLP (MTK_PIN_NO(4) | 3) +#define PINMUX_GPIO4__FUNC_SSPM_URXD_AO_VLP (MTK_PIN_NO(4) | 4) +#define PINMUX_GPIO4__FUNC_MD_MCIF_URXD0 (MTK_PIN_NO(4) | 5) +#define PINMUX_GPIO4__FUNC_IOBIST4 (MTK_PIN_NO(4) | 8) + +#define PINMUX_GPIO5__FUNC_GPIO5 (MTK_PIN_NO(5) | 0) +#define PINMUX_GPIO5__FUNC_TP_GPIO5_AO (MTK_PIN_NO(5) | 1) +#define PINMUX_GPIO5__FUNC_SPI7_MO (MTK_PIN_NO(5) | 2) +#define PINMUX_GPIO5__FUNC_IOBIST5 (MTK_PIN_NO(5) | 8) + +#define PINMUX_GPIO6__FUNC_GPIO6 (MTK_PIN_NO(6) | 0) +#define PINMUX_GPIO6__FUNC_TP_GPIO6_AO (MTK_PIN_NO(6) | 1) +#define PINMUX_GPIO6__FUNC_SPI7_MI (MTK_PIN_NO(6) | 2) +#define PINMUX_GPIO6__FUNC_GPS_PPS (MTK_PIN_NO(6) | 3) +#define PINMUX_GPIO6__FUNC_MD32_0_GPIO0 (MTK_PIN_NO(6) | 4) +#define PINMUX_GPIO6__FUNC_IOBIST6 (MTK_PIN_NO(6) | 8) + +#define PINMUX_GPIO7__FUNC_GPIO7 (MTK_PIN_NO(7) | 0) +#define PINMUX_GPIO7__FUNC_TP_GPIO7_AO (MTK_PIN_NO(7) | 1) +#define PINMUX_GPIO7__FUNC_SRCLKENA1 (MTK_PIN_NO(7) | 2) +#define PINMUX_GPIO7__FUNC_PWM_1 (MTK_PIN_NO(7) | 3) +#define PINMUX_GPIO7__FUNC_MD32_1_GPIO0 (MTK_PIN_NO(7) | 4) +#define PINMUX_GPIO7__FUNC_SCP_SDA4 (MTK_PIN_NO(7) | 5) +#define PINMUX_GPIO7__FUNC_MD_INT4 (MTK_PIN_NO(7) | 6) +#define PINMUX_GPIO7__FUNC_IOBIST7 (MTK_PIN_NO(7) | 8) + +#define PINMUX_GPIO8__FUNC_GPIO8 (MTK_PIN_NO(8) | 0) +#define PINMUX_GPIO8__FUNC_SSPM_JTAG_TRSTN_VCORE (MTK_PIN_NO(8) | 1) +#define PINMUX_GPIO8__FUNC_SCP_JTAG0_TRSTN_VCORE (MTK_PIN_NO(8) | 2) +#define PINMUX_GPIO8__FUNC_CONN_BGF_MCU_TRST_B (MTK_PIN_NO(8) | 6) +#define PINMUX_GPIO8__FUNC_IOBIST8 (MTK_PIN_NO(8) | 8) + +#define PINMUX_GPIO9__FUNC_GPIO9 (MTK_PIN_NO(9) | 0) +#define PINMUX_GPIO9__FUNC_SSPM_JTAG_TCK_VCORE (MTK_PIN_NO(9) | 1) +#define PINMUX_GPIO9__FUNC_SCP_JTAG0_TCK_VCORE (MTK_PIN_NO(9) | 2) +#define PINMUX_GPIO9__FUNC_CONN_BGF_MCU_TCK (MTK_PIN_NO(9) | 6) +#define PINMUX_GPIO9__FUNC_IOBIST9 (MTK_PIN_NO(9) | 8) + +#define PINMUX_GPIO10__FUNC_GPIO10 (MTK_PIN_NO(10) | 0) +#define PINMUX_GPIO10__FUNC_SSPM_JTAG_TMS_VCORE (MTK_PIN_NO(10) | 1) +#define PINMUX_GPIO10__FUNC_SCP_JTAG0_TMS_VCORE (MTK_PIN_NO(10) | 2) +#define PINMUX_GPIO10__FUNC_CONN_BGF_MCU_TMS (MTK_PIN_NO(10) | 6) +#define PINMUX_GPIO10__FUNC_IOBIST10 (MTK_PIN_NO(10) | 8) + +#define PINMUX_GPIO11__FUNC_GPIO11 (MTK_PIN_NO(11) | 0) +#define PINMUX_GPIO11__FUNC_SSPM_JTAG_TDI_VCORE (MTK_PIN_NO(11) | 1) +#define PINMUX_GPIO11__FUNC_SCP_JTAG0_TDI_VCORE (MTK_PIN_NO(11) | 2) +#define PINMUX_GPIO11__FUNC_CONN_BGF_MCU_TDI (MTK_PIN_NO(11) | 6) +#define PINMUX_GPIO11__FUNC_IOBIST11 (MTK_PIN_NO(11) | 8) + +#define PINMUX_GPIO12__FUNC_GPIO12 (MTK_PIN_NO(12) | 0) +#define PINMUX_GPIO12__FUNC_SSPM_JTAG_TDO_VCORE (MTK_PIN_NO(12) | 1) +#define PINMUX_GPIO12__FUNC_SCP_JTAG0_TDO_VCORE (MTK_PIN_NO(12) | 2) +#define PINMUX_GPIO12__FUNC_CONN_BGF_MCU_TDO (MTK_PIN_NO(12) | 6) +#define PINMUX_GPIO12__FUNC_IOBIST12 (MTK_PIN_NO(12) | 8) + +#define PINMUX_GPIO13__FUNC_GPIO13 (MTK_PIN_NO(13) | 0) +#define PINMUX_GPIO13__FUNC_TP_GPIO8_AO (MTK_PIN_NO(13) | 1) +#define PINMUX_GPIO13__FUNC_HFRP_JTAG0_TRSTN (MTK_PIN_NO(13) | 2) +#define PINMUX_GPIO13__FUNC_MFG_EB_JTAG_TRSTN (MTK_PIN_NO(13) | 3) +#define PINMUX_GPIO13__FUNC_SSPM_JTAG_TRSTN_VLP (MTK_PIN_NO(13) | 4) +#define PINMUX_GPIO13__FUNC_SPM_JTAG_TRSTN_VLP (MTK_PIN_NO(13) | 5) +#define PINMUX_GPIO13__FUNC_SCP_JTAG0_TRSTN_VLP (MTK_PIN_NO(13) | 6) +#define PINMUX_GPIO13__FUNC_IO_JTAG_TRSTN (MTK_PIN_NO(13) | 7) +#define PINMUX_GPIO13__FUNC_IOBIST13 (MTK_PIN_NO(13) | 8) + +#define PINMUX_GPIO14__FUNC_GPIO14 (MTK_PIN_NO(14) | 0) +#define PINMUX_GPIO14__FUNC_TP_GPIO9_AO (MTK_PIN_NO(14) | 1) +#define PINMUX_GPIO14__FUNC_HFRP_JTAG0_TCK (MTK_PIN_NO(14) | 2) +#define PINMUX_GPIO14__FUNC_MFG_EB_JTAG_TCK (MTK_PIN_NO(14) | 3) +#define PINMUX_GPIO14__FUNC_SSPM_JTAG_TCK_VLP (MTK_PIN_NO(14) | 4) +#define PINMUX_GPIO14__FUNC_SPM_JTAG_TCK_VLP (MTK_PIN_NO(14) | 5) +#define PINMUX_GPIO14__FUNC_SCP_JTAG0_TCK_VLP (MTK_PIN_NO(14) | 6) +#define PINMUX_GPIO14__FUNC_IO_JTAG_TCK (MTK_PIN_NO(14) | 7) +#define PINMUX_GPIO14__FUNC_IOBIST14 (MTK_PIN_NO(14) | 8) + +#define PINMUX_GPIO15__FUNC_GPIO15 (MTK_PIN_NO(15) | 0) +#define PINMUX_GPIO15__FUNC_TP_GPIO10_AO (MTK_PIN_NO(15) | 1) +#define PINMUX_GPIO15__FUNC_HFRP_JTAG0_TMS (MTK_PIN_NO(15) | 2) +#define PINMUX_GPIO15__FUNC_MFG_EB_JTAG_TMS (MTK_PIN_NO(15) | 3) +#define PINMUX_GPIO15__FUNC_SSPM_JTAG_TMS_VLP (MTK_PIN_NO(15) | 4) +#define PINMUX_GPIO15__FUNC_SPM_JTAG_TMS_VLP (MTK_PIN_NO(15) | 5) +#define PINMUX_GPIO15__FUNC_SCP_JTAG0_TMS_VLP (MTK_PIN_NO(15) | 6) +#define PINMUX_GPIO15__FUNC_IO_JTAG_TMS (MTK_PIN_NO(15) | 7) +#define PINMUX_GPIO15__FUNC_IOBIST15 (MTK_PIN_NO(15) | 8) + +#define PINMUX_GPIO16__FUNC_GPIO16 (MTK_PIN_NO(16) | 0) +#define PINMUX_GPIO16__FUNC_TP_GPIO11_AO (MTK_PIN_NO(16) | 1) +#define PINMUX_GPIO16__FUNC_HFRP_JTAG0_TDI (MTK_PIN_NO(16) | 2) +#define PINMUX_GPIO16__FUNC_MFG_EB_JTAG_TDI (MTK_PIN_NO(16) | 3) +#define PINMUX_GPIO16__FUNC_SSPM_JTAG_TDI_VLP (MTK_PIN_NO(16) | 4) +#define PINMUX_GPIO16__FUNC_SPM_JTAG_TDI_VLP (MTK_PIN_NO(16) | 5) +#define PINMUX_GPIO16__FUNC_SCP_JTAG0_TDI_VLP (MTK_PIN_NO(16) | 6) +#define PINMUX_GPIO16__FUNC_IO_JTAG_TDI (MTK_PIN_NO(16) | 7) +#define PINMUX_GPIO16__FUNC_IOBIST16 (MTK_PIN_NO(16) | 8) + +#define PINMUX_GPIO17__FUNC_GPIO17 (MTK_PIN_NO(17) | 0) +#define PINMUX_GPIO17__FUNC_TP_GPIO12_AO (MTK_PIN_NO(17) | 1) +#define PINMUX_GPIO17__FUNC_HFRP_JTAG0_TDO (MTK_PIN_NO(17) | 2) +#define PINMUX_GPIO17__FUNC_MFG_EB_JTAG_TDO (MTK_PIN_NO(17) | 3) +#define PINMUX_GPIO17__FUNC_SSPM_JTAG_TDO_VLP (MTK_PIN_NO(17) | 4) +#define PINMUX_GPIO17__FUNC_SPM_JTAG_TDO_VLP (MTK_PIN_NO(17) | 5) +#define PINMUX_GPIO17__FUNC_SCP_JTAG0_TDO_VLP (MTK_PIN_NO(17) | 6) +#define PINMUX_GPIO17__FUNC_IO_JTAG_TDO (MTK_PIN_NO(17) | 7) +#define PINMUX_GPIO17__FUNC_IOBIST17 (MTK_PIN_NO(17) | 8) + +#define PINMUX_GPIO18__FUNC_GPIO18 (MTK_PIN_NO(18) | 0) +#define PINMUX_GPIO18__FUNC_MD1_SIM2_SRST (MTK_PIN_NO(18) | 1) +#define PINMUX_GPIO18__FUNC_MD1_SIM1_SRST (MTK_PIN_NO(18) | 2) +#define PINMUX_GPIO18__FUNC_IDDIG (MTK_PIN_NO(18) | 5) +#define PINMUX_GPIO18__FUNC_TSFDC_EN (MTK_PIN_NO(18) | 6) +#define PINMUX_GPIO18__FUNC_IOBIST18 (MTK_PIN_NO(18) | 8) + +#define PINMUX_GPIO19__FUNC_GPIO19 (MTK_PIN_NO(19) | 0) +#define PINMUX_GPIO19__FUNC_MD1_SIM2_SCLK (MTK_PIN_NO(19) | 1) +#define PINMUX_GPIO19__FUNC_MD1_SIM1_SCLK (MTK_PIN_NO(19) | 2) +#define PINMUX_GPIO19__FUNC_TP_UTXD2_VCORE (MTK_PIN_NO(19) | 3) +#define PINMUX_GPIO19__FUNC_SSPM_UTXD_AO_VCORE (MTK_PIN_NO(19) | 4) +#define PINMUX_GPIO19__FUNC_MD32_1_TXD (MTK_PIN_NO(19) | 5) +#define PINMUX_GPIO19__FUNC_UTXD2 (MTK_PIN_NO(19) | 6) +#define PINMUX_GPIO19__FUNC_IOBIST19 (MTK_PIN_NO(19) | 8) + +#define PINMUX_GPIO20__FUNC_GPIO20 (MTK_PIN_NO(20) | 0) +#define PINMUX_GPIO20__FUNC_MD1_SIM2_SIO (MTK_PIN_NO(20) | 1) +#define PINMUX_GPIO20__FUNC_MD1_SIM1_SIO (MTK_PIN_NO(20) | 2) +#define PINMUX_GPIO20__FUNC_TP_URXD2_VCORE (MTK_PIN_NO(20) | 3) +#define PINMUX_GPIO20__FUNC_SSPM_URXD_AO_VCORE (MTK_PIN_NO(20) | 4) +#define PINMUX_GPIO20__FUNC_MD32_1_RXD (MTK_PIN_NO(20) | 5) +#define PINMUX_GPIO20__FUNC_URXD2 (MTK_PIN_NO(20) | 6) +#define PINMUX_GPIO20__FUNC_IOBIST20 (MTK_PIN_NO(20) | 8) + +#define PINMUX_GPIO21__FUNC_GPIO21 (MTK_PIN_NO(21) | 0) +#define PINMUX_GPIO21__FUNC_KPROW1 (MTK_PIN_NO(21) | 1) +#define PINMUX_GPIO21__FUNC_CONN_WIFI_TXD (MTK_PIN_NO(21) | 2) +#define PINMUX_GPIO21__FUNC_CONN_BT_TXD (MTK_PIN_NO(21) | 3) +#define PINMUX_GPIO21__FUNC_HFRP_UTXD1 (MTK_PIN_NO(21) | 4) +#define PINMUX_GPIO21__FUNC_TP_UTXD1_VCORE (MTK_PIN_NO(21) | 5) +#define PINMUX_GPIO21__FUNC_CONN_BGF_UART0_TXD (MTK_PIN_NO(21) | 6) +#define PINMUX_GPIO21__FUNC_MD_UTXD1 (MTK_PIN_NO(21) | 7) +#define PINMUX_GPIO21__FUNC_IOBIST21 (MTK_PIN_NO(21) | 8) + +#define PINMUX_GPIO22__FUNC_GPIO22 (MTK_PIN_NO(22) | 0) +#define PINMUX_GPIO22__FUNC_KPCOL1 (MTK_PIN_NO(22) | 1) +#define PINMUX_GPIO22__FUNC_PMSR_SMAP (MTK_PIN_NO(22) | 3) +#define PINMUX_GPIO22__FUNC_HFRP_URXD1 (MTK_PIN_NO(22) | 4) +#define PINMUX_GPIO22__FUNC_TP_URXD1_VCORE (MTK_PIN_NO(22) | 5) +#define PINMUX_GPIO22__FUNC_CONN_BGF_UART0_RXD (MTK_PIN_NO(22) | 6) +#define PINMUX_GPIO22__FUNC_MD_URXD1 (MTK_PIN_NO(22) | 7) +#define PINMUX_GPIO22__FUNC_IOBIST22 (MTK_PIN_NO(22) | 8) + +#define PINMUX_GPIO23__FUNC_GPIO23 (MTK_PIN_NO(23) | 0) +#define PINMUX_GPIO23__FUNC_CONN_TCXOENA_REQ (MTK_PIN_NO(23) | 3) +#define PINMUX_GPIO23__FUNC_USB_DRVVBUS (MTK_PIN_NO(23) | 5) +#define PINMUX_GPIO23__FUNC_DBG_MON_A6 (MTK_PIN_NO(23) | 7) +#define PINMUX_GPIO23__FUNC_IOBIST23 (MTK_PIN_NO(23) | 8) + +#define PINMUX_GPIO24__FUNC_GPIO24 (MTK_PIN_NO(24) | 0) +#define PINMUX_GPIO24__FUNC_KPROW0 (MTK_PIN_NO(24) | 1) +#define PINMUX_GPIO24__FUNC_I2SIN2_MCK (MTK_PIN_NO(24) | 2) +#define PINMUX_GPIO24__FUNC_USB_DRVVBUS (MTK_PIN_NO(24) | 5) +#define PINMUX_GPIO24__FUNC_DBG_MON_B0 (MTK_PIN_NO(24) | 7) +#define PINMUX_GPIO24__FUNC_IOBIST24 (MTK_PIN_NO(24) | 8) + +#define PINMUX_GPIO25__FUNC_GPIO25 (MTK_PIN_NO(25) | 0) +#define PINMUX_GPIO25__FUNC_PWM_3 (MTK_PIN_NO(25) | 4) +#define PINMUX_GPIO25__FUNC_DBG_MON_A8 (MTK_PIN_NO(25) | 7) +#define PINMUX_GPIO25__FUNC_IOBIST25 (MTK_PIN_NO(25) | 8) + +#define PINMUX_GPIO26__FUNC_GPIO26 (MTK_PIN_NO(26) | 0) +#define PINMUX_GPIO26__FUNC_CMFLASH0 (MTK_PIN_NO(26) | 1) +#define PINMUX_GPIO26__FUNC_CONN_TCXOENA_REQ (MTK_PIN_NO(26) | 2) +#define PINMUX_GPIO26__FUNC_MD32_0_GPIO0 (MTK_PIN_NO(26) | 3) +#define PINMUX_GPIO26__FUNC_PWM_0 (MTK_PIN_NO(26) | 4) +#define PINMUX_GPIO26__FUNC_VBUSVALID (MTK_PIN_NO(26) | 5) +#define PINMUX_GPIO26__FUNC_IOBIST26 (MTK_PIN_NO(26) | 8) + +#define PINMUX_GPIO27__FUNC_GPIO27 (MTK_PIN_NO(27) | 0) +#define PINMUX_GPIO27__FUNC_CMFLASH1 (MTK_PIN_NO(27) | 1) +#define PINMUX_GPIO27__FUNC_DAP_SONIC_SWCK (MTK_PIN_NO(27) | 6) +#define PINMUX_GPIO27__FUNC_DBG_MON_A10 (MTK_PIN_NO(27) | 7) +#define PINMUX_GPIO27__FUNC_IOBIST27 (MTK_PIN_NO(27) | 8) + +#define PINMUX_GPIO28__FUNC_GPIO28 (MTK_PIN_NO(28) | 0) +#define PINMUX_GPIO28__FUNC_CMFLASH2 (MTK_PIN_NO(28) | 1) +#define PINMUX_GPIO28__FUNC_GPS_PPS (MTK_PIN_NO(28) | 4) +#define PINMUX_GPIO28__FUNC_DAP_SONIC_SWD (MTK_PIN_NO(28) | 6) +#define PINMUX_GPIO28__FUNC_DBG_MON_A11 (MTK_PIN_NO(28) | 7) +#define PINMUX_GPIO28__FUNC_IOBIST28 (MTK_PIN_NO(28) | 8) + +#define PINMUX_GPIO29__FUNC_GPIO29 (MTK_PIN_NO(29) | 0) +#define PINMUX_GPIO29__FUNC_CMFLASH3 (MTK_PIN_NO(29) | 1) +#define PINMUX_GPIO29__FUNC_SCL10 (MTK_PIN_NO(29) | 3) +#define PINMUX_GPIO29__FUNC_DAP_MD32_SWCK (MTK_PIN_NO(29) | 6) +#define PINMUX_GPIO29__FUNC_DBG_MON_A12 (MTK_PIN_NO(29) | 7) +#define PINMUX_GPIO29__FUNC_IOBIST29 (MTK_PIN_NO(29) | 8) + +#define PINMUX_GPIO30__FUNC_GPIO30 (MTK_PIN_NO(30) | 0) +#define PINMUX_GPIO30__FUNC_SDA10 (MTK_PIN_NO(30) | 3) +#define PINMUX_GPIO30__FUNC_DAP_MD32_SWD (MTK_PIN_NO(30) | 6) +#define PINMUX_GPIO30__FUNC_DBG_MON_A13 (MTK_PIN_NO(30) | 7) +#define PINMUX_GPIO30__FUNC_IOBIST30 (MTK_PIN_NO(30) | 8) + +#define PINMUX_GPIO31__FUNC_GPIO31 (MTK_PIN_NO(31) | 0) +#define PINMUX_GPIO31__FUNC_CMVREF0 (MTK_PIN_NO(31) | 1) +#define PINMUX_GPIO31__FUNC_SCL12 (MTK_PIN_NO(31) | 3) +#define PINMUX_GPIO31__FUNC_DBG_MON_A14 (MTK_PIN_NO(31) | 7) +#define PINMUX_GPIO31__FUNC_IOBIST31 (MTK_PIN_NO(31) | 8) + +#define PINMUX_GPIO32__FUNC_GPIO32 (MTK_PIN_NO(32) | 0) +#define PINMUX_GPIO32__FUNC_CMVREF1 (MTK_PIN_NO(32) | 1) +#define PINMUX_GPIO32__FUNC_SDA12 (MTK_PIN_NO(32) | 3) +#define PINMUX_GPIO32__FUNC_DBG_MON_A15 (MTK_PIN_NO(32) | 7) +#define PINMUX_GPIO32__FUNC_IOBIST32 (MTK_PIN_NO(32) | 8) + +#define PINMUX_GPIO33__FUNC_GPIO33 (MTK_PIN_NO(33) | 0) +#define PINMUX_GPIO33__FUNC_CMVREF2 (MTK_PIN_NO(33) | 1) +#define PINMUX_GPIO33__FUNC_USB_DRVVBUS (MTK_PIN_NO(33) | 3) +#define PINMUX_GPIO33__FUNC_DBG_MON_A16 (MTK_PIN_NO(33) | 7) +#define PINMUX_GPIO33__FUNC_IOBIST33 (MTK_PIN_NO(33) | 8) + +#define PINMUX_GPIO34__FUNC_GPIO34 (MTK_PIN_NO(34) | 0) +#define PINMUX_GPIO34__FUNC_CMVREF3 (MTK_PIN_NO(34) | 1) +#define PINMUX_GPIO34__FUNC_VBUSVALID (MTK_PIN_NO(34) | 3) +#define PINMUX_GPIO34__FUNC_DBG_MON_A17 (MTK_PIN_NO(34) | 7) +#define PINMUX_GPIO34__FUNC_IOBIST34 (MTK_PIN_NO(34) | 8) + +#define PINMUX_GPIO35__FUNC_GPIO35 (MTK_PIN_NO(35) | 0) +#define PINMUX_GPIO35__FUNC_CMVREF4 (MTK_PIN_NO(35) | 1) +#define PINMUX_GPIO35__FUNC_IDDIG (MTK_PIN_NO(35) | 3) +#define PINMUX_GPIO35__FUNC_DBG_MON_A18 (MTK_PIN_NO(35) | 7) +#define PINMUX_GPIO35__FUNC_IOBIST35 (MTK_PIN_NO(35) | 8) + +#define PINMUX_GPIO36__FUNC_GPIO36 (MTK_PIN_NO(36) | 0) +#define PINMUX_GPIO36__FUNC_CMMCLK0 (MTK_PIN_NO(36) | 1) +#define PINMUX_GPIO36__FUNC_CLKM0 (MTK_PIN_NO(36) | 2) +#define PINMUX_GPIO36__FUNC_DBG_MON_A19 (MTK_PIN_NO(36) | 7) +#define PINMUX_GPIO36__FUNC_IOBIST36 (MTK_PIN_NO(36) | 8) + +#define PINMUX_GPIO37__FUNC_GPIO37 (MTK_PIN_NO(37) | 0) +#define PINMUX_GPIO37__FUNC_CMMCLK1 (MTK_PIN_NO(37) | 1) +#define PINMUX_GPIO37__FUNC_CLKM1 (MTK_PIN_NO(37) | 2) +#define PINMUX_GPIO37__FUNC_MD32_1_GPIO0 (MTK_PIN_NO(37) | 4) +#define PINMUX_GPIO37__FUNC_DBG_MON_A20 (MTK_PIN_NO(37) | 7) +#define PINMUX_GPIO37__FUNC_IOBIST37 (MTK_PIN_NO(37) | 8) + +#define PINMUX_GPIO38__FUNC_GPIO38 (MTK_PIN_NO(38) | 0) +#define PINMUX_GPIO38__FUNC_CMMCLK2 (MTK_PIN_NO(38) | 1) +#define PINMUX_GPIO38__FUNC_CLKM2 (MTK_PIN_NO(38) | 2) +#define PINMUX_GPIO38__FUNC_DBG_MON_A21 (MTK_PIN_NO(38) | 7) +#define PINMUX_GPIO38__FUNC_IOBIST38 (MTK_PIN_NO(38) | 8) + +#define PINMUX_GPIO39__FUNC_GPIO39 (MTK_PIN_NO(39) | 0) +#define PINMUX_GPIO39__FUNC_CMMCLK3 (MTK_PIN_NO(39) | 1) +#define PINMUX_GPIO39__FUNC_CLKM3 (MTK_PIN_NO(39) | 2) +#define PINMUX_GPIO39__FUNC_DBG_MON_A22 (MTK_PIN_NO(39) | 7) +#define PINMUX_GPIO39__FUNC_IOBIST39 (MTK_PIN_NO(39) | 8) + +#define PINMUX_GPIO40__FUNC_GPIO40 (MTK_PIN_NO(40) | 0) +#define PINMUX_GPIO40__FUNC_I2SIN1_MCK (MTK_PIN_NO(40) | 1) +#define PINMUX_GPIO40__FUNC_IDDIG (MTK_PIN_NO(40) | 2) +#define PINMUX_GPIO40__FUNC_IRRX_IN (MTK_PIN_NO(40) | 3) +#define PINMUX_GPIO40__FUNC_GPS_PPS (MTK_PIN_NO(40) | 4) +#define PINMUX_GPIO40__FUNC_ANT_SEL8 (MTK_PIN_NO(40) | 6) +#define PINMUX_GPIO40__FUNC_IOBIST40 (MTK_PIN_NO(40) | 8) + +#define PINMUX_GPIO41__FUNC_GPIO41 (MTK_PIN_NO(41) | 0) +#define PINMUX_GPIO41__FUNC_I2SIN1_BCK (MTK_PIN_NO(41) | 1) +#define PINMUX_GPIO41__FUNC_CONN_WF_MCU_AICE_TMSC (MTK_PIN_NO(41) | 4) +#define PINMUX_GPIO41__FUNC_ANT_SEL9 (MTK_PIN_NO(41) | 6) +#define PINMUX_GPIO41__FUNC_IOBIST41 (MTK_PIN_NO(41) | 8) + +#define PINMUX_GPIO42__FUNC_GPIO42 (MTK_PIN_NO(42) | 0) +#define PINMUX_GPIO42__FUNC_I2SIN1_LRCK (MTK_PIN_NO(42) | 1) +#define PINMUX_GPIO42__FUNC_CONN_WF_MCU_AICE_TCKC (MTK_PIN_NO(42) | 4) +#define PINMUX_GPIO42__FUNC_ANT_SEL10 (MTK_PIN_NO(42) | 6) +#define PINMUX_GPIO42__FUNC_IOBIST42 (MTK_PIN_NO(42) | 8) + +#define PINMUX_GPIO43__FUNC_GPIO43 (MTK_PIN_NO(43) | 0) +#define PINMUX_GPIO43__FUNC_I2SOUT1_DO (MTK_PIN_NO(43) | 1) +#define PINMUX_GPIO43__FUNC_CONN_BGF_MCU_AICE_TMSC (MTK_PIN_NO(43) | 4) +#define PINMUX_GPIO43__FUNC_ANT_SEL11 (MTK_PIN_NO(43) | 6) +#define PINMUX_GPIO43__FUNC_IOBIST43 (MTK_PIN_NO(43) | 8) + +#define PINMUX_GPIO44__FUNC_GPIO44 (MTK_PIN_NO(44) | 0) +#define PINMUX_GPIO44__FUNC_I2SIN1_DI (MTK_PIN_NO(44) | 1) +#define PINMUX_GPIO44__FUNC_CONN_BGF_MCU_AICE_TCKC (MTK_PIN_NO(44) | 4) +#define PINMUX_GPIO44__FUNC_ANT_SEL12 (MTK_PIN_NO(44) | 6) +#define PINMUX_GPIO44__FUNC_IOBIST44 (MTK_PIN_NO(44) | 8) + +#define PINMUX_GPIO45__FUNC_GPIO45 (MTK_PIN_NO(45) | 0) +#define PINMUX_GPIO45__FUNC_I2SIN2_BCK (MTK_PIN_NO(45) | 1) +#define PINMUX_GPIO45__FUNC_SCL11 (MTK_PIN_NO(45) | 2) +#define PINMUX_GPIO45__FUNC_BPI_BUS10 (MTK_PIN_NO(45) | 3) +#define PINMUX_GPIO45__FUNC_MD_UCTS0 (MTK_PIN_NO(45) | 4) +#define PINMUX_GPIO45__FUNC_TP_UCTS1_VCORE (MTK_PIN_NO(45) | 5) +#define PINMUX_GPIO45__FUNC_HFRP_UCTS1 (MTK_PIN_NO(45) | 6) +#define PINMUX_GPIO45__FUNC_DBG_MON_B1 (MTK_PIN_NO(45) | 7) +#define PINMUX_GPIO45__FUNC_IOBIST45 (MTK_PIN_NO(45) | 8) + +#define PINMUX_GPIO46__FUNC_GPIO46 (MTK_PIN_NO(46) | 0) +#define PINMUX_GPIO46__FUNC_I2SIN2_LRCK (MTK_PIN_NO(46) | 1) +#define PINMUX_GPIO46__FUNC_SDA11 (MTK_PIN_NO(46) | 2) +#define PINMUX_GPIO46__FUNC_BPI_BUS11 (MTK_PIN_NO(46) | 3) +#define PINMUX_GPIO46__FUNC_MD_URTS0 (MTK_PIN_NO(46) | 4) +#define PINMUX_GPIO46__FUNC_TP_URTS1_VCORE (MTK_PIN_NO(46) | 5) +#define PINMUX_GPIO46__FUNC_HFRP_URTS1 (MTK_PIN_NO(46) | 6) +#define PINMUX_GPIO46__FUNC_DBG_MON_B2 (MTK_PIN_NO(46) | 7) +#define PINMUX_GPIO46__FUNC_IOBIST46 (MTK_PIN_NO(46) | 8) + +#define PINMUX_GPIO47__FUNC_GPIO47 (MTK_PIN_NO(47) | 0) +#define PINMUX_GPIO47__FUNC_I2SOUT2_DO (MTK_PIN_NO(47) | 1) +#define PINMUX_GPIO47__FUNC_SCL1 (MTK_PIN_NO(47) | 2) +#define PINMUX_GPIO47__FUNC_BPI_BUS12 (MTK_PIN_NO(47) | 3) +#define PINMUX_GPIO47__FUNC_MD_UCTS1 (MTK_PIN_NO(47) | 4) +#define PINMUX_GPIO47__FUNC_TP_UCTS2_VCORE (MTK_PIN_NO(47) | 5) +#define PINMUX_GPIO47__FUNC_UCTS2 (MTK_PIN_NO(47) | 6) +#define PINMUX_GPIO47__FUNC_DBG_MON_B3 (MTK_PIN_NO(47) | 7) +#define PINMUX_GPIO47__FUNC_IOBIST47 (MTK_PIN_NO(47) | 8) + +#define PINMUX_GPIO48__FUNC_GPIO48 (MTK_PIN_NO(48) | 0) +#define PINMUX_GPIO48__FUNC_I2SIN2_DI (MTK_PIN_NO(48) | 1) +#define PINMUX_GPIO48__FUNC_SDA1 (MTK_PIN_NO(48) | 2) +#define PINMUX_GPIO48__FUNC_BPI_BUS13 (MTK_PIN_NO(48) | 3) +#define PINMUX_GPIO48__FUNC_MD_URTS1 (MTK_PIN_NO(48) | 4) +#define PINMUX_GPIO48__FUNC_TP_URTS2_VCORE (MTK_PIN_NO(48) | 5) +#define PINMUX_GPIO48__FUNC_URTS2 (MTK_PIN_NO(48) | 6) +#define PINMUX_GPIO48__FUNC_DBG_MON_B4 (MTK_PIN_NO(48) | 7) +#define PINMUX_GPIO48__FUNC_IOBIST48 (MTK_PIN_NO(48) | 8) + +#define PINMUX_GPIO49__FUNC_GPIO49 (MTK_PIN_NO(49) | 0) +#define PINMUX_GPIO49__FUNC_UTXD0 (MTK_PIN_NO(49) | 1) +#define PINMUX_GPIO49__FUNC_MBISTREADEN_TRIGGER (MTK_PIN_NO(49) | 2) +#define PINMUX_GPIO49__FUNC_MD_UTXD1 (MTK_PIN_NO(49) | 3) +#define PINMUX_GPIO49__FUNC_HFRP_UTXD1 (MTK_PIN_NO(49) | 4) +#define PINMUX_GPIO49__FUNC_MD32_0_TXD (MTK_PIN_NO(49) | 5) +#define PINMUX_GPIO49__FUNC_PTA_TXD (MTK_PIN_NO(49) | 6) +#define PINMUX_GPIO49__FUNC_IOBIST49 (MTK_PIN_NO(49) | 8) + +#define PINMUX_GPIO50__FUNC_GPIO50 (MTK_PIN_NO(50) | 0) +#define PINMUX_GPIO50__FUNC_URXD0 (MTK_PIN_NO(50) | 1) +#define PINMUX_GPIO50__FUNC_MBISTWRITEEN_TRIGGER (MTK_PIN_NO(50) | 2) +#define PINMUX_GPIO50__FUNC_MD_URXD1 (MTK_PIN_NO(50) | 3) +#define PINMUX_GPIO50__FUNC_HFRP_URXD1 (MTK_PIN_NO(50) | 4) +#define PINMUX_GPIO50__FUNC_MD32_0_RXD (MTK_PIN_NO(50) | 5) +#define PINMUX_GPIO50__FUNC_PTA_RXD (MTK_PIN_NO(50) | 6) +#define PINMUX_GPIO50__FUNC_IOBIST50 (MTK_PIN_NO(50) | 8) + +#define PINMUX_GPIO51__FUNC_GPIO51 (MTK_PIN_NO(51) | 0) +#define PINMUX_GPIO51__FUNC_UTXD1 (MTK_PIN_NO(51) | 1) +#define PINMUX_GPIO51__FUNC_TP_UTXD1_VLP (MTK_PIN_NO(51) | 2) +#define PINMUX_GPIO51__FUNC_TP_UTXD2_VLP (MTK_PIN_NO(51) | 3) +#define PINMUX_GPIO51__FUNC_CONN_BGF_UART0_TXD (MTK_PIN_NO(51) | 4) +#define PINMUX_GPIO51__FUNC_SSPM_UTXD_AO_VLP (MTK_PIN_NO(51) | 5) +#define PINMUX_GPIO51__FUNC_MD_MCIF_UTXD0 (MTK_PIN_NO(51) | 6) +#define PINMUX_GPIO51__FUNC_MD_UTXD0 (MTK_PIN_NO(51) | 7) +#define PINMUX_GPIO51__FUNC_IOBIST51 (MTK_PIN_NO(51) | 8) + +#define PINMUX_GPIO52__FUNC_GPIO52 (MTK_PIN_NO(52) | 0) +#define PINMUX_GPIO52__FUNC_URXD1 (MTK_PIN_NO(52) | 1) +#define PINMUX_GPIO52__FUNC_TP_URXD1_VLP (MTK_PIN_NO(52) | 2) +#define PINMUX_GPIO52__FUNC_TP_URXD2_VLP (MTK_PIN_NO(52) | 3) +#define PINMUX_GPIO52__FUNC_CONN_BGF_UART0_RXD (MTK_PIN_NO(52) | 4) +#define PINMUX_GPIO52__FUNC_SSPM_URXD_AO_VLP (MTK_PIN_NO(52) | 5) +#define PINMUX_GPIO52__FUNC_MD_MCIF_URXD0 (MTK_PIN_NO(52) | 6) +#define PINMUX_GPIO52__FUNC_MD_URXD0 (MTK_PIN_NO(52) | 7) +#define PINMUX_GPIO52__FUNC_IOBIST52 (MTK_PIN_NO(52) | 8) + +#define PINMUX_GPIO53__FUNC_GPIO53 (MTK_PIN_NO(53) | 0) +#define PINMUX_GPIO53__FUNC_JTRSTN_SEL1_VCORE (MTK_PIN_NO(53) | 1) +#define PINMUX_GPIO53__FUNC_SPM_JTAG_TRSTN_VCORE (MTK_PIN_NO(53) | 2) +#define PINMUX_GPIO53__FUNC_IOBIST53 (MTK_PIN_NO(53) | 8) + +#define PINMUX_GPIO54__FUNC_GPIO54 (MTK_PIN_NO(54) | 0) +#define PINMUX_GPIO54__FUNC_JTCK_SEL1_VCORE (MTK_PIN_NO(54) | 1) +#define PINMUX_GPIO54__FUNC_SPM_JTAG_TCK_VCORE (MTK_PIN_NO(54) | 2) +#define PINMUX_GPIO54__FUNC_IOBIST54 (MTK_PIN_NO(54) | 8) + +#define PINMUX_GPIO55__FUNC_GPIO55 (MTK_PIN_NO(55) | 0) +#define PINMUX_GPIO55__FUNC_JTMS_SEL1_VCORE (MTK_PIN_NO(55) | 1) +#define PINMUX_GPIO55__FUNC_SPM_JTAG_TMS_VCORE (MTK_PIN_NO(55) | 2) +#define PINMUX_GPIO55__FUNC_IOBIST55 (MTK_PIN_NO(55) | 8) + +#define PINMUX_GPIO56__FUNC_GPIO56 (MTK_PIN_NO(56) | 0) +#define PINMUX_GPIO56__FUNC_JTDI_SEL1_VCORE (MTK_PIN_NO(56) | 1) +#define PINMUX_GPIO56__FUNC_SPM_JTAG_TDI_VCORE (MTK_PIN_NO(56) | 2) +#define PINMUX_GPIO56__FUNC_IOBIST56 (MTK_PIN_NO(56) | 8) + +#define PINMUX_GPIO57__FUNC_GPIO57 (MTK_PIN_NO(57) | 0) +#define PINMUX_GPIO57__FUNC_JTDO_SEL1_VCORE (MTK_PIN_NO(57) | 1) +#define PINMUX_GPIO57__FUNC_SPM_JTAG_TDO_VCORE (MTK_PIN_NO(57) | 2) +#define PINMUX_GPIO57__FUNC_IOBIST57 (MTK_PIN_NO(57) | 8) + +#define PINMUX_GPIO58__FUNC_GPIO58 (MTK_PIN_NO(58) | 0) +#define PINMUX_GPIO58__FUNC_SPI4_CLK (MTK_PIN_NO(58) | 1) +#define PINMUX_GPIO58__FUNC_MD_UTXD0 (MTK_PIN_NO(58) | 2) +#define PINMUX_GPIO58__FUNC_UTXD2 (MTK_PIN_NO(58) | 3) +#define PINMUX_GPIO58__FUNC_TP_UTXD1_VCORE (MTK_PIN_NO(58) | 4) +#define PINMUX_GPIO58__FUNC_MBISTREADEN_TRIGGER (MTK_PIN_NO(58) | 5) +#define PINMUX_GPIO58__FUNC_EXTIF0_ACT (MTK_PIN_NO(58) | 6) +#define PINMUX_GPIO58__FUNC_DAP_SONIC_SWCK (MTK_PIN_NO(58) | 7) +#define PINMUX_GPIO58__FUNC_IOBIST58 (MTK_PIN_NO(58) | 8) + +#define PINMUX_GPIO59__FUNC_GPIO59 (MTK_PIN_NO(59) | 0) +#define PINMUX_GPIO59__FUNC_SPI4_CSB (MTK_PIN_NO(59) | 1) +#define PINMUX_GPIO59__FUNC_MD_URXD0 (MTK_PIN_NO(59) | 2) +#define PINMUX_GPIO59__FUNC_URXD2 (MTK_PIN_NO(59) | 3) +#define PINMUX_GPIO59__FUNC_TP_URXD1_VCORE (MTK_PIN_NO(59) | 4) +#define PINMUX_GPIO59__FUNC_MBISTWRITEEN_TRIGGER (MTK_PIN_NO(59) | 5) +#define PINMUX_GPIO59__FUNC_EXTIF0_PRI (MTK_PIN_NO(59) | 6) +#define PINMUX_GPIO59__FUNC_DAP_SONIC_SWD (MTK_PIN_NO(59) | 7) +#define PINMUX_GPIO59__FUNC_IOBIST59 (MTK_PIN_NO(59) | 8) + +#define PINMUX_GPIO60__FUNC_GPIO60 (MTK_PIN_NO(60) | 0) +#define PINMUX_GPIO60__FUNC_SPI4_MO (MTK_PIN_NO(60) | 1) +#define PINMUX_GPIO60__FUNC_EXTIF0_GNT_B (MTK_PIN_NO(60) | 6) +#define PINMUX_GPIO60__FUNC_DAP_MD32_SWCK (MTK_PIN_NO(60) | 7) +#define PINMUX_GPIO60__FUNC_IOBIST60 (MTK_PIN_NO(60) | 8) + +#define PINMUX_GPIO61__FUNC_GPIO61 (MTK_PIN_NO(61) | 0) +#define PINMUX_GPIO61__FUNC_SPI4_MI (MTK_PIN_NO(61) | 1) +#define PINMUX_GPIO61__FUNC_DAP_MD32_SWD (MTK_PIN_NO(61) | 7) +#define PINMUX_GPIO61__FUNC_IOBIST61 (MTK_PIN_NO(61) | 8) + +#define PINMUX_GPIO62__FUNC_GPIO62 (MTK_PIN_NO(62) | 0) +#define PINMUX_GPIO62__FUNC_SCP_SPI1_CK (MTK_PIN_NO(62) | 1) +#define PINMUX_GPIO62__FUNC_SPI1_CLK (MTK_PIN_NO(62) | 2) +#define PINMUX_GPIO62__FUNC_TP_UTXD1_VLP (MTK_PIN_NO(62) | 3) +#define PINMUX_GPIO62__FUNC_TP_GPIO0_AO (MTK_PIN_NO(62) | 5) +#define PINMUX_GPIO62__FUNC_UTXD0 (MTK_PIN_NO(62) | 6) +#define PINMUX_GPIO62__FUNC_DBG_MON_A25 (MTK_PIN_NO(62) | 7) +#define PINMUX_GPIO62__FUNC_IOBIST62 (MTK_PIN_NO(62) | 8) + +#define PINMUX_GPIO63__FUNC_GPIO63 (MTK_PIN_NO(63) | 0) +#define PINMUX_GPIO63__FUNC_SCP_SPI1_CS (MTK_PIN_NO(63) | 1) +#define PINMUX_GPIO63__FUNC_SPI1_CSB (MTK_PIN_NO(63) | 2) +#define PINMUX_GPIO63__FUNC_TP_URXD1_VLP (MTK_PIN_NO(63) | 3) +#define PINMUX_GPIO63__FUNC_TP_GPIO1_AO (MTK_PIN_NO(63) | 5) +#define PINMUX_GPIO63__FUNC_URXD0 (MTK_PIN_NO(63) | 6) +#define PINMUX_GPIO63__FUNC_DBG_MON_A26 (MTK_PIN_NO(63) | 7) +#define PINMUX_GPIO63__FUNC_IOBIST63 (MTK_PIN_NO(63) | 8) + +#define PINMUX_GPIO64__FUNC_GPIO64 (MTK_PIN_NO(64) | 0) +#define PINMUX_GPIO64__FUNC_SCP_SPI1_MO (MTK_PIN_NO(64) | 1) +#define PINMUX_GPIO64__FUNC_SPI1_MO (MTK_PIN_NO(64) | 2) +#define PINMUX_GPIO64__FUNC_TP_GPIO2_AO (MTK_PIN_NO(64) | 5) +#define PINMUX_GPIO64__FUNC_DBG_MON_A9 (MTK_PIN_NO(64) | 7) +#define PINMUX_GPIO64__FUNC_IOBIST64 (MTK_PIN_NO(64) | 8) + +#define PINMUX_GPIO65__FUNC_GPIO65 (MTK_PIN_NO(65) | 0) +#define PINMUX_GPIO65__FUNC_SCP_SPI1_MI (MTK_PIN_NO(65) | 1) +#define PINMUX_GPIO65__FUNC_SPI1_MI (MTK_PIN_NO(65) | 2) +#define PINMUX_GPIO65__FUNC_TP_GPIO3_AO (MTK_PIN_NO(65) | 5) +#define PINMUX_GPIO65__FUNC_IOBIST65 (MTK_PIN_NO(65) | 8) + +#define PINMUX_GPIO66__FUNC_GPIO66 (MTK_PIN_NO(66) | 0) +#define PINMUX_GPIO66__FUNC_SCP_SPI2_CK (MTK_PIN_NO(66) | 1) +#define PINMUX_GPIO66__FUNC_SPI2_CLK (MTK_PIN_NO(66) | 2) +#define PINMUX_GPIO66__FUNC_TP_GPIO4_AO (MTK_PIN_NO(66) | 5) +#define PINMUX_GPIO66__FUNC_UTXD1 (MTK_PIN_NO(66) | 6) +#define PINMUX_GPIO66__FUNC_DBG_MON_B13 (MTK_PIN_NO(66) | 7) +#define PINMUX_GPIO66__FUNC_IOBIST66 (MTK_PIN_NO(66) | 8) + +#define PINMUX_GPIO67__FUNC_GPIO67 (MTK_PIN_NO(67) | 0) +#define PINMUX_GPIO67__FUNC_SCP_SPI2_CS (MTK_PIN_NO(67) | 1) +#define PINMUX_GPIO67__FUNC_SPI2_CSB (MTK_PIN_NO(67) | 2) +#define PINMUX_GPIO67__FUNC_TP_GPIO5_AO (MTK_PIN_NO(67) | 5) +#define PINMUX_GPIO67__FUNC_URXD1 (MTK_PIN_NO(67) | 6) +#define PINMUX_GPIO67__FUNC_DBG_MON_B14 (MTK_PIN_NO(67) | 7) +#define PINMUX_GPIO67__FUNC_IOBIST67 (MTK_PIN_NO(67) | 8) + +#define PINMUX_GPIO68__FUNC_GPIO68 (MTK_PIN_NO(68) | 0) +#define PINMUX_GPIO68__FUNC_SCP_SPI2_MO (MTK_PIN_NO(68) | 1) +#define PINMUX_GPIO68__FUNC_SPI2_MO (MTK_PIN_NO(68) | 2) +#define PINMUX_GPIO68__FUNC_TP_GPIO6_AO (MTK_PIN_NO(68) | 5) +#define PINMUX_GPIO68__FUNC_DBG_MON_B15 (MTK_PIN_NO(68) | 7) +#define PINMUX_GPIO68__FUNC_IOBIST68 (MTK_PIN_NO(68) | 8) + +#define PINMUX_GPIO69__FUNC_GPIO69 (MTK_PIN_NO(69) | 0) +#define PINMUX_GPIO69__FUNC_SCP_SPI2_MI (MTK_PIN_NO(69) | 1) +#define PINMUX_GPIO69__FUNC_SPI2_MI (MTK_PIN_NO(69) | 2) +#define PINMUX_GPIO69__FUNC_TP_GPIO7_AO (MTK_PIN_NO(69) | 5) +#define PINMUX_GPIO69__FUNC_DBG_MON_B16 (MTK_PIN_NO(69) | 7) +#define PINMUX_GPIO69__FUNC_IOBIST69 (MTK_PIN_NO(69) | 8) + +#define PINMUX_GPIO70__FUNC_GPIO70 (MTK_PIN_NO(70) | 0) +#define PINMUX_GPIO70__FUNC_SCP_SPI3_CK (MTK_PIN_NO(70) | 1) +#define PINMUX_GPIO70__FUNC_SPI3_CLK (MTK_PIN_NO(70) | 2) +#define PINMUX_GPIO70__FUNC_MD_INT4 (MTK_PIN_NO(70) | 3) +#define PINMUX_GPIO70__FUNC_TP_GPIO8_AO (MTK_PIN_NO(70) | 5) +#define PINMUX_GPIO70__FUNC_DBG_MON_B17 (MTK_PIN_NO(70) | 7) +#define PINMUX_GPIO70__FUNC_IOBIST70 (MTK_PIN_NO(70) | 8) + +#define PINMUX_GPIO71__FUNC_GPIO71 (MTK_PIN_NO(71) | 0) +#define PINMUX_GPIO71__FUNC_SCP_SPI3_CS (MTK_PIN_NO(71) | 1) +#define PINMUX_GPIO71__FUNC_SPI3_CSB (MTK_PIN_NO(71) | 2) +#define PINMUX_GPIO71__FUNC_MD_INT3 (MTK_PIN_NO(71) | 3) +#define PINMUX_GPIO71__FUNC_TP_GPIO9_AO (MTK_PIN_NO(71) | 5) +#define PINMUX_GPIO71__FUNC_DBG_MON_B18 (MTK_PIN_NO(71) | 7) +#define PINMUX_GPIO71__FUNC_IOBIST71 (MTK_PIN_NO(71) | 8) + +#define PINMUX_GPIO72__FUNC_GPIO72 (MTK_PIN_NO(72) | 0) +#define PINMUX_GPIO72__FUNC_SCP_SPI3_MO (MTK_PIN_NO(72) | 1) +#define PINMUX_GPIO72__FUNC_SPI3_MO (MTK_PIN_NO(72) | 2) +#define PINMUX_GPIO72__FUNC_TP_GPIO10_AO (MTK_PIN_NO(72) | 5) +#define PINMUX_GPIO72__FUNC_DBG_MON_B19 (MTK_PIN_NO(72) | 7) +#define PINMUX_GPIO72__FUNC_IOBIST72 (MTK_PIN_NO(72) | 8) + +#define PINMUX_GPIO73__FUNC_GPIO73 (MTK_PIN_NO(73) | 0) +#define PINMUX_GPIO73__FUNC_SCP_SPI3_MI (MTK_PIN_NO(73) | 1) +#define PINMUX_GPIO73__FUNC_SPI3_MI (MTK_PIN_NO(73) | 2) +#define PINMUX_GPIO73__FUNC_TP_GPIO11_AO (MTK_PIN_NO(73) | 5) +#define PINMUX_GPIO73__FUNC_DBG_MON_B20 (MTK_PIN_NO(73) | 7) +#define PINMUX_GPIO73__FUNC_IOBIST73 (MTK_PIN_NO(73) | 8) + +#define PINMUX_GPIO74__FUNC_GPIO74 (MTK_PIN_NO(74) | 0) +#define PINMUX_GPIO74__FUNC_SCP_SPI0_CK (MTK_PIN_NO(74) | 1) +#define PINMUX_GPIO74__FUNC_SPI0_CLK (MTK_PIN_NO(74) | 2) +#define PINMUX_GPIO74__FUNC_MD_INT0 (MTK_PIN_NO(74) | 3) +#define PINMUX_GPIO74__FUNC_BPI_BUS14 (MTK_PIN_NO(74) | 4) +#define PINMUX_GPIO74__FUNC_TP_GPIO12_AO (MTK_PIN_NO(74) | 5) +#define PINMUX_GPIO74__FUNC_DBG_MON_B5 (MTK_PIN_NO(74) | 7) +#define PINMUX_GPIO74__FUNC_IOBIST74 (MTK_PIN_NO(74) | 8) + +#define PINMUX_GPIO75__FUNC_GPIO75 (MTK_PIN_NO(75) | 0) +#define PINMUX_GPIO75__FUNC_SCP_SPI0_CS (MTK_PIN_NO(75) | 1) +#define PINMUX_GPIO75__FUNC_SPI0_CSB (MTK_PIN_NO(75) | 2) +#define PINMUX_GPIO75__FUNC_BPI_BUS15 (MTK_PIN_NO(75) | 4) +#define PINMUX_GPIO75__FUNC_TP_GPIO13_AO (MTK_PIN_NO(75) | 5) +#define PINMUX_GPIO75__FUNC_DBG_MON_B6 (MTK_PIN_NO(75) | 7) +#define PINMUX_GPIO75__FUNC_IOBIST75 (MTK_PIN_NO(75) | 8) + +#define PINMUX_GPIO76__FUNC_GPIO76 (MTK_PIN_NO(76) | 0) +#define PINMUX_GPIO76__FUNC_SCP_SPI0_MO (MTK_PIN_NO(76) | 1) +#define PINMUX_GPIO76__FUNC_SPI0_MO (MTK_PIN_NO(76) | 2) +#define PINMUX_GPIO76__FUNC_BPI_BUS16 (MTK_PIN_NO(76) | 4) +#define PINMUX_GPIO76__FUNC_TP_GPIO14_AO (MTK_PIN_NO(76) | 5) +#define PINMUX_GPIO76__FUNC_DBG_MON_B7 (MTK_PIN_NO(76) | 7) +#define PINMUX_GPIO76__FUNC_IOBIST76 (MTK_PIN_NO(76) | 8) + +#define PINMUX_GPIO77__FUNC_GPIO77 (MTK_PIN_NO(77) | 0) +#define PINMUX_GPIO77__FUNC_SCP_SPI0_MI (MTK_PIN_NO(77) | 1) +#define PINMUX_GPIO77__FUNC_SPI0_MI (MTK_PIN_NO(77) | 2) +#define PINMUX_GPIO77__FUNC_BPI_BUS17 (MTK_PIN_NO(77) | 4) +#define PINMUX_GPIO77__FUNC_TP_GPIO15_AO (MTK_PIN_NO(77) | 5) +#define PINMUX_GPIO77__FUNC_DBG_MON_B8 (MTK_PIN_NO(77) | 7) +#define PINMUX_GPIO77__FUNC_IOBIST77 (MTK_PIN_NO(77) | 8) + +#define PINMUX_GPIO78__FUNC_GPIO78 (MTK_PIN_NO(78) | 0) +#define PINMUX_GPIO78__FUNC_SPI5_CLK (MTK_PIN_NO(78) | 1) +#define PINMUX_GPIO78__FUNC_MD32_0_TXD (MTK_PIN_NO(78) | 2) +#define PINMUX_GPIO78__FUNC_PTA_TXD (MTK_PIN_NO(78) | 3) +#define PINMUX_GPIO78__FUNC_TP_UTXD2_VCORE (MTK_PIN_NO(78) | 4) +#define PINMUX_GPIO78__FUNC_SSPM_UTXD_AO_VCORE (MTK_PIN_NO(78) | 5) +#define PINMUX_GPIO78__FUNC_UTXD2 (MTK_PIN_NO(78) | 6) +#define PINMUX_GPIO78__FUNC_DBG_MON_B21 (MTK_PIN_NO(78) | 7) +#define PINMUX_GPIO78__FUNC_IOBIST78 (MTK_PIN_NO(78) | 8) + +#define PINMUX_GPIO79__FUNC_GPIO79 (MTK_PIN_NO(79) | 0) +#define PINMUX_GPIO79__FUNC_SPI5_CSB (MTK_PIN_NO(79) | 1) +#define PINMUX_GPIO79__FUNC_MD32_0_RXD (MTK_PIN_NO(79) | 2) +#define PINMUX_GPIO79__FUNC_PTA_RXD (MTK_PIN_NO(79) | 3) +#define PINMUX_GPIO79__FUNC_TP_URXD2_VCORE (MTK_PIN_NO(79) | 4) +#define PINMUX_GPIO79__FUNC_SSPM_URXD_AO_VCORE (MTK_PIN_NO(79) | 5) +#define PINMUX_GPIO79__FUNC_URXD2 (MTK_PIN_NO(79) | 6) +#define PINMUX_GPIO79__FUNC_DBG_MON_B22 (MTK_PIN_NO(79) | 7) +#define PINMUX_GPIO79__FUNC_IOBIST79 (MTK_PIN_NO(79) | 8) + +#define PINMUX_GPIO80__FUNC_GPIO80 (MTK_PIN_NO(80) | 0) +#define PINMUX_GPIO80__FUNC_SPI5_MO (MTK_PIN_NO(80) | 1) +#define PINMUX_GPIO80__FUNC_DBG_MON_B23 (MTK_PIN_NO(80) | 7) +#define PINMUX_GPIO80__FUNC_IOBIST80 (MTK_PIN_NO(80) | 8) + +#define PINMUX_GPIO81__FUNC_GPIO81 (MTK_PIN_NO(81) | 0) +#define PINMUX_GPIO81__FUNC_SPI5_MI (MTK_PIN_NO(81) | 1) +#define PINMUX_GPIO81__FUNC_DBG_MON_B24 (MTK_PIN_NO(81) | 7) +#define PINMUX_GPIO81__FUNC_IOBIST81 (MTK_PIN_NO(81) | 8) + +#define PINMUX_GPIO82__FUNC_GPIO82 (MTK_PIN_NO(82) | 0) +#define PINMUX_GPIO82__FUNC_MSDC1_CLK (MTK_PIN_NO(82) | 1) +#define PINMUX_GPIO82__FUNC_MFG_EB_JTAG_TCK (MTK_PIN_NO(82) | 2) +#define PINMUX_GPIO82__FUNC_UDI_TCK (MTK_PIN_NO(82) | 3) +#define PINMUX_GPIO82__FUNC_CONN_DSP_JCK (MTK_PIN_NO(82) | 4) +#define PINMUX_GPIO82__FUNC_IOBIST82 (MTK_PIN_NO(82) | 8) + +#define PINMUX_GPIO83__FUNC_GPIO83 (MTK_PIN_NO(83) | 0) +#define PINMUX_GPIO83__FUNC_MSDC1_CMD (MTK_PIN_NO(83) | 1) +#define PINMUX_GPIO83__FUNC_MFG_EB_JTAG_TMS (MTK_PIN_NO(83) | 2) +#define PINMUX_GPIO83__FUNC_UDI_TMS (MTK_PIN_NO(83) | 3) +#define PINMUX_GPIO83__FUNC_CONN_DSP_JMS (MTK_PIN_NO(83) | 4) +#define PINMUX_GPIO83__FUNC_TSFDC_VCO_RST (MTK_PIN_NO(83) | 6) +#define PINMUX_GPIO83__FUNC_IOBIST83 (MTK_PIN_NO(83) | 8) + +#define PINMUX_GPIO84__FUNC_GPIO84 (MTK_PIN_NO(84) | 0) +#define PINMUX_GPIO84__FUNC_MSDC1_DAT0 (MTK_PIN_NO(84) | 1) +#define PINMUX_GPIO84__FUNC_MFG_EB_JTAG_TDI (MTK_PIN_NO(84) | 2) +#define PINMUX_GPIO84__FUNC_UDI_TDI (MTK_PIN_NO(84) | 3) +#define PINMUX_GPIO84__FUNC_CONN_DSP_JDI (MTK_PIN_NO(84) | 4) +#define PINMUX_GPIO84__FUNC_TSFDC_TSSEL2 (MTK_PIN_NO(84) | 6) +#define PINMUX_GPIO84__FUNC_IOBIST84 (MTK_PIN_NO(84) | 8) + +#define PINMUX_GPIO85__FUNC_GPIO85 (MTK_PIN_NO(85) | 0) +#define PINMUX_GPIO85__FUNC_MSDC1_DAT1 (MTK_PIN_NO(85) | 1) +#define PINMUX_GPIO85__FUNC_MFG_EB_JTAG_TDO (MTK_PIN_NO(85) | 2) +#define PINMUX_GPIO85__FUNC_UDI_TDO (MTK_PIN_NO(85) | 3) +#define PINMUX_GPIO85__FUNC_CONN_DSP_JDO (MTK_PIN_NO(85) | 4) +#define PINMUX_GPIO85__FUNC_TSFDC_TSSEL1 (MTK_PIN_NO(85) | 6) +#define PINMUX_GPIO85__FUNC_IOBIST85 (MTK_PIN_NO(85) | 8) + +#define PINMUX_GPIO86__FUNC_GPIO86 (MTK_PIN_NO(86) | 0) +#define PINMUX_GPIO86__FUNC_MSDC1_DAT2 (MTK_PIN_NO(86) | 1) +#define PINMUX_GPIO86__FUNC_MFG_EB_JTAG_TRSTN (MTK_PIN_NO(86) | 2) +#define PINMUX_GPIO86__FUNC_UDI_NTRST (MTK_PIN_NO(86) | 3) +#define PINMUX_GPIO86__FUNC_TSFDC_TSSEL0 (MTK_PIN_NO(86) | 6) +#define PINMUX_GPIO86__FUNC_IOBIST86 (MTK_PIN_NO(86) | 8) + +#define PINMUX_GPIO87__FUNC_GPIO87 (MTK_PIN_NO(87) | 0) +#define PINMUX_GPIO87__FUNC_MSDC1_DAT3 (MTK_PIN_NO(87) | 1) +#define PINMUX_GPIO87__FUNC_IRRX_IN (MTK_PIN_NO(87) | 2) +#define PINMUX_GPIO87__FUNC_CONN_DSP_JINTP (MTK_PIN_NO(87) | 4) +#define PINMUX_GPIO87__FUNC_TSFDC_RCK_SELB (MTK_PIN_NO(87) | 6) +#define PINMUX_GPIO87__FUNC_IOBIST87 (MTK_PIN_NO(87) | 8) + +#define PINMUX_GPIO88__FUNC_GPIO88 (MTK_PIN_NO(88) | 0) +#define PINMUX_GPIO88__FUNC_MD1_SIM1_SCLK (MTK_PIN_NO(88) | 1) +#define PINMUX_GPIO88__FUNC_MD1_SIM2_SCLK (MTK_PIN_NO(88) | 2) +#define PINMUX_GPIO88__FUNC_CONN_DSP_L5_JINTP (MTK_PIN_NO(88) | 4) +#define PINMUX_GPIO88__FUNC_TSFDC_26M (MTK_PIN_NO(88) | 6) +#define PINMUX_GPIO88__FUNC_IOBIST88 (MTK_PIN_NO(88) | 8) + +#define PINMUX_GPIO89__FUNC_GPIO89 (MTK_PIN_NO(89) | 0) +#define PINMUX_GPIO89__FUNC_MD1_SIM1_SRST (MTK_PIN_NO(89) | 1) +#define PINMUX_GPIO89__FUNC_MD1_SIM2_SRST (MTK_PIN_NO(89) | 2) +#define PINMUX_GPIO89__FUNC_SPM_JTAG_TRSTN_VCORE (MTK_PIN_NO(89) | 3) +#define PINMUX_GPIO89__FUNC_MCUPM_JTAG_TRSTN (MTK_PIN_NO(89) | 5) +#define PINMUX_GPIO89__FUNC_TSFDC_SDO (MTK_PIN_NO(89) | 6) +#define PINMUX_GPIO89__FUNC_IOBIST89 (MTK_PIN_NO(89) | 8) + +#define PINMUX_GPIO90__FUNC_GPIO90 (MTK_PIN_NO(90) | 0) +#define PINMUX_GPIO90__FUNC_MD1_SIM1_SIO (MTK_PIN_NO(90) | 1) +#define PINMUX_GPIO90__FUNC_MD1_SIM2_SIO (MTK_PIN_NO(90) | 2) +#define PINMUX_GPIO90__FUNC_SPM_JTAG_TCK_VCORE (MTK_PIN_NO(90) | 3) +#define PINMUX_GPIO90__FUNC_CONN_DSP_L5_JCK (MTK_PIN_NO(90) | 4) +#define PINMUX_GPIO90__FUNC_MCUPM_JTAG_TCK (MTK_PIN_NO(90) | 5) +#define PINMUX_GPIO90__FUNC_TSFDC_FOUT (MTK_PIN_NO(90) | 6) +#define PINMUX_GPIO90__FUNC_IOBIST90 (MTK_PIN_NO(90) | 8) + +#define PINMUX_GPIO91__FUNC_GPIO91 (MTK_PIN_NO(91) | 0) +#define PINMUX_GPIO91__FUNC_MD1_SIM2_SCLK (MTK_PIN_NO(91) | 1) +#define PINMUX_GPIO91__FUNC_MD1_SIM1_SCLK (MTK_PIN_NO(91) | 2) +#define PINMUX_GPIO91__FUNC_SPM_JTAG_TMS_VCORE (MTK_PIN_NO(91) | 3) +#define PINMUX_GPIO91__FUNC_CONN_DSP_L5_JMS (MTK_PIN_NO(91) | 4) +#define PINMUX_GPIO91__FUNC_MCUPM_JTAG_TMS (MTK_PIN_NO(91) | 5) +#define PINMUX_GPIO91__FUNC_TSFDC_SCK (MTK_PIN_NO(91) | 6) +#define PINMUX_GPIO91__FUNC_IOBIST91 (MTK_PIN_NO(91) | 8) + +#define PINMUX_GPIO92__FUNC_GPIO92 (MTK_PIN_NO(92) | 0) +#define PINMUX_GPIO92__FUNC_MD1_SIM2_SRST (MTK_PIN_NO(92) | 1) +#define PINMUX_GPIO92__FUNC_MD1_SIM1_SRST (MTK_PIN_NO(92) | 2) +#define PINMUX_GPIO92__FUNC_SPM_JTAG_TDI_VCORE (MTK_PIN_NO(92) | 3) +#define PINMUX_GPIO92__FUNC_CONN_DSP_L5_JDI (MTK_PIN_NO(92) | 4) +#define PINMUX_GPIO92__FUNC_MCUPM_JTAG_TDI (MTK_PIN_NO(92) | 5) +#define PINMUX_GPIO92__FUNC_TSFDC_SDI (MTK_PIN_NO(92) | 6) +#define PINMUX_GPIO92__FUNC_IOBIST92 (MTK_PIN_NO(92) | 8) + +#define PINMUX_GPIO93__FUNC_GPIO93 (MTK_PIN_NO(93) | 0) +#define PINMUX_GPIO93__FUNC_MD1_SIM2_SIO (MTK_PIN_NO(93) | 1) +#define PINMUX_GPIO93__FUNC_MD1_SIM1_SIO (MTK_PIN_NO(93) | 2) +#define PINMUX_GPIO93__FUNC_SPM_JTAG_TDO_VCORE (MTK_PIN_NO(93) | 3) +#define PINMUX_GPIO93__FUNC_CONN_DSP_L5_JDO (MTK_PIN_NO(93) | 4) +#define PINMUX_GPIO93__FUNC_MCUPM_JTAG_TDO (MTK_PIN_NO(93) | 5) +#define PINMUX_GPIO93__FUNC_TSFDC_SCF (MTK_PIN_NO(93) | 6) +#define PINMUX_GPIO93__FUNC_IOBIST93 (MTK_PIN_NO(93) | 8) + +#define PINMUX_GPIO94__FUNC_GPIO94 (MTK_PIN_NO(94) | 0) +#define PINMUX_GPIO94__FUNC_MD_INT1_C2K_UIM0_HOT_PLUG (MTK_PIN_NO(94) | 1) +#define PINMUX_GPIO94__FUNC_MD_INT2_C2K_UIM1_HOT_PLUG (MTK_PIN_NO(94) | 2) +#define PINMUX_GPIO94__FUNC_SRCLKENAI0 (MTK_PIN_NO(94) | 3) +#define PINMUX_GPIO94__FUNC_MD_MCIF_UTXD0 (MTK_PIN_NO(94) | 6) +#define PINMUX_GPIO94__FUNC_IOBIST94 (MTK_PIN_NO(94) | 8) + +#define PINMUX_GPIO95__FUNC_GPIO95 (MTK_PIN_NO(95) | 0) +#define PINMUX_GPIO95__FUNC_MD_INT2_C2K_UIM1_HOT_PLUG (MTK_PIN_NO(95) | 1) +#define PINMUX_GPIO95__FUNC_MD_INT1_C2K_UIM0_HOT_PLUG (MTK_PIN_NO(95) | 2) +#define PINMUX_GPIO95__FUNC_SRCLKENAI1 (MTK_PIN_NO(95) | 3) +#define PINMUX_GPIO95__FUNC_SRCLKENA1 (MTK_PIN_NO(95) | 4) +#define PINMUX_GPIO95__FUNC_MD_MCIF_URXD0 (MTK_PIN_NO(95) | 6) +#define PINMUX_GPIO95__FUNC_IOBIST95 (MTK_PIN_NO(95) | 8) + +#define PINMUX_GPIO96__FUNC_GPIO96 (MTK_PIN_NO(96) | 0) +#define PINMUX_GPIO96__FUNC_DSI_TE (MTK_PIN_NO(96) | 1) +#define PINMUX_GPIO96__FUNC_DBG_MON_B25 (MTK_PIN_NO(96) | 7) +#define PINMUX_GPIO96__FUNC_IOBIST96 (MTK_PIN_NO(96) | 8) + +#define PINMUX_GPIO97__FUNC_GPIO97 (MTK_PIN_NO(97) | 0) +#define PINMUX_GPIO97__FUNC_LCM_RST (MTK_PIN_NO(97) | 1) +#define PINMUX_GPIO97__FUNC_DBG_MON_B26 (MTK_PIN_NO(97) | 7) +#define PINMUX_GPIO97__FUNC_IOBIST97 (MTK_PIN_NO(97) | 8) + +#define PINMUX_GPIO98__FUNC_GPIO98 (MTK_PIN_NO(98) | 0) +#define PINMUX_GPIO98__FUNC_DISP_PWM (MTK_PIN_NO(98) | 1) +#define PINMUX_GPIO98__FUNC_PWM_2 (MTK_PIN_NO(98) | 2) +#define PINMUX_GPIO98__FUNC_DBG_MON_B27 (MTK_PIN_NO(98) | 7) +#define PINMUX_GPIO98__FUNC_IOBIST98 (MTK_PIN_NO(98) | 8) + +#define PINMUX_GPIO99__FUNC_GPIO99 (MTK_PIN_NO(99) | 0) +#define PINMUX_GPIO99__FUNC_ANT_SEL0 (MTK_PIN_NO(99) | 1) +#define PINMUX_GPIO99__FUNC_CONN_BPI_BUS17_ANT0 (MTK_PIN_NO(99) | 2) +#define PINMUX_GPIO99__FUNC_GPS_L1_ELNA_EN (MTK_PIN_NO(99) | 3) +#define PINMUX_GPIO99__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(99) | 4) +#define PINMUX_GPIO99__FUNC_SCL6 (MTK_PIN_NO(99) | 5) +#define PINMUX_GPIO99__FUNC_IOBIST99 (MTK_PIN_NO(99) | 8) + +#define PINMUX_GPIO100__FUNC_GPIO100 (MTK_PIN_NO(100) | 0) +#define PINMUX_GPIO100__FUNC_ANT_SEL1 (MTK_PIN_NO(100) | 1) +#define PINMUX_GPIO100__FUNC_CONN_BPI_BUS18_ANT1 (MTK_PIN_NO(100) | 2) +#define PINMUX_GPIO100__FUNC_GPS_L5_ELNA_EN (MTK_PIN_NO(100) | 3) +#define PINMUX_GPIO100__FUNC_AGPS_SYNC (MTK_PIN_NO(100) | 4) +#define PINMUX_GPIO100__FUNC_SDA6 (MTK_PIN_NO(100) | 5) +#define PINMUX_GPIO100__FUNC_IOBIST100 (MTK_PIN_NO(100) | 8) + +#define PINMUX_GPIO101__FUNC_GPIO101 (MTK_PIN_NO(101) | 0) +#define PINMUX_GPIO101__FUNC_ANT_SEL2 (MTK_PIN_NO(101) | 1) +#define PINMUX_GPIO101__FUNC_CONN_BPI_BUS19_ANT2 (MTK_PIN_NO(101) | 2) +#define PINMUX_GPIO101__FUNC_UDI_NTRST (MTK_PIN_NO(101) | 3) +#define PINMUX_GPIO101__FUNC_CONN_WF_MCU_TRST_B (MTK_PIN_NO(101) | 4) +#define PINMUX_GPIO101__FUNC_IOBIST101 (MTK_PIN_NO(101) | 8) + +#define PINMUX_GPIO102__FUNC_GPIO102 (MTK_PIN_NO(102) | 0) +#define PINMUX_GPIO102__FUNC_ANT_SEL3 (MTK_PIN_NO(102) | 1) +#define PINMUX_GPIO102__FUNC_CONN_BPI_BUS20_ANT3 (MTK_PIN_NO(102) | 2) +#define PINMUX_GPIO102__FUNC_UDI_TCK (MTK_PIN_NO(102) | 3) +#define PINMUX_GPIO102__FUNC_CONN_WF_MCU_TCK (MTK_PIN_NO(102) | 4) +#define PINMUX_GPIO102__FUNC_IOBIST102 (MTK_PIN_NO(102) | 8) + +#define PINMUX_GPIO103__FUNC_GPIO103 (MTK_PIN_NO(103) | 0) +#define PINMUX_GPIO103__FUNC_ANT_SEL4 (MTK_PIN_NO(103) | 1) +#define PINMUX_GPIO103__FUNC_CONN_BPI_BUS21_ANT4 (MTK_PIN_NO(103) | 2) +#define PINMUX_GPIO103__FUNC_UDI_TMS (MTK_PIN_NO(103) | 3) +#define PINMUX_GPIO103__FUNC_CONN_WF_MCU_TMS (MTK_PIN_NO(103) | 4) +#define PINMUX_GPIO103__FUNC_IOBIST103 (MTK_PIN_NO(103) | 8) + +#define PINMUX_GPIO104__FUNC_GPIO104 (MTK_PIN_NO(104) | 0) +#define PINMUX_GPIO104__FUNC_ANT_SEL5 (MTK_PIN_NO(104) | 1) +#define PINMUX_GPIO104__FUNC_CONN_BPI_BUS16_OLAT5 (MTK_PIN_NO(104) | 2) +#define PINMUX_GPIO104__FUNC_UDI_TDI (MTK_PIN_NO(104) | 3) +#define PINMUX_GPIO104__FUNC_CONN_WF_MCU_TDI (MTK_PIN_NO(104) | 4) +#define PINMUX_GPIO104__FUNC_IOBIST104 (MTK_PIN_NO(104) | 8) + +#define PINMUX_GPIO105__FUNC_GPIO105 (MTK_PIN_NO(105) | 0) +#define PINMUX_GPIO105__FUNC_ANT_SEL6 (MTK_PIN_NO(105) | 1) +#define PINMUX_GPIO105__FUNC_CONN_TCXOENA_REQ (MTK_PIN_NO(105) | 2) +#define PINMUX_GPIO105__FUNC_UDI_TDO (MTK_PIN_NO(105) | 3) +#define PINMUX_GPIO105__FUNC_CONN_WF_MCU_TDO (MTK_PIN_NO(105) | 4) +#define PINMUX_GPIO105__FUNC_IOBIST105 (MTK_PIN_NO(105) | 8) + +#define PINMUX_GPIO106__FUNC_GPIO106 (MTK_PIN_NO(106) | 0) +#define PINMUX_GPIO106__FUNC_BPI_BUS0 (MTK_PIN_NO(106) | 1) +#define PINMUX_GPIO106__FUNC_CONN_BPI_BUS10 (MTK_PIN_NO(106) | 2) +#define PINMUX_GPIO106__FUNC_MFG_TSFDC_EN (MTK_PIN_NO(106) | 4) +#define PINMUX_GPIO106__FUNC_I2SOUT4_DATA0 (MTK_PIN_NO(106) | 5) +#define PINMUX_GPIO106__FUNC_ANT_SEL7 (MTK_PIN_NO(106) | 6) +#define PINMUX_GPIO106__FUNC_IOBIST106 (MTK_PIN_NO(106) | 8) + +#define PINMUX_GPIO107__FUNC_GPIO107 (MTK_PIN_NO(107) | 0) +#define PINMUX_GPIO107__FUNC_BPI_BUS1 (MTK_PIN_NO(107) | 1) +#define PINMUX_GPIO107__FUNC_CONN_BPI_BUS11_OLAT0 (MTK_PIN_NO(107) | 2) +#define PINMUX_GPIO107__FUNC_MFG_TSFDC_VCO_RST (MTK_PIN_NO(107) | 4) +#define PINMUX_GPIO107__FUNC_I2SOUT4_DATA1 (MTK_PIN_NO(107) | 5) +#define PINMUX_GPIO107__FUNC_ANT_SEL8 (MTK_PIN_NO(107) | 6) +#define PINMUX_GPIO107__FUNC_IOBIST107 (MTK_PIN_NO(107) | 8) + +#define PINMUX_GPIO108__FUNC_GPIO108 (MTK_PIN_NO(108) | 0) +#define PINMUX_GPIO108__FUNC_BPI_BUS2 (MTK_PIN_NO(108) | 1) +#define PINMUX_GPIO108__FUNC_CONN_BPI_BUS12_OLAT1 (MTK_PIN_NO(108) | 2) +#define PINMUX_GPIO108__FUNC_CONN_TCXOENA_REQ (MTK_PIN_NO(108) | 3) +#define PINMUX_GPIO108__FUNC_MFG_TSFDC_TSSEL2 (MTK_PIN_NO(108) | 4) +#define PINMUX_GPIO108__FUNC_I2SOUT4_DATA2 (MTK_PIN_NO(108) | 5) +#define PINMUX_GPIO108__FUNC_ANT_SEL9 (MTK_PIN_NO(108) | 6) +#define PINMUX_GPIO108__FUNC_IOBIST108 (MTK_PIN_NO(108) | 8) + +#define PINMUX_GPIO109__FUNC_GPIO109 (MTK_PIN_NO(109) | 0) +#define PINMUX_GPIO109__FUNC_BPI_BUS3 (MTK_PIN_NO(109) | 1) +#define PINMUX_GPIO109__FUNC_CONN_BPI_BUS13_OLAT2 (MTK_PIN_NO(109) | 2) +#define PINMUX_GPIO109__FUNC_MFG_TSFDC_TSSEL1 (MTK_PIN_NO(109) | 4) +#define PINMUX_GPIO109__FUNC_I2SOUT4_DATA3 (MTK_PIN_NO(109) | 5) +#define PINMUX_GPIO109__FUNC_ANT_SEL10 (MTK_PIN_NO(109) | 6) +#define PINMUX_GPIO109__FUNC_IOBIST109 (MTK_PIN_NO(109) | 8) + +#define PINMUX_GPIO110__FUNC_GPIO110 (MTK_PIN_NO(110) | 0) +#define PINMUX_GPIO110__FUNC_BPI_BUS4 (MTK_PIN_NO(110) | 1) +#define PINMUX_GPIO110__FUNC_CONN_BPI_BUS14_OLAT3 (MTK_PIN_NO(110) | 2) +#define PINMUX_GPIO110__FUNC_GPS_L1_ELNA_EN (MTK_PIN_NO(110) | 3) +#define PINMUX_GPIO110__FUNC_MFG_TSFDC_TSSEL0 (MTK_PIN_NO(110) | 4) +#define PINMUX_GPIO110__FUNC_I2SIN4_BCK (MTK_PIN_NO(110) | 5) +#define PINMUX_GPIO110__FUNC_ANT_SEL11 (MTK_PIN_NO(110) | 6) +#define PINMUX_GPIO110__FUNC_IOBIST110 (MTK_PIN_NO(110) | 8) + +#define PINMUX_GPIO111__FUNC_GPIO111 (MTK_PIN_NO(111) | 0) +#define PINMUX_GPIO111__FUNC_BPI_BUS5 (MTK_PIN_NO(111) | 1) +#define PINMUX_GPIO111__FUNC_CONN_BPI_BUS15_OLAT4 (MTK_PIN_NO(111) | 2) +#define PINMUX_GPIO111__FUNC_GPS_L5_ELNA_EN (MTK_PIN_NO(111) | 3) +#define PINMUX_GPIO111__FUNC_MFG_TSFDC_RCK_SELB (MTK_PIN_NO(111) | 4) +#define PINMUX_GPIO111__FUNC_I2SIN4_DATA0 (MTK_PIN_NO(111) | 5) +#define PINMUX_GPIO111__FUNC_ANT_SEL12 (MTK_PIN_NO(111) | 6) +#define PINMUX_GPIO111__FUNC_IOBIST111 (MTK_PIN_NO(111) | 8) + +#define PINMUX_GPIO112__FUNC_GPIO112 (MTK_PIN_NO(112) | 0) +#define PINMUX_GPIO112__FUNC_BPI_BUS6 (MTK_PIN_NO(112) | 1) +#define PINMUX_GPIO112__FUNC_CONN_BPI_BUS6 (MTK_PIN_NO(112) | 2) +#define PINMUX_GPIO112__FUNC_MIPI3_D_SDATA (MTK_PIN_NO(112) | 3) +#define PINMUX_GPIO112__FUNC_MFG_TSFDC_SDO (MTK_PIN_NO(112) | 4) +#define PINMUX_GPIO112__FUNC_I2SIN4_DATA1 (MTK_PIN_NO(112) | 5) +#define PINMUX_GPIO112__FUNC_ANT_SEL13 (MTK_PIN_NO(112) | 6) +#define PINMUX_GPIO112__FUNC_IOBIST112 (MTK_PIN_NO(112) | 8) + +#define PINMUX_GPIO113__FUNC_GPIO113 (MTK_PIN_NO(113) | 0) +#define PINMUX_GPIO113__FUNC_BPI_BUS7 (MTK_PIN_NO(113) | 1) +#define PINMUX_GPIO113__FUNC_CONN_BPI_BUS7 (MTK_PIN_NO(113) | 2) +#define PINMUX_GPIO113__FUNC_MIPI3_D_SCLK (MTK_PIN_NO(113) | 3) +#define PINMUX_GPIO113__FUNC_MFG_TSFDC_FOUT (MTK_PIN_NO(113) | 4) +#define PINMUX_GPIO113__FUNC_I2SIN4_DATA2 (MTK_PIN_NO(113) | 5) +#define PINMUX_GPIO113__FUNC_ANT_SEL14 (MTK_PIN_NO(113) | 6) +#define PINMUX_GPIO113__FUNC_IOBIST113 (MTK_PIN_NO(113) | 8) + +#define PINMUX_GPIO114__FUNC_GPIO114 (MTK_PIN_NO(114) | 0) +#define PINMUX_GPIO114__FUNC_BPI_BUS8 (MTK_PIN_NO(114) | 1) +#define PINMUX_GPIO114__FUNC_CONN_BPI_BUS8 (MTK_PIN_NO(114) | 2) +#define PINMUX_GPIO114__FUNC_MIPI4_D_SDATA (MTK_PIN_NO(114) | 3) +#define PINMUX_GPIO114__FUNC_SCL9 (MTK_PIN_NO(114) | 4) +#define PINMUX_GPIO114__FUNC_I2SIN4_DATA3 (MTK_PIN_NO(114) | 5) +#define PINMUX_GPIO114__FUNC_ANT_SEL15 (MTK_PIN_NO(114) | 6) +#define PINMUX_GPIO114__FUNC_IOBIST114 (MTK_PIN_NO(114) | 8) + +#define PINMUX_GPIO115__FUNC_GPIO115 (MTK_PIN_NO(115) | 0) +#define PINMUX_GPIO115__FUNC_BPI_BUS9 (MTK_PIN_NO(115) | 1) +#define PINMUX_GPIO115__FUNC_CONN_BPI_BUS9 (MTK_PIN_NO(115) | 2) +#define PINMUX_GPIO115__FUNC_MIPI4_D_SCLK (MTK_PIN_NO(115) | 3) +#define PINMUX_GPIO115__FUNC_SDA9 (MTK_PIN_NO(115) | 4) +#define PINMUX_GPIO115__FUNC_I2SIN4_LRCK (MTK_PIN_NO(115) | 5) +#define PINMUX_GPIO115__FUNC_ANT_SEL16 (MTK_PIN_NO(115) | 6) +#define PINMUX_GPIO115__FUNC_IOBIST115 (MTK_PIN_NO(115) | 8) + +#define PINMUX_GPIO116__FUNC_GPIO116 (MTK_PIN_NO(116) | 0) +#define PINMUX_GPIO116__FUNC_MD_UCNT_A_TGL (MTK_PIN_NO(116) | 1) +#define PINMUX_GPIO116__FUNC_IOBIST116 (MTK_PIN_NO(116) | 8) + +#define PINMUX_GPIO117__FUNC_GPIO117 (MTK_PIN_NO(117) | 0) +#define PINMUX_GPIO117__FUNC_DIGRF_IRQ (MTK_PIN_NO(117) | 1) +#define PINMUX_GPIO117__FUNC_IOBIST117 (MTK_PIN_NO(117) | 8) + +#define PINMUX_GPIO118__FUNC_GPIO118 (MTK_PIN_NO(118) | 0) +#define PINMUX_GPIO118__FUNC_IOBIST118 (MTK_PIN_NO(118) | 8) + +#define PINMUX_GPIO119__FUNC_GPIO119 (MTK_PIN_NO(119) | 0) +#define PINMUX_GPIO119__FUNC_AP_GOOD (MTK_PIN_NO(119) | 1) +#define PINMUX_GPIO119__FUNC_CONN_WIFI_TXD (MTK_PIN_NO(119) | 3) +#define PINMUX_GPIO119__FUNC_GPS_PPS (MTK_PIN_NO(119) | 4) +#define PINMUX_GPIO119__FUNC_PMSR_SMAP (MTK_PIN_NO(119) | 5) +#define PINMUX_GPIO119__FUNC_AGPS_SYNC (MTK_PIN_NO(119) | 6) +#define PINMUX_GPIO119__FUNC_IOBIST119 (MTK_PIN_NO(119) | 8) + +#define PINMUX_GPIO120__FUNC_GPIO120 (MTK_PIN_NO(120) | 0) +#define PINMUX_GPIO120__FUNC_KPCOL0_VLP (MTK_PIN_NO(120) | 1) +#define PINMUX_GPIO120__FUNC_IOBIST120 (MTK_PIN_NO(120) | 8) + +#define PINMUX_GPIO121__FUNC_GPIO121 (MTK_PIN_NO(121) | 0) +#define PINMUX_GPIO121__FUNC_SRCLKENAI0 (MTK_PIN_NO(121) | 1) +#define PINMUX_GPIO121__FUNC_SRCLKENAI1 (MTK_PIN_NO(121) | 2) +#define PINMUX_GPIO121__FUNC_IOBIST121 (MTK_PIN_NO(121) | 8) + +#define PINMUX_GPIO122__FUNC_GPIO122 (MTK_PIN_NO(122) | 0) +#define PINMUX_GPIO122__FUNC_WATCHDOG (MTK_PIN_NO(122) | 1) +#define PINMUX_GPIO122__FUNC_IOBIST122 (MTK_PIN_NO(122) | 8) + +#define PINMUX_GPIO123__FUNC_GPIO123 (MTK_PIN_NO(123) | 0) +#define PINMUX_GPIO123__FUNC_IOBIST123 (MTK_PIN_NO(123) | 8) + +#define PINMUX_GPIO124__FUNC_GPIO124 (MTK_PIN_NO(124) | 0) +#define PINMUX_GPIO124__FUNC_SRCLKENA0 (MTK_PIN_NO(124) | 1) +#define PINMUX_GPIO124__FUNC_IOBIST124 (MTK_PIN_NO(124) | 8) + +#define PINMUX_GPIO125__FUNC_GPIO125 (MTK_PIN_NO(125) | 0) +#define PINMUX_GPIO125__FUNC_RTC32K_CK (MTK_PIN_NO(125) | 1) +#define PINMUX_GPIO125__FUNC_IOBIST125 (MTK_PIN_NO(125) | 8) + +#define PINMUX_GPIO126__FUNC_GPIO126 (MTK_PIN_NO(126) | 0) +#define PINMUX_GPIO126__FUNC_SPMI_M_SCL (MTK_PIN_NO(126) | 1) +#define PINMUX_GPIO126__FUNC_IOBIST126 (MTK_PIN_NO(126) | 8) + +#define PINMUX_GPIO127__FUNC_GPIO127 (MTK_PIN_NO(127) | 0) +#define PINMUX_GPIO127__FUNC_SPMI_M_SDA (MTK_PIN_NO(127) | 1) +#define PINMUX_GPIO127__FUNC_IOBIST127 (MTK_PIN_NO(127) | 8) + +#define PINMUX_GPIO128__FUNC_GPIO128 (MTK_PIN_NO(128) | 0) +#define PINMUX_GPIO128__FUNC_SPMI_P_SCL (MTK_PIN_NO(128) | 1) +#define PINMUX_GPIO128__FUNC_IOBIST128 (MTK_PIN_NO(128) | 8) + +#define PINMUX_GPIO129__FUNC_GPIO129 (MTK_PIN_NO(129) | 0) +#define PINMUX_GPIO129__FUNC_SPMI_P_SDA (MTK_PIN_NO(129) | 1) +#define PINMUX_GPIO129__FUNC_IOBIST129 (MTK_PIN_NO(129) | 8) + +#define PINMUX_GPIO130__FUNC_GPIO130 (MTK_PIN_NO(130) | 0) +#define PINMUX_GPIO130__FUNC_BPI_BUS13 (MTK_PIN_NO(130) | 3) +#define PINMUX_GPIO130__FUNC_IOBIST130 (MTK_PIN_NO(130) | 8) + +#define PINMUX_GPIO131__FUNC_GPIO131 (MTK_PIN_NO(131) | 0) +#define PINMUX_GPIO131__FUNC_SPI6_CLK (MTK_PIN_NO(131) | 1) +#define PINMUX_GPIO131__FUNC_KPROW2 (MTK_PIN_NO(131) | 2) +#define PINMUX_GPIO131__FUNC_BPI_BUS14 (MTK_PIN_NO(131) | 3) +#define PINMUX_GPIO131__FUNC_CONN_BT_TXD (MTK_PIN_NO(131) | 4) +#define PINMUX_GPIO131__FUNC_MD32_1_TXD (MTK_PIN_NO(131) | 5) +#define PINMUX_GPIO131__FUNC_PTA_TXD (MTK_PIN_NO(131) | 6) +#define PINMUX_GPIO131__FUNC_IOBIST131 (MTK_PIN_NO(131) | 8) + +#define PINMUX_GPIO132__FUNC_GPIO132 (MTK_PIN_NO(132) | 0) +#define PINMUX_GPIO132__FUNC_SPI6_CSB (MTK_PIN_NO(132) | 1) +#define PINMUX_GPIO132__FUNC_KPCOL2 (MTK_PIN_NO(132) | 2) +#define PINMUX_GPIO132__FUNC_BPI_BUS15 (MTK_PIN_NO(132) | 3) +#define PINMUX_GPIO132__FUNC_MD32_1_RXD (MTK_PIN_NO(132) | 5) +#define PINMUX_GPIO132__FUNC_PTA_RXD (MTK_PIN_NO(132) | 6) +#define PINMUX_GPIO132__FUNC_IOBIST132 (MTK_PIN_NO(132) | 8) + +#define PINMUX_GPIO133__FUNC_GPIO133 (MTK_PIN_NO(133) | 0) +#define PINMUX_GPIO133__FUNC_SPI6_MO (MTK_PIN_NO(133) | 1) +#define PINMUX_GPIO133__FUNC_CLKM0 (MTK_PIN_NO(133) | 2) +#define PINMUX_GPIO133__FUNC_BPI_BUS16 (MTK_PIN_NO(133) | 3) +#define PINMUX_GPIO133__FUNC_CMFLASH2 (MTK_PIN_NO(133) | 4) +#define PINMUX_GPIO133__FUNC_IOBIST133 (MTK_PIN_NO(133) | 8) + +#define PINMUX_GPIO134__FUNC_GPIO134 (MTK_PIN_NO(134) | 0) +#define PINMUX_GPIO134__FUNC_SPI6_MI (MTK_PIN_NO(134) | 1) +#define PINMUX_GPIO134__FUNC_CLKM1 (MTK_PIN_NO(134) | 2) +#define PINMUX_GPIO134__FUNC_BPI_BUS17 (MTK_PIN_NO(134) | 3) +#define PINMUX_GPIO134__FUNC_CMFLASH3 (MTK_PIN_NO(134) | 4) +#define PINMUX_GPIO134__FUNC_IOBIST134 (MTK_PIN_NO(134) | 8) + +#define PINMUX_GPIO135__FUNC_GPIO135 (MTK_PIN_NO(135) | 0) +#define PINMUX_GPIO135__FUNC_SCP_SCL1 (MTK_PIN_NO(135) | 1) +#define PINMUX_GPIO135__FUNC_CLKM2 (MTK_PIN_NO(135) | 2) +#define PINMUX_GPIO135__FUNC_SCP_DMIC_CLK (MTK_PIN_NO(135) | 3) +#define PINMUX_GPIO135__FUNC_DMIC_CLK (MTK_PIN_NO(135) | 4) +#define PINMUX_GPIO135__FUNC_TP_GPIO13_AO (MTK_PIN_NO(135) | 5) +#define PINMUX_GPIO135__FUNC_DBG_MON_A23 (MTK_PIN_NO(135) | 7) +#define PINMUX_GPIO135__FUNC_IOBIST135 (MTK_PIN_NO(135) | 8) + +#define PINMUX_GPIO136__FUNC_GPIO136 (MTK_PIN_NO(136) | 0) +#define PINMUX_GPIO136__FUNC_SCP_SDA1 (MTK_PIN_NO(136) | 1) +#define PINMUX_GPIO136__FUNC_CLKM3 (MTK_PIN_NO(136) | 2) +#define PINMUX_GPIO136__FUNC_SCP_DMIC_DAT (MTK_PIN_NO(136) | 3) +#define PINMUX_GPIO136__FUNC_DMIC_DAT (MTK_PIN_NO(136) | 4) +#define PINMUX_GPIO136__FUNC_TP_GPIO14_AO (MTK_PIN_NO(136) | 5) +#define PINMUX_GPIO136__FUNC_DBG_MON_A24 (MTK_PIN_NO(136) | 7) +#define PINMUX_GPIO136__FUNC_IOBIST136 (MTK_PIN_NO(136) | 8) + +#define PINMUX_GPIO137__FUNC_GPIO137 (MTK_PIN_NO(137) | 0) +#define PINMUX_GPIO137__FUNC_IRRX_IN (MTK_PIN_NO(137) | 2) +#define PINMUX_GPIO137__FUNC_MD_INT0 (MTK_PIN_NO(137) | 3) +#define PINMUX_GPIO137__FUNC_SPMI_M_TRIG_FLAG (MTK_PIN_NO(137) | 4) +#define PINMUX_GPIO137__FUNC_TP_GPIO15_AO (MTK_PIN_NO(137) | 5) +#define PINMUX_GPIO137__FUNC_UFS_MPHY_SCL (MTK_PIN_NO(137) | 6) +#define PINMUX_GPIO137__FUNC_IOBIST137 (MTK_PIN_NO(137) | 8) + +#define PINMUX_GPIO138__FUNC_GPIO138 (MTK_PIN_NO(138) | 0) +#define PINMUX_GPIO138__FUNC_PWM_VLP (MTK_PIN_NO(138) | 2) +#define PINMUX_GPIO138__FUNC_MD_INT3 (MTK_PIN_NO(138) | 3) +#define PINMUX_GPIO138__FUNC_TP_GPIO0_AO (MTK_PIN_NO(138) | 5) +#define PINMUX_GPIO138__FUNC_UFS_MPHY_SDA (MTK_PIN_NO(138) | 6) +#define PINMUX_GPIO138__FUNC_IOBIST138 (MTK_PIN_NO(138) | 8) + +#define PINMUX_GPIO139__FUNC_GPIO139 (MTK_PIN_NO(139) | 0) +#define PINMUX_GPIO139__FUNC_SCL0 (MTK_PIN_NO(139) | 1) +#define PINMUX_GPIO139__FUNC_BPI_BUS18 (MTK_PIN_NO(139) | 4) +#define PINMUX_GPIO139__FUNC_DBG_MON_B28 (MTK_PIN_NO(139) | 7) +#define PINMUX_GPIO139__FUNC_IOBIST139 (MTK_PIN_NO(139) | 8) + +#define PINMUX_GPIO140__FUNC_GPIO140 (MTK_PIN_NO(140) | 0) +#define PINMUX_GPIO140__FUNC_SDA0 (MTK_PIN_NO(140) | 1) +#define PINMUX_GPIO140__FUNC_BPI_BUS19 (MTK_PIN_NO(140) | 4) +#define PINMUX_GPIO140__FUNC_DBG_MON_B29 (MTK_PIN_NO(140) | 7) +#define PINMUX_GPIO140__FUNC_IOBIST140 (MTK_PIN_NO(140) | 8) + +#define PINMUX_GPIO141__FUNC_GPIO141 (MTK_PIN_NO(141) | 0) +#define PINMUX_GPIO141__FUNC_SCL1 (MTK_PIN_NO(141) | 1) +#define PINMUX_GPIO141__FUNC_SCL9 (MTK_PIN_NO(141) | 2) +#define PINMUX_GPIO141__FUNC_BPI_BUS20 (MTK_PIN_NO(141) | 4) +#define PINMUX_GPIO141__FUNC_DBG_MON_B30 (MTK_PIN_NO(141) | 7) +#define PINMUX_GPIO141__FUNC_IOBIST141 (MTK_PIN_NO(141) | 8) + +#define PINMUX_GPIO142__FUNC_GPIO142 (MTK_PIN_NO(142) | 0) +#define PINMUX_GPIO142__FUNC_SDA1 (MTK_PIN_NO(142) | 1) +#define PINMUX_GPIO142__FUNC_SDA9 (MTK_PIN_NO(142) | 2) +#define PINMUX_GPIO142__FUNC_BPI_BUS21 (MTK_PIN_NO(142) | 4) +#define PINMUX_GPIO142__FUNC_DBG_MON_B31 (MTK_PIN_NO(142) | 7) +#define PINMUX_GPIO142__FUNC_IOBIST142 (MTK_PIN_NO(142) | 8) + +#define PINMUX_GPIO143__FUNC_GPIO143 (MTK_PIN_NO(143) | 0) +#define PINMUX_GPIO143__FUNC_SCL2 (MTK_PIN_NO(143) | 1) +#define PINMUX_GPIO143__FUNC_DBG_MON_B9 (MTK_PIN_NO(143) | 7) +#define PINMUX_GPIO143__FUNC_IOBIST143 (MTK_PIN_NO(143) | 8) + +#define PINMUX_GPIO144__FUNC_GPIO144 (MTK_PIN_NO(144) | 0) +#define PINMUX_GPIO144__FUNC_SDA2 (MTK_PIN_NO(144) | 1) +#define PINMUX_GPIO144__FUNC_DBG_MON_B10 (MTK_PIN_NO(144) | 7) +#define PINMUX_GPIO144__FUNC_IOBIST144 (MTK_PIN_NO(144) | 8) + +#define PINMUX_GPIO145__FUNC_GPIO145 (MTK_PIN_NO(145) | 0) +#define PINMUX_GPIO145__FUNC_SCL3 (MTK_PIN_NO(145) | 1) +#define PINMUX_GPIO145__FUNC_DMIC1_CLK (MTK_PIN_NO(145) | 3) +#define PINMUX_GPIO145__FUNC_DBG_MON_B11 (MTK_PIN_NO(145) | 7) +#define PINMUX_GPIO145__FUNC_IOBIST145 (MTK_PIN_NO(145) | 8) + +#define PINMUX_GPIO146__FUNC_GPIO146 (MTK_PIN_NO(146) | 0) +#define PINMUX_GPIO146__FUNC_SDA3 (MTK_PIN_NO(146) | 1) +#define PINMUX_GPIO146__FUNC_DMIC1_DAT (MTK_PIN_NO(146) | 3) +#define PINMUX_GPIO146__FUNC_DBG_MON_B12 (MTK_PIN_NO(146) | 7) +#define PINMUX_GPIO146__FUNC_IOBIST146 (MTK_PIN_NO(146) | 8) + +#define PINMUX_GPIO147__FUNC_GPIO147 (MTK_PIN_NO(147) | 0) +#define PINMUX_GPIO147__FUNC_SCL4 (MTK_PIN_NO(147) | 1) +#define PINMUX_GPIO147__FUNC_DBG_MON_A31 (MTK_PIN_NO(147) | 7) +#define PINMUX_GPIO147__FUNC_IOBIST147 (MTK_PIN_NO(147) | 8) + +#define PINMUX_GPIO148__FUNC_GPIO148 (MTK_PIN_NO(148) | 0) +#define PINMUX_GPIO148__FUNC_SDA4 (MTK_PIN_NO(148) | 1) +#define PINMUX_GPIO148__FUNC_DBG_MON_A7 (MTK_PIN_NO(148) | 7) +#define PINMUX_GPIO148__FUNC_IOBIST148 (MTK_PIN_NO(148) | 8) + +#define PINMUX_GPIO149__FUNC_GPIO149 (MTK_PIN_NO(149) | 0) +#define PINMUX_GPIO149__FUNC_SCL5 (MTK_PIN_NO(149) | 1) +#define PINMUX_GPIO149__FUNC_IOBIST149 (MTK_PIN_NO(149) | 8) + +#define PINMUX_GPIO150__FUNC_GPIO150 (MTK_PIN_NO(150) | 0) +#define PINMUX_GPIO150__FUNC_SDA5 (MTK_PIN_NO(150) | 1) +#define PINMUX_GPIO150__FUNC_IOBIST150 (MTK_PIN_NO(150) | 8) + +#define PINMUX_GPIO151__FUNC_GPIO151 (MTK_PIN_NO(151) | 0) +#define PINMUX_GPIO151__FUNC_SCL6 (MTK_PIN_NO(151) | 1) +#define PINMUX_GPIO151__FUNC_SCL11 (MTK_PIN_NO(151) | 2) +#define PINMUX_GPIO151__FUNC_IOBIST151 (MTK_PIN_NO(151) | 8) + +#define PINMUX_GPIO152__FUNC_GPIO152 (MTK_PIN_NO(152) | 0) +#define PINMUX_GPIO152__FUNC_SDA6 (MTK_PIN_NO(152) | 1) +#define PINMUX_GPIO152__FUNC_SDA11 (MTK_PIN_NO(152) | 2) +#define PINMUX_GPIO152__FUNC_IOBIST152 (MTK_PIN_NO(152) | 8) + +#define PINMUX_GPIO153__FUNC_GPIO153 (MTK_PIN_NO(153) | 0) +#define PINMUX_GPIO153__FUNC_SCL7 (MTK_PIN_NO(153) | 1) +#define PINMUX_GPIO153__FUNC_DBG_MON_A3 (MTK_PIN_NO(153) | 7) +#define PINMUX_GPIO153__FUNC_IOBIST153 (MTK_PIN_NO(153) | 8) + +#define PINMUX_GPIO154__FUNC_GPIO154 (MTK_PIN_NO(154) | 0) +#define PINMUX_GPIO154__FUNC_SDA7 (MTK_PIN_NO(154) | 1) +#define PINMUX_GPIO154__FUNC_DBG_MON_A4 (MTK_PIN_NO(154) | 7) +#define PINMUX_GPIO154__FUNC_IOBIST154 (MTK_PIN_NO(154) | 8) + +#define PINMUX_GPIO155__FUNC_GPIO155 (MTK_PIN_NO(155) | 0) +#define PINMUX_GPIO155__FUNC_SCL8 (MTK_PIN_NO(155) | 1) +#define PINMUX_GPIO155__FUNC_DBG_MON_A5 (MTK_PIN_NO(155) | 7) +#define PINMUX_GPIO155__FUNC_IOBIST155 (MTK_PIN_NO(155) | 8) + +#define PINMUX_GPIO156__FUNC_GPIO156 (MTK_PIN_NO(156) | 0) +#define PINMUX_GPIO156__FUNC_SDA8 (MTK_PIN_NO(156) | 1) +#define PINMUX_GPIO156__FUNC_IOBIST156 (MTK_PIN_NO(156) | 8) + +#define PINMUX_GPIO157__FUNC_GPIO157 (MTK_PIN_NO(157) | 0) +#define PINMUX_GPIO157__FUNC_SCP_SCL0 (MTK_PIN_NO(157) | 1) +#define PINMUX_GPIO157__FUNC_SCP_SCL5 (MTK_PIN_NO(157) | 3) +#define PINMUX_GPIO157__FUNC_TP_UCTS1_VLP (MTK_PIN_NO(157) | 4) +#define PINMUX_GPIO157__FUNC_TP_GPIO0_AO (MTK_PIN_NO(157) | 5) +#define PINMUX_GPIO157__FUNC_DBG_MON_A27 (MTK_PIN_NO(157) | 7) +#define PINMUX_GPIO157__FUNC_IOBIST157 (MTK_PIN_NO(157) | 8) + +#define PINMUX_GPIO158__FUNC_GPIO158 (MTK_PIN_NO(158) | 0) +#define PINMUX_GPIO158__FUNC_SCP_SDA0 (MTK_PIN_NO(158) | 1) +#define PINMUX_GPIO158__FUNC_SCP_SDA5 (MTK_PIN_NO(158) | 3) +#define PINMUX_GPIO158__FUNC_TP_URTS1_VLP (MTK_PIN_NO(158) | 4) +#define PINMUX_GPIO158__FUNC_TP_GPIO1_AO (MTK_PIN_NO(158) | 5) +#define PINMUX_GPIO158__FUNC_DBG_MON_A28 (MTK_PIN_NO(158) | 7) +#define PINMUX_GPIO158__FUNC_IOBIST158 (MTK_PIN_NO(158) | 8) + +#define PINMUX_GPIO159__FUNC_GPIO159 (MTK_PIN_NO(159) | 0) +#define PINMUX_GPIO159__FUNC_SCP_SCL1 (MTK_PIN_NO(159) | 1) +#define PINMUX_GPIO159__FUNC_SCP_SCL4 (MTK_PIN_NO(159) | 3) +#define PINMUX_GPIO159__FUNC_TP_UCTS2_VLP (MTK_PIN_NO(159) | 4) +#define PINMUX_GPIO159__FUNC_TP_GPIO2_AO (MTK_PIN_NO(159) | 5) +#define PINMUX_GPIO159__FUNC_DBG_MON_A29 (MTK_PIN_NO(159) | 7) +#define PINMUX_GPIO159__FUNC_IOBIST159 (MTK_PIN_NO(159) | 8) + +#define PINMUX_GPIO160__FUNC_GPIO160 (MTK_PIN_NO(160) | 0) +#define PINMUX_GPIO160__FUNC_SCP_SDA1 (MTK_PIN_NO(160) | 1) +#define PINMUX_GPIO160__FUNC_SCP_SDA4 (MTK_PIN_NO(160) | 3) +#define PINMUX_GPIO160__FUNC_TP_URTS2_VLP (MTK_PIN_NO(160) | 4) +#define PINMUX_GPIO160__FUNC_TP_GPIO3_AO (MTK_PIN_NO(160) | 5) +#define PINMUX_GPIO160__FUNC_DBG_MON_A30 (MTK_PIN_NO(160) | 7) +#define PINMUX_GPIO160__FUNC_IOBIST160 (MTK_PIN_NO(160) | 8) + +#define PINMUX_GPIO161__FUNC_GPIO161 (MTK_PIN_NO(161) | 0) +#define PINMUX_GPIO161__FUNC_SCP_SCL2 (MTK_PIN_NO(161) | 1) +#define PINMUX_GPIO161__FUNC_SCL10 (MTK_PIN_NO(161) | 2) +#define PINMUX_GPIO161__FUNC_SCP_DMIC_CLK (MTK_PIN_NO(161) | 3) +#define PINMUX_GPIO161__FUNC_DMIC_CLK (MTK_PIN_NO(161) | 4) +#define PINMUX_GPIO161__FUNC_TP_GPIO4_AO (MTK_PIN_NO(161) | 5) +#define PINMUX_GPIO161__FUNC_EXTIF0_PRI (MTK_PIN_NO(161) | 6) +#define PINMUX_GPIO161__FUNC_IOBIST161 (MTK_PIN_NO(161) | 8) + +#define PINMUX_GPIO162__FUNC_GPIO162 (MTK_PIN_NO(162) | 0) +#define PINMUX_GPIO162__FUNC_SCP_SDA2 (MTK_PIN_NO(162) | 1) +#define PINMUX_GPIO162__FUNC_SDA10 (MTK_PIN_NO(162) | 2) +#define PINMUX_GPIO162__FUNC_SCP_DMIC_DAT (MTK_PIN_NO(162) | 3) +#define PINMUX_GPIO162__FUNC_DMIC_DAT (MTK_PIN_NO(162) | 4) +#define PINMUX_GPIO162__FUNC_TP_GPIO5_AO (MTK_PIN_NO(162) | 5) +#define PINMUX_GPIO162__FUNC_EXTIF0_GNT_B (MTK_PIN_NO(162) | 6) +#define PINMUX_GPIO162__FUNC_IOBIST162 (MTK_PIN_NO(162) | 8) + +#define PINMUX_GPIO163__FUNC_GPIO163 (MTK_PIN_NO(163) | 0) +#define PINMUX_GPIO163__FUNC_SCP_SCL3 (MTK_PIN_NO(163) | 1) +#define PINMUX_GPIO163__FUNC_SCL12 (MTK_PIN_NO(163) | 2) +#define PINMUX_GPIO163__FUNC_TP_GPIO6_AO (MTK_PIN_NO(163) | 5) +#define PINMUX_GPIO163__FUNC_MBISTREADEN_TRIGGER (MTK_PIN_NO(163) | 7) +#define PINMUX_GPIO163__FUNC_IOBIST163 (MTK_PIN_NO(163) | 8) + +#define PINMUX_GPIO164__FUNC_GPIO164 (MTK_PIN_NO(164) | 0) +#define PINMUX_GPIO164__FUNC_SCP_SDA3 (MTK_PIN_NO(164) | 1) +#define PINMUX_GPIO164__FUNC_SDA12 (MTK_PIN_NO(164) | 2) +#define PINMUX_GPIO164__FUNC_TP_GPIO7_AO (MTK_PIN_NO(164) | 5) +#define PINMUX_GPIO164__FUNC_MBISTWRITEEN_TRIGGER (MTK_PIN_NO(164) | 7) +#define PINMUX_GPIO164__FUNC_IOBIST164 (MTK_PIN_NO(164) | 8) + +#define PINMUX_GPIO165__FUNC_GPIO165 (MTK_PIN_NO(165) | 0) +#define PINMUX_GPIO165__FUNC_MIPI0_D_SCLK (MTK_PIN_NO(165) | 1) +#define PINMUX_GPIO165__FUNC_CONN_MIPI0_SCLK (MTK_PIN_NO(165) | 2) +#define PINMUX_GPIO165__FUNC_BPI_BUS18 (MTK_PIN_NO(165) | 3) +#define PINMUX_GPIO165__FUNC_ANT_SEL17 (MTK_PIN_NO(165) | 6) +#define PINMUX_GPIO165__FUNC_IOBIST165 (MTK_PIN_NO(165) | 8) + +#define PINMUX_GPIO166__FUNC_GPIO166 (MTK_PIN_NO(166) | 0) +#define PINMUX_GPIO166__FUNC_MIPI0_D_SDATA (MTK_PIN_NO(166) | 1) +#define PINMUX_GPIO166__FUNC_CONN_MIPI0_SDATA (MTK_PIN_NO(166) | 2) +#define PINMUX_GPIO166__FUNC_BPI_BUS19 (MTK_PIN_NO(166) | 3) +#define PINMUX_GPIO166__FUNC_ANT_SEL18 (MTK_PIN_NO(166) | 6) +#define PINMUX_GPIO166__FUNC_IOBIST166 (MTK_PIN_NO(166) | 8) + +#define PINMUX_GPIO167__FUNC_GPIO167 (MTK_PIN_NO(167) | 0) +#define PINMUX_GPIO167__FUNC_MIPI1_D_SCLK (MTK_PIN_NO(167) | 1) +#define PINMUX_GPIO167__FUNC_CONN_MIPI1_SCLK (MTK_PIN_NO(167) | 2) +#define PINMUX_GPIO167__FUNC_BPI_BUS20 (MTK_PIN_NO(167) | 3) +#define PINMUX_GPIO167__FUNC_ANT_SEL19 (MTK_PIN_NO(167) | 6) +#define PINMUX_GPIO167__FUNC_IOBIST167 (MTK_PIN_NO(167) | 8) + +#define PINMUX_GPIO168__FUNC_GPIO168 (MTK_PIN_NO(168) | 0) +#define PINMUX_GPIO168__FUNC_MIPI1_D_SDATA (MTK_PIN_NO(168) | 1) +#define PINMUX_GPIO168__FUNC_CONN_MIPI1_SDATA (MTK_PIN_NO(168) | 2) +#define PINMUX_GPIO168__FUNC_BPI_BUS21 (MTK_PIN_NO(168) | 3) +#define PINMUX_GPIO168__FUNC_ANT_SEL20 (MTK_PIN_NO(168) | 6) +#define PINMUX_GPIO168__FUNC_IOBIST168 (MTK_PIN_NO(168) | 8) + +#define PINMUX_GPIO169__FUNC_GPIO169 (MTK_PIN_NO(169) | 0) +#define PINMUX_GPIO169__FUNC_MIPI2_D_SCLK (MTK_PIN_NO(169) | 1) +#define PINMUX_GPIO169__FUNC_BPI_BUS10 (MTK_PIN_NO(169) | 3) +#define PINMUX_GPIO169__FUNC_MD_GPS_L1_BLANK (MTK_PIN_NO(169) | 6) +#define PINMUX_GPIO169__FUNC_IOBIST169 (MTK_PIN_NO(169) | 8) + +#define PINMUX_GPIO170__FUNC_GPIO170 (MTK_PIN_NO(170) | 0) +#define PINMUX_GPIO170__FUNC_MIPI2_D_SDATA (MTK_PIN_NO(170) | 1) +#define PINMUX_GPIO170__FUNC_BPI_BUS11 (MTK_PIN_NO(170) | 3) +#define PINMUX_GPIO170__FUNC_MD_GPS_L5_BLANK (MTK_PIN_NO(170) | 6) +#define PINMUX_GPIO170__FUNC_IOBIST170 (MTK_PIN_NO(170) | 8) + +#define PINMUX_GPIO171__FUNC_GPIO171 (MTK_PIN_NO(171) | 0) +#define PINMUX_GPIO171__FUNC_MIPI_M_SCLK (MTK_PIN_NO(171) | 1) +#define PINMUX_GPIO171__FUNC_IOBIST171 (MTK_PIN_NO(171) | 8) + +#define PINMUX_GPIO172__FUNC_GPIO172 (MTK_PIN_NO(172) | 0) +#define PINMUX_GPIO172__FUNC_MIPI_M_SDATA (MTK_PIN_NO(172) | 1) +#define PINMUX_GPIO172__FUNC_IOBIST172 (MTK_PIN_NO(172) | 8) + +#define PINMUX_GPIO173__FUNC_GPIO173 (MTK_PIN_NO(173) | 0) +#define PINMUX_GPIO173__FUNC_AUD_CLK_MOSI (MTK_PIN_NO(173) | 1) +#define PINMUX_GPIO173__FUNC_AUD_CLK_MOSI_A (MTK_PIN_NO(173) | 3) +#define PINMUX_GPIO173__FUNC_IOBIST173 (MTK_PIN_NO(173) | 8) + +#define PINMUX_GPIO174__FUNC_GPIO174 (MTK_PIN_NO(174) | 0) +#define PINMUX_GPIO174__FUNC_AUD_SYNC_MOSI (MTK_PIN_NO(174) | 1) +#define PINMUX_GPIO174__FUNC_IOBIST174 (MTK_PIN_NO(174) | 8) + +#define PINMUX_GPIO175__FUNC_GPIO175 (MTK_PIN_NO(175) | 0) +#define PINMUX_GPIO175__FUNC_AUD_DAT_MOSI0 (MTK_PIN_NO(175) | 1) +#define PINMUX_GPIO175__FUNC_AUD_DAT_MOSI0_A (MTK_PIN_NO(175) | 3) +#define PINMUX_GPIO175__FUNC_IOBIST175 (MTK_PIN_NO(175) | 8) + +#define PINMUX_GPIO176__FUNC_GPIO176 (MTK_PIN_NO(176) | 0) +#define PINMUX_GPIO176__FUNC_AUD_DAT_MOSI1 (MTK_PIN_NO(176) | 1) +#define PINMUX_GPIO176__FUNC_AUD_DAT_MOSI1_A (MTK_PIN_NO(176) | 3) +#define PINMUX_GPIO176__FUNC_IOBIST176 (MTK_PIN_NO(176) | 8) + +#define PINMUX_GPIO177__FUNC_GPIO177 (MTK_PIN_NO(177) | 0) +#define PINMUX_GPIO177__FUNC_AUD_NLE_MOSI0 (MTK_PIN_NO(177) | 1) +#define PINMUX_GPIO177__FUNC_AUD_SYNC_MISO (MTK_PIN_NO(177) | 2) +#define PINMUX_GPIO177__FUNC_IOBIST177 (MTK_PIN_NO(177) | 8) + +#define PINMUX_GPIO178__FUNC_GPIO178 (MTK_PIN_NO(178) | 0) +#define PINMUX_GPIO178__FUNC_AUD_NLE_MOSI1 (MTK_PIN_NO(178) | 1) +#define PINMUX_GPIO178__FUNC_AUD_CLK_MISO (MTK_PIN_NO(178) | 2) +#define PINMUX_GPIO178__FUNC_AUD_CLK_MISO_A (MTK_PIN_NO(178) | 3) +#define PINMUX_GPIO178__FUNC_IOBIST178 (MTK_PIN_NO(178) | 8) + +#define PINMUX_GPIO179__FUNC_GPIO179 (MTK_PIN_NO(179) | 0) +#define PINMUX_GPIO179__FUNC_AUD_DAT_MISO0 (MTK_PIN_NO(179) | 1) +#define PINMUX_GPIO179__FUNC_VOW_DAT_MISO (MTK_PIN_NO(179) | 2) +#define PINMUX_GPIO179__FUNC_AUD_DAT_MISO0_A (MTK_PIN_NO(179) | 3) +#define PINMUX_GPIO179__FUNC_IOBIST179 (MTK_PIN_NO(179) | 8) + +#define PINMUX_GPIO180__FUNC_GPIO180 (MTK_PIN_NO(180) | 0) +#define PINMUX_GPIO180__FUNC_AUD_DAT_MISO1 (MTK_PIN_NO(180) | 1) +#define PINMUX_GPIO180__FUNC_VOW_CLK_MISO (MTK_PIN_NO(180) | 2) +#define PINMUX_GPIO180__FUNC_AUD_DAT_MISO1_A (MTK_PIN_NO(180) | 3) +#define PINMUX_GPIO180__FUNC_IOBIST180 (MTK_PIN_NO(180) | 8) + +#define PINMUX_GPIO181__FUNC_GPIO181 (MTK_PIN_NO(181) | 0) +#define PINMUX_GPIO181__FUNC_SCP_VREQ_VAO (MTK_PIN_NO(181) | 1) +#define PINMUX_GPIO181__FUNC_IOBIST181 (MTK_PIN_NO(181) | 8) + +#define PINMUX_GPIO182__FUNC_GPIO182 (MTK_PIN_NO(182) | 0) +#define PINMUX_GPIO182__FUNC_CONN_TOP_CLK (MTK_PIN_NO(182) | 1) +#define PINMUX_GPIO182__FUNC_IOBIST182 (MTK_PIN_NO(182) | 8) + +#define PINMUX_GPIO183__FUNC_GPIO183 (MTK_PIN_NO(183) | 0) +#define PINMUX_GPIO183__FUNC_CONN_TOP_DATA (MTK_PIN_NO(183) | 1) +#define PINMUX_GPIO183__FUNC_IOBIST183 (MTK_PIN_NO(183) | 8) + +#define PINMUX_GPIO184__FUNC_GPIO184 (MTK_PIN_NO(184) | 0) +#define PINMUX_GPIO184__FUNC_CONN_BT_CLK (MTK_PIN_NO(184) | 1) +#define PINMUX_GPIO184__FUNC_IOBIST184 (MTK_PIN_NO(184) | 8) + +#define PINMUX_GPIO185__FUNC_GPIO185 (MTK_PIN_NO(185) | 0) +#define PINMUX_GPIO185__FUNC_CONN_BT_DATA (MTK_PIN_NO(185) | 1) +#define PINMUX_GPIO185__FUNC_IOBIST185 (MTK_PIN_NO(185) | 8) + +#define PINMUX_GPIO186__FUNC_GPIO186 (MTK_PIN_NO(186) | 0) +#define PINMUX_GPIO186__FUNC_CONN_HRST_B (MTK_PIN_NO(186) | 1) +#define PINMUX_GPIO186__FUNC_IOBIST186 (MTK_PIN_NO(186) | 8) + +#define PINMUX_GPIO187__FUNC_GPIO187 (MTK_PIN_NO(187) | 0) +#define PINMUX_GPIO187__FUNC_CONN_WB_PTA (MTK_PIN_NO(187) | 1) +#define PINMUX_GPIO187__FUNC_IOBIST187 (MTK_PIN_NO(187) | 8) + +#define PINMUX_GPIO188__FUNC_GPIO188 (MTK_PIN_NO(188) | 0) +#define PINMUX_GPIO188__FUNC_CONN_WF_CTRL0 (MTK_PIN_NO(188) | 1) +#define PINMUX_GPIO188__FUNC_IOBIST188 (MTK_PIN_NO(188) | 8) + +#define PINMUX_GPIO189__FUNC_GPIO189 (MTK_PIN_NO(189) | 0) +#define PINMUX_GPIO189__FUNC_CONN_WF_CTRL1 (MTK_PIN_NO(189) | 1) +#define PINMUX_GPIO189__FUNC_IOBIST189 (MTK_PIN_NO(189) | 8) + +#define PINMUX_GPIO190__FUNC_GPIO190 (MTK_PIN_NO(190) | 0) +#define PINMUX_GPIO190__FUNC_CONN_WF_CTRL2 (MTK_PIN_NO(190) | 1) +#define PINMUX_GPIO190__FUNC_IOBIST190 (MTK_PIN_NO(190) | 8) + +#define PINMUX_GPIO191__FUNC_GPIO191 (MTK_PIN_NO(191) | 0) +#define PINMUX_GPIO191__FUNC_CONN_TOP_CLK_2 (MTK_PIN_NO(191) | 1) +#define PINMUX_GPIO191__FUNC_IOBIST191 (MTK_PIN_NO(191) | 8) + +#define PINMUX_GPIO192__FUNC_GPIO192 (MTK_PIN_NO(192) | 0) +#define PINMUX_GPIO192__FUNC_CONN_TOP_DATA_2 (MTK_PIN_NO(192) | 1) +#define PINMUX_GPIO192__FUNC_IOBIST192 (MTK_PIN_NO(192) | 8) + +#define PINMUX_GPIO193__FUNC_GPIO193 (MTK_PIN_NO(193) | 0) +#define PINMUX_GPIO193__FUNC_CONN_HRST_B_2 (MTK_PIN_NO(193) | 1) +#define PINMUX_GPIO193__FUNC_IOBIST193 (MTK_PIN_NO(193) | 8) + +#define PINMUX_GPIO194__FUNC_GPIO194 (MTK_PIN_NO(194) | 0) +#define PINMUX_GPIO194__FUNC_GPS_L1_ELNA_EN (MTK_PIN_NO(194) | 1) +#define PINMUX_GPIO194__FUNC_MD_GPS_L1_BLANK (MTK_PIN_NO(194) | 2) +#define PINMUX_GPIO194__FUNC_IOBIST194 (MTK_PIN_NO(194) | 8) + +#define PINMUX_GPIO195__FUNC_GPIO195 (MTK_PIN_NO(195) | 0) +#define PINMUX_GPIO195__FUNC_GPS_L5_ELNA_EN (MTK_PIN_NO(195) | 1) +#define PINMUX_GPIO195__FUNC_MD_GPS_L5_BLANK (MTK_PIN_NO(195) | 2) +#define PINMUX_GPIO195__FUNC_ANT_SEL21 (MTK_PIN_NO(195) | 3) +#define PINMUX_GPIO195__FUNC_SPMI_P_TRIG_FLAG (MTK_PIN_NO(195) | 5) +#define PINMUX_GPIO195__FUNC_IOBIST195 (MTK_PIN_NO(195) | 8) + +#define PINMUX_GPIO196__FUNC_GPIO196 (MTK_PIN_NO(196) | 0) +#define PINMUX_GPIO196__FUNC_PAD_RESET_DRAM_0 (MTK_PIN_NO(196) | 1) +#define PINMUX_GPIO196__FUNC_IOBIST196 (MTK_PIN_NO(196) | 8) + +#endif /* __6858_PINFUNC_H */ diff --git a/arch/sh/boards/mach-rsk/devices-rsk7203.c b/arch/sh/boards/mach-rsk/devices-rsk7203.c index e6b05d4588b7..e8a8fc1d2ca9 100644 --- a/arch/sh/boards/mach-rsk/devices-rsk7203.c +++ b/arch/sh/boards/mach-rsk/devices-rsk7203.c @@ -4,17 +4,18 @@ * * Copyright (C) 2008 - 2010 Paul Mundt */ +#include #include #include #include #include #include #include -#include -#include -#include +#include +#include +#include #include -#include +#include #include static struct smsc911x_platform_config smsc911x_config = { @@ -37,101 +38,236 @@ static struct resource smsc911x_resources[] = { }, }; -static struct platform_device smsc911x_device = { - .name = "smsc911x", - .id = -1, - .num_resources = ARRAY_SIZE(smsc911x_resources), - .resource = smsc911x_resources, - .dev = { - .platform_data = &smsc911x_config, +static const struct software_node rsk7203_gpio_leds_node = { + .name = "rsk7203-gpio-leds", +}; + +static const struct software_node rsk7203_green_led_node = { + .name = "green", + .parent = &rsk7203_gpio_leds_node, + .properties = (const struct property_entry[]) { + PROPERTY_ENTRY_STRING("label", "green"), + PROPERTY_ENTRY_GPIO("gpios", &pfc_gpiochip_node, + GPIO_PE10, GPIO_ACTIVE_LOW), + { } }, }; -static struct gpio_led rsk7203_gpio_leds[] = { +static const struct software_node rsk7203_orange_led_node = { + .name = "orange", + .parent = &rsk7203_gpio_leds_node, + .properties = (const struct property_entry[]) { + PROPERTY_ENTRY_STRING("label", "orange"), + PROPERTY_ENTRY_STRING("linux,default-trigger", "nand-disk"), + PROPERTY_ENTRY_GPIO("gpios", &pfc_gpiochip_node, + GPIO_PE12, GPIO_ACTIVE_LOW), + { } + }, +}; + +static const struct software_node rsk7203_red1_led_node = { + .name = "red:timer", + .parent = &rsk7203_gpio_leds_node, + .properties = (const struct property_entry[]) { + PROPERTY_ENTRY_STRING("label", "red:timer"), + PROPERTY_ENTRY_STRING("linux,default-trigger", "timer"), + PROPERTY_ENTRY_GPIO("gpios", &pfc_gpiochip_node, + GPIO_PC14, GPIO_ACTIVE_LOW), + { } + }, +}; + +static const struct software_node rsk7203_red2_led_node = { + .name = "red:heartbeat", + .parent = &rsk7203_gpio_leds_node, + .properties = (const struct property_entry[]) { + PROPERTY_ENTRY_STRING("label", "red:heartbeat"), + PROPERTY_ENTRY_STRING("linux,default-trigger", "heartbeat"), + PROPERTY_ENTRY_GPIO("gpios", &pfc_gpiochip_node, + GPIO_PE11, GPIO_ACTIVE_LOW), + { } + }, +}; + +static const struct software_node rsk7203_gpio_keys_node = { + .name = "rsk7203-gpio-keys", + .properties = (const struct property_entry[]) { + PROPERTY_ENTRY_U32("poll-interval", 50), + { } + }, +}; + +static const struct software_node rsk7203_sw1_key_node = { + .parent = &rsk7203_gpio_keys_node, + .properties = (const struct property_entry[]) { + PROPERTY_ENTRY_U32("linux,code", BTN_0), + PROPERTY_ENTRY_GPIO("gpios", &pfc_gpiochip_node, + GPIO_PB0, GPIO_ACTIVE_LOW), + PROPERTY_ENTRY_STRING("label", "SW1"), + { } + }, +}; + +static const struct software_node rsk7203_sw2_key_node = { + .parent = &rsk7203_gpio_keys_node, + .properties = (const struct property_entry[]) { + PROPERTY_ENTRY_U32("linux,code", BTN_1), + PROPERTY_ENTRY_GPIO("gpios", &pfc_gpiochip_node, + GPIO_PB1, GPIO_ACTIVE_LOW), + PROPERTY_ENTRY_STRING("label", "SW2"), + { } + }, +}; + +static const struct software_node rsk7203_sw3_key_node = { + .parent = &rsk7203_gpio_keys_node, + .properties = (const struct property_entry[]) { + PROPERTY_ENTRY_U32("linux,code", BTN_2), + PROPERTY_ENTRY_GPIO("gpios", &pfc_gpiochip_node, + GPIO_PB2, GPIO_ACTIVE_LOW), + PROPERTY_ENTRY_STRING("label", "SW3"), + { } + }, +}; + +/* The base of the function GPIOs in the flat enum */ +#define SH7203_FN_BASE GPIO_FN_PINT7_PB + +static const struct software_node rsk7203_pfc_functions_node = { + .name = "functions", + .parent = &pfc_gpiochip_node, +}; + +static const struct software_node rsk7203_txd0_hog_node = { + .name = "txd0-hog", + .parent = &rsk7203_pfc_functions_node, + .properties = (const struct property_entry[]) { + PROPERTY_ENTRY_BOOL("gpio-hog"), + PROPERTY_ENTRY_U32_ARRAY("gpios", ((u32[]){ + GPIO_FN_TXD0 - SH7203_FN_BASE, GPIO_ACTIVE_HIGH + })), + PROPERTY_ENTRY_BOOL("input"), + PROPERTY_ENTRY_STRING("line-name", "TXD0"), + { } + }, +}; + +static const struct software_node rsk7203_rxd0_hog_node = { + .name = "rxd0-hog", + .parent = &rsk7203_pfc_functions_node, + .properties = (const struct property_entry[]) { + PROPERTY_ENTRY_BOOL("gpio-hog"), + PROPERTY_ENTRY_U32_ARRAY("gpios", ((u32[]){ + GPIO_FN_RXD0 - SH7203_FN_BASE, GPIO_ACTIVE_HIGH + })), + PROPERTY_ENTRY_BOOL("input"), + PROPERTY_ENTRY_STRING("line-name", "RXD0"), + { } + }, +}; + +static const struct software_node rsk7203_irq0_hog_node = { + .name = "irq0-hog", + .parent = &rsk7203_pfc_functions_node, + .properties = (const struct property_entry[]) { + PROPERTY_ENTRY_BOOL("gpio-hog"), + PROPERTY_ENTRY_U32_ARRAY("gpios", ((u32[]){ + GPIO_FN_IRQ0_PB - SH7203_FN_BASE, GPIO_ACTIVE_HIGH + })), + PROPERTY_ENTRY_BOOL("input"), + PROPERTY_ENTRY_STRING("line-name", "IRQ0_PB"), + { } + }, +}; + +static const struct software_node * const rsk7203_swnodes[] __initconst = { + &rsk7203_gpio_leds_node, + &rsk7203_green_led_node, + &rsk7203_orange_led_node, + &rsk7203_red1_led_node, + &rsk7203_red2_led_node, + &rsk7203_gpio_keys_node, + &rsk7203_sw1_key_node, + &rsk7203_sw2_key_node, + &rsk7203_sw3_key_node, + &rsk7203_pfc_functions_node, + &rsk7203_txd0_hog_node, + &rsk7203_rxd0_hog_node, + &rsk7203_irq0_hog_node, + NULL +}; + +static const struct platform_device_info rsk7203_devices[] __initconst = { { - .name = "green", - .gpio = GPIO_PE10, - .active_low = 1, - }, { - .name = "orange", - .default_trigger = "nand-disk", - .gpio = GPIO_PE12, - .active_low = 1, - }, { - .name = "red:timer", - .default_trigger = "timer", - .gpio = GPIO_PC14, - .active_low = 1, - }, { - .name = "red:heartbeat", - .default_trigger = "heartbeat", - .gpio = GPIO_PE11, - .active_low = 1, + .name = "smsc911x", + .id = PLATFORM_DEVID_NONE, + .res = smsc911x_resources, + .num_res = ARRAY_SIZE(smsc911x_resources), + .data = &smsc911x_config, + .size_data = sizeof(smsc911x_config), }, -}; - -static struct gpio_led_platform_data rsk7203_gpio_leds_info = { - .leds = rsk7203_gpio_leds, - .num_leds = ARRAY_SIZE(rsk7203_gpio_leds), -}; - -static struct platform_device led_device = { - .name = "leds-gpio", - .id = -1, - .dev = { - .platform_data = &rsk7203_gpio_leds_info, - }, -}; - -static struct gpio_keys_button rsk7203_gpio_keys_table[] = { { - .code = BTN_0, - .gpio = GPIO_PB0, - .active_low = 1, - .desc = "SW1", - }, { - .code = BTN_1, - .gpio = GPIO_PB1, - .active_low = 1, - .desc = "SW2", - }, { - .code = BTN_2, - .gpio = GPIO_PB2, - .active_low = 1, - .desc = "SW3", + .name = "leds-gpio", + .id = PLATFORM_DEVID_NONE, + .swnode = &rsk7203_gpio_leds_node, + }, + { + .name = "gpio-keys-polled", + .id = PLATFORM_DEVID_NONE, + .swnode = &rsk7203_gpio_keys_node, }, }; -static struct gpio_keys_platform_data rsk7203_gpio_keys_info = { - .buttons = rsk7203_gpio_keys_table, - .nbuttons = ARRAY_SIZE(rsk7203_gpio_keys_table), - .poll_interval = 50, /* default to 50ms */ -}; +/* + * The pfc-sh7203 device is registered at arch_initcall level, and the + * sh-pfc driver (registered at postcore_initcall level) probes as soon + * as the device is created. + * + * We need to register our software nodes at postcore_initcall level so + * they are already present in the system when the driver probes and + * tries to apply GPIO hogs. + */ +static int __init rsk7203_sw_nodes_setup(void) +{ + int error; -static struct platform_device keys_device = { - .name = "gpio-keys-polled", - .dev = { - .platform_data = &rsk7203_gpio_keys_info, - }, -}; + error = software_node_register(&pfc_gpiochip_node); + if (error && error != -EEXIST) { + pr_err("RSK7203: failed to register PFC software node: %d\n", + error); + return error; + } -static struct platform_device *rsk7203_devices[] __initdata = { - &smsc911x_device, - &led_device, - &keys_device, -}; + error = software_node_register_node_group(rsk7203_swnodes); + if (error) { + pr_err("RSK7203: failed to register board software nodes: %d\n", + error); + return error; + } + + return 0; +} +postcore_initcall(rsk7203_sw_nodes_setup); static int __init rsk7203_devices_setup(void) { - /* Select pins for SCIF0 */ - gpio_request(GPIO_FN_TXD0, NULL); - gpio_request(GPIO_FN_RXD0, NULL); + struct platform_device *pd; + int error; + int i; /* Setup LAN9118: CS1 in 16-bit Big Endian Mode, IRQ0 at Port B */ __raw_writel(0x36db0400, 0xfffc0008); /* CS1BCR */ - gpio_request(GPIO_FN_IRQ0_PB, NULL); - return platform_add_devices(rsk7203_devices, - ARRAY_SIZE(rsk7203_devices)); + for (i = 0; i < ARRAY_SIZE(rsk7203_devices); i++) { + pd = platform_device_register_full(&rsk7203_devices[i]); + error = PTR_ERR_OR_ZERO(pd); + if (error) { + pr_err("failed to create platform device %s: %d\n", + rsk7203_devices[i].name, error); + return error; + } + } + + return 0; } device_initcall(rsk7203_devices_setup); diff --git a/arch/sh/include/cpu-common/cpu/pfc.h b/arch/sh/include/cpu-common/cpu/pfc.h index 879d2c9da537..d57e38c05bdb 100644 --- a/arch/sh/include/cpu-common/cpu/pfc.h +++ b/arch/sh/include/cpu-common/cpu/pfc.h @@ -11,6 +11,9 @@ #include struct resource; +struct software_node; + +extern const struct software_node pfc_gpiochip_node; int sh_pfc_register(const char *name, struct resource *resource, u32 num_resources); diff --git a/arch/sh/kernel/cpu/pfc.c b/arch/sh/kernel/cpu/pfc.c index 062056ede88d..5a8d804d607b 100644 --- a/arch/sh/kernel/cpu/pfc.c +++ b/arch/sh/kernel/cpu/pfc.c @@ -5,21 +5,29 @@ * Copyright (C) 2012 Renesas Solutions Corp. */ +#include #include #include +#include #include -static struct platform_device sh_pfc_device = { - .id = -1, +const struct software_node pfc_gpiochip_node = { + .name = "sh-pfc", }; int __init sh_pfc_register(const char *name, struct resource *resource, u32 num_resources) { - sh_pfc_device.name = name; - sh_pfc_device.num_resources = num_resources; - sh_pfc_device.resource = resource; + struct platform_device_info pdev_info = { + .name = name, + .id = PLATFORM_DEVID_NONE, + .res = resource, + .num_res = num_resources, + .swnode = &pfc_gpiochip_node, + }; + struct platform_device *pdev; - return platform_device_register(&sh_pfc_device); + pdev = platform_device_register_full(&pdev_info); + return PTR_ERR_OR_ZERO(pdev); } diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig index eda54aa5fde6..e5618b51ac14 100644 --- a/drivers/pinctrl/Kconfig +++ b/drivers/pinctrl/Kconfig @@ -488,6 +488,7 @@ config PINCTRL_PIC32 depends on MACH_PIC32 || COMPILE_TEST select PINMUX select GENERIC_PINCONF + select GPIOLIB select GPIOLIB_IRQCHIP help This is the pin controller and gpio driver for Microchip PIC32 @@ -564,6 +565,7 @@ config PINCTRL_STMFX depends on I2C depends on HAS_IOMEM select GENERIC_PINCONF + select GPIOLIB select GPIOLIB_IRQCHIP select MFD_STMFX help diff --git a/drivers/pinctrl/airoha/pinctrl-airoha.c b/drivers/pinctrl/airoha/pinctrl-airoha.c index 04b4424c688b..abfb018f207e 100644 --- a/drivers/pinctrl/airoha/pinctrl-airoha.c +++ b/drivers/pinctrl/airoha/pinctrl-airoha.c @@ -2519,10 +2519,8 @@ static int airoha_pinctrl_add_gpiochip(struct airoha_pinctrl *pinctrl, err = devm_request_irq(dev, irq, airoha_irq_handler, IRQF_SHARED, dev_name(dev), pinctrl); - if (err) { - dev_err(dev, "error requesting irq %d: %d\n", irq, err); + if (err) return err; - } return devm_gpiochip_add_data(dev, gc, pinctrl); } diff --git a/drivers/pinctrl/aspeed/pinctrl-aspeed-g7-soc1.c b/drivers/pinctrl/aspeed/pinctrl-aspeed-g7-soc1.c index 50027d69c342..f8b4066699ce 100644 --- a/drivers/pinctrl/aspeed/pinctrl-aspeed-g7-soc1.c +++ b/drivers/pinctrl/aspeed/pinctrl-aspeed-g7-soc1.c @@ -1018,7 +1018,8 @@ PIN_GROUP(I3C6, AA22, AB20); PIN_GROUP(I3C7, AF18, AE19); PIN_GROUP(I3C8, AD20, AC20); PIN_GROUP(I3C9, AA21, AB21); -PIN_GROUP(JTAGM1, D12, F10, E11, F11, F13); +PIN_GROUP(JTAGM1, F10, E11, F11, F13); +PIN_GROUP(JTAGM1TRST, D12); PIN_GROUP(LPC0, AF26, AF25, B16, D14, B15, B14, C17, B13, E14, C15); PIN_GROUP(LPC1, C16, C14, C11, D9, F14, D10, C12, C13, AE16, AE17); PIN_GROUP(LTPI, U25, U26, Y26, AA24); @@ -1263,6 +1264,7 @@ static const struct pingroup aspeed_g7_soc1_groups[] = { GROUP(I3C8), GROUP(I3C9), GROUP(JTAGM1), + GROUP(JTAGM1TRST), GROUP(LPC0), GROUP(LPC1), GROUP(LTPI), @@ -1528,7 +1530,7 @@ static const struct aspeed_g7_soc1_function aspeed_g7_soc1_functions[] = { FUNC(I3C7, (1), "I3C7"), FUNC(I3C8, (1), "I3C8"), FUNC(I3C9, (1), "I3C9"), - FUNC(JTAGM1, (1), "JTAGM1"), + FUNC(JTAGM1, (1, 1), "JTAGM1", "JTAGM1TRST"), FUNC(LPC0, (2), "LPC0"), FUNC(LPC1, (2), "LPC1"), FUNC(LTPI, (2), "LTPI"), diff --git a/drivers/pinctrl/bcm/Kconfig b/drivers/pinctrl/bcm/Kconfig index 206f3f1249cf..19d22e7fd11e 100644 --- a/drivers/pinctrl/bcm/Kconfig +++ b/drivers/pinctrl/bcm/Kconfig @@ -121,6 +121,7 @@ source "drivers/pinctrl/bcm/Kconfig.stb" config PINCTRL_IPROC_GPIO bool "Broadcom iProc GPIO (with PINCONF) driver" depends on ARCH_BCM_IPROC || COMPILE_TEST + select GPIOLIB select GPIOLIB_IRQCHIP select PINCONF select GENERIC_PINCONF @@ -186,6 +187,7 @@ config PINCTRL_NS config PINCTRL_NSP_GPIO bool "Broadcom NSP GPIO (with PINCONF) driver" depends on ARCH_BCM_NSP || COMPILE_TEST + select GPIOLIB select GPIOLIB_IRQCHIP select PINCONF select GENERIC_PINCONF diff --git a/drivers/pinctrl/bcm/pinctrl-bcm2835.c b/drivers/pinctrl/bcm/pinctrl-bcm2835.c index e7b35019a5a7..725e880ae086 100644 --- a/drivers/pinctrl/bcm/pinctrl-bcm2835.c +++ b/drivers/pinctrl/bcm/pinctrl-bcm2835.c @@ -1350,7 +1350,6 @@ static int bcm2835_pinctrl_probe(struct platform_device *pdev) pc->pctl_desc = *pdata->pctl_desc; pc->pctl_dev = devm_pinctrl_register(dev, &pc->pctl_desc, pc); if (IS_ERR(pc->pctl_dev)) { - gpiochip_remove(&pc->gpio_chip); return PTR_ERR(pc->pctl_dev); } diff --git a/drivers/pinctrl/bcm/pinctrl-nsp-gpio.c b/drivers/pinctrl/bcm/pinctrl-nsp-gpio.c index b425ecacd1b0..1fbb101386a3 100644 --- a/drivers/pinctrl/bcm/pinctrl-nsp-gpio.c +++ b/drivers/pinctrl/bcm/pinctrl-nsp-gpio.c @@ -671,11 +671,8 @@ static int nsp_gpio_probe(struct platform_device *pdev) /* Install ISR for this GPIO controller. */ ret = devm_request_irq(dev, irq, nsp_gpio_irq_handler, IRQF_SHARED, "gpio-a", &chip->gc); - if (ret) { - dev_err(&pdev->dev, "Unable to request IRQ%d: %d\n", - irq, ret); + if (ret) return ret; - } girq = &chip->gc.irq; gpio_irq_chip_set_chip(girq, &nsp_gpio_irq_chip); diff --git a/drivers/pinctrl/freescale/pinctrl-imx1-core.c b/drivers/pinctrl/freescale/pinctrl-imx1-core.c index b7bd4ef9c0db..4a6bdaefa42f 100644 --- a/drivers/pinctrl/freescale/pinctrl-imx1-core.c +++ b/drivers/pinctrl/freescale/pinctrl-imx1-core.c @@ -547,14 +547,11 @@ static int imx1_pinctrl_parse_functions(struct device_node *np, */ static bool imx1_pinctrl_dt_is_flat_functions(struct device_node *np) { - struct device_node *function_np; - struct device_node *pinctrl_np; - - for_each_child_of_node(np, function_np) { + for_each_child_of_node_scoped(np, function_np) { if (of_property_present(function_np, "fsl,pins")) return true; - for_each_child_of_node(function_np, pinctrl_np) { + for_each_child_of_node_scoped(function_np, pinctrl_np) { if (of_property_present(pinctrl_np, "fsl,pins")) return false; } diff --git a/drivers/pinctrl/mediatek/Kconfig b/drivers/pinctrl/mediatek/Kconfig index 97980cc28b9c..30ef3dc5dfb1 100644 --- a/drivers/pinctrl/mediatek/Kconfig +++ b/drivers/pinctrl/mediatek/Kconfig @@ -11,7 +11,7 @@ config EINT_MTK default PINCTRL_MTK_PARIS config PINCTRL_MTK - bool + tristate depends on OF select PINMUX select GENERIC_PINCONF @@ -22,13 +22,13 @@ config PINCTRL_MTK_V2 tristate config PINCTRL_MTK_MTMIPS - bool + tristate depends on RALINK select PINMUX select GENERIC_PINCONF config PINCTRL_MTK_MOORE - bool + tristate depends on OF select GENERIC_PINCONF select GENERIC_PINCTRL_GROUPS @@ -48,42 +48,42 @@ config PINCTRL_MTK_PARIS # For MIPS SoCs config PINCTRL_MT7620 - bool "MediaTek MT7620 pin control" + tristate "MediaTek MT7620 pin control" depends on SOC_MT7620 || COMPILE_TEST depends on RALINK default SOC_MT7620 select PINCTRL_MTK_MTMIPS config PINCTRL_MT7621 - bool "MediaTek MT7621 pin control" + tristate "MediaTek MT7621 pin control" depends on SOC_MT7621 || COMPILE_TEST depends on RALINK default SOC_MT7621 select PINCTRL_MTK_MTMIPS config PINCTRL_MT76X8 - bool "MediaTek MT76X8 pin control" + tristate "MediaTek MT76X8 pin control" depends on SOC_MT7620 || COMPILE_TEST depends on RALINK default SOC_MT7620 select PINCTRL_MTK_MTMIPS config PINCTRL_RT2880 - bool "Ralink RT2880 pin control" + tristate "Ralink RT2880 pin control" depends on SOC_RT288X || COMPILE_TEST depends on RALINK default SOC_RT288X select PINCTRL_MTK_MTMIPS config PINCTRL_RT305X - bool "Ralink RT305X pin control" + tristate "Ralink RT305X pin control" depends on SOC_RT305X || COMPILE_TEST depends on RALINK default SOC_RT305X select PINCTRL_MTK_MTMIPS config PINCTRL_RT3883 - bool "Ralink RT3883 pin control" + tristate "Ralink RT3883 pin control" depends on SOC_RT3883 || COMPILE_TEST depends on RALINK default SOC_RT3883 @@ -91,35 +91,35 @@ config PINCTRL_RT3883 # For ARMv7 SoCs config PINCTRL_MT2701 - bool "MediaTek MT2701 pin control" + tristate "MediaTek MT2701 pin control" depends on MACH_MT7623 || MACH_MT2701 || COMPILE_TEST depends on OF default MACH_MT2701 select PINCTRL_MTK config PINCTRL_MT7623 - bool "MediaTek MT7623 pin control with generic binding" + tristate "MediaTek MT7623 pin control with generic binding" depends on MACH_MT7623 || COMPILE_TEST depends on OF default MACH_MT7623 select PINCTRL_MTK_MOORE config PINCTRL_MT7629 - bool "MediaTek MT7629 pin control" + tristate "MediaTek MT7629 pin control" depends on MACH_MT7629 || COMPILE_TEST depends on OF default MACH_MT7629 select PINCTRL_MTK_MOORE config PINCTRL_MT8135 - bool "MediaTek MT8135 pin control" + tristate "MediaTek MT8135 pin control" depends on MACH_MT8135 || COMPILE_TEST depends on OF default MACH_MT8135 select PINCTRL_MTK config PINCTRL_MT8127 - bool "MediaTek MT8127 pin control" + tristate "MediaTek MT8127 pin control" depends on MACH_MT8127 || COMPILE_TEST depends on OF default MACH_MT8127 @@ -127,7 +127,7 @@ config PINCTRL_MT8127 # For ARMv8 SoCs config PINCTRL_MT2712 - bool "MediaTek MT2712 pin control" + tristate "MediaTek MT2712 pin control" depends on OF depends on ARM64 || COMPILE_TEST default ARM64 && ARCH_MEDIATEK @@ -153,21 +153,31 @@ config PINCTRL_MT6779 map specific eint which doesn't have real gpio pin. config PINCTRL_MT6795 - bool "MediaTek MT6795 pin control" + tristate "MediaTek MT6795 pin control" depends on OF depends on ARM64 || COMPILE_TEST default ARM64 && ARCH_MEDIATEK select PINCTRL_MTK_PARIS config PINCTRL_MT6797 - bool "MediaTek MT6797 pin control" + tristate "MediaTek MT6797 pin control" depends on OF depends on ARM64 || COMPILE_TEST default ARM64 && ARCH_MEDIATEK select PINCTRL_MTK_PARIS +config PINCTRL_MT6858 + tristate "MediaTek MT6858 pin control" + depends on OF + depends on ARM64 || COMPILE_TEST + default ARM64 && ARCH_MEDIATEK + select PINCTRL_MTK_PARIS + help + Say yes here to support pin controller and gpio driver + on the MediaTek MT6858 SoC. + config PINCTRL_MT6878 - bool "MediaTek MT6878 pin control" + tristate "MediaTek MT6878 pin control" depends on OF depends on ARM64 || COMPILE_TEST default ARM64 && ARCH_MEDIATEK @@ -177,7 +187,7 @@ config PINCTRL_MT6878 on the MediaTek MT6878 SoC. config PINCTRL_MT6893 - bool "MediaTek Dimensity MT6893 pin control" + tristate "MediaTek Dimensity MT6893 pin control" depends on OF depends on ARM64 || COMPILE_TEST default ARM64 && ARCH_MEDIATEK @@ -187,63 +197,63 @@ config PINCTRL_MT6893 on the MediaTek Dimensity 1200 MT6893 Smartphone SoC. config PINCTRL_MT7622 - bool "MediaTek MT7622 pin control" + tristate "MediaTek MT7622 pin control" depends on OF depends on ARM64 || COMPILE_TEST default ARM64 && ARCH_MEDIATEK select PINCTRL_MTK_MOORE config PINCTRL_MT7981 - bool "MediaTek MT7981 pin control" + tristate "MediaTek MT7981 pin control" depends on OF depends on ARM64 || COMPILE_TEST default ARM64 && ARCH_MEDIATEK select PINCTRL_MTK_MOORE config PINCTRL_MT7986 - bool "MediaTek MT7986 pin control" + tristate "MediaTek MT7986 pin control" depends on OF depends on ARM64 || COMPILE_TEST default ARM64 && ARCH_MEDIATEK select PINCTRL_MTK_MOORE config PINCTRL_MT7988 - bool "Mediatek MT7988 pin control" + tristate "Mediatek MT7988 pin control" depends on OF depends on ARM64 || COMPILE_TEST default ARM64 && ARCH_MEDIATEK select PINCTRL_MTK_MOORE config PINCTRL_MT8167 - bool "MediaTek MT8167 pin control" + tristate "MediaTek MT8167 pin control" depends on OF depends on ARM64 || COMPILE_TEST default ARM64 && ARCH_MEDIATEK select PINCTRL_MTK config PINCTRL_MT8173 - bool "MediaTek MT8173 pin control" + tristate "MediaTek MT8173 pin control" depends on OF depends on ARM64 || COMPILE_TEST default ARM64 && ARCH_MEDIATEK select PINCTRL_MTK config PINCTRL_MT8183 - bool "MediaTek MT8183 pin control" + tristate "MediaTek MT8183 pin control" depends on OF depends on ARM64 || COMPILE_TEST default ARM64 && ARCH_MEDIATEK select PINCTRL_MTK_PARIS config PINCTRL_MT8186 - bool "MediaTek MT8186 pin control" + tristate "MediaTek MT8186 pin control" depends on OF depends on ARM64 || COMPILE_TEST default ARM64 && ARCH_MEDIATEK select PINCTRL_MTK_PARIS config PINCTRL_MT8188 - bool "MediaTek MT8188 pin control" + tristate "MediaTek MT8188 pin control" depends on OF depends on ARM64 || COMPILE_TEST default ARM64 && ARCH_MEDIATEK @@ -255,7 +265,7 @@ config PINCTRL_MT8188 map specific eint which doesn't have real gpio pin. config PINCTRL_MT8189 - bool "MediaTek MT8189 pin control" + tristate "MediaTek MT8189 pin control" depends on OF depends on ARM64 || COMPILE_TEST default ARM64 && ARCH_MEDIATEK @@ -267,21 +277,21 @@ config PINCTRL_MT8189 map specific eint which doesn't have real gpio pin. config PINCTRL_MT8192 - bool "MediaTek MT8192 pin control" + tristate "MediaTek MT8192 pin control" depends on OF depends on ARM64 || COMPILE_TEST default ARM64 && ARCH_MEDIATEK select PINCTRL_MTK_PARIS config PINCTRL_MT8195 - bool "MediaTek MT8195 pin control" + tristate "MediaTek MT8195 pin control" depends on OF depends on ARM64 || COMPILE_TEST default ARM64 && ARCH_MEDIATEK select PINCTRL_MTK_PARIS config PINCTRL_MT8196 - bool "MediaTek MT8196 pin control" + tristate "MediaTek MT8196 pin control" depends on OF depends on ARM64 || COMPILE_TEST default ARM64 && ARCH_MEDIATEK @@ -293,14 +303,14 @@ config PINCTRL_MT8196 map specific eint which doesn't have real gpio pin. config PINCTRL_MT8365 - bool "MediaTek MT8365 pin control" + tristate "MediaTek MT8365 pin control" depends on OF depends on ARM64 || COMPILE_TEST default ARM64 && ARCH_MEDIATEK select PINCTRL_MTK config PINCTRL_MT8516 - bool "MediaTek MT8516 pin control" + tristate "MediaTek MT8516 pin control" depends on OF depends on ARM64 || COMPILE_TEST default ARM64 && ARCH_MEDIATEK @@ -308,7 +318,7 @@ config PINCTRL_MT8516 # For PMIC config PINCTRL_MT6397 - bool "MediaTek MT6397 pin control" + tristate "MediaTek MT6397 pin control" depends on MFD_MT6397 || COMPILE_TEST depends on OF default MFD_MT6397 diff --git a/drivers/pinctrl/mediatek/Makefile b/drivers/pinctrl/mediatek/Makefile index 6dc17b0c23f9..6ee3833dc6e2 100644 --- a/drivers/pinctrl/mediatek/Makefile +++ b/drivers/pinctrl/mediatek/Makefile @@ -22,6 +22,7 @@ obj-$(CONFIG_PINCTRL_MT6765) += pinctrl-mt6765.o obj-$(CONFIG_PINCTRL_MT6779) += pinctrl-mt6779.o obj-$(CONFIG_PINCTRL_MT6795) += pinctrl-mt6795.o obj-$(CONFIG_PINCTRL_MT6797) += pinctrl-mt6797.o +obj-$(CONFIG_PINCTRL_MT6858) += pinctrl-mt6858.o obj-$(CONFIG_PINCTRL_MT6878) += pinctrl-mt6878.o obj-$(CONFIG_PINCTRL_MT6893) += pinctrl-mt6893.o obj-$(CONFIG_PINCTRL_MT7622) += pinctrl-mt7622.o diff --git a/drivers/pinctrl/mediatek/mtk-eint.c b/drivers/pinctrl/mediatek/mtk-eint.c index 47ac92ea98c2..8b022545a3e9 100644 --- a/drivers/pinctrl/mediatek/mtk-eint.c +++ b/drivers/pinctrl/mediatek/mtk-eint.c @@ -12,8 +12,10 @@ */ #include +#include #include #include +#include #include #include #include @@ -509,6 +511,27 @@ int mtk_eint_find_irq(struct mtk_eint *eint, unsigned long eint_n) } EXPORT_SYMBOL_GPL(mtk_eint_find_irq); +static void mtk_eint_teardown(void *data) +{ + struct mtk_eint *eint = data; + unsigned int i, virq; + + /* Detach the demux handler so it can no longer reference freed data. */ + irq_set_chained_handler_and_data(eint->irq, NULL, NULL); + + /* Wait for any in-flight handler to finish before tearing down. */ + synchronize_irq(eint->irq); + + /* Dispose of all child mappings before the domain is removed. */ + for (i = 0; i < eint->hw->ap_num; i++) { + virq = irq_find_mapping(eint->domain, i); + if (virq) + irq_dispose_mapping(virq); + } + + irq_domain_remove(eint->domain); +} + int mtk_eint_do_init(struct mtk_eint *eint, struct mtk_eint_pin *eint_pin) { unsigned int size, i, port, virq, inst = 0; @@ -601,7 +624,7 @@ int mtk_eint_do_init(struct mtk_eint *eint, struct mtk_eint_pin *eint_pin) irq_set_chained_handler_and_data(eint->irq, mtk_eint_irq_handler, eint); - return 0; + return devm_add_action_or_reset(eint->dev, mtk_eint_teardown, eint); err_eint: for (i = 0; i < eint->nbase; i++) { diff --git a/drivers/pinctrl/mediatek/pinctrl-moore.c b/drivers/pinctrl/mediatek/pinctrl-moore.c index 17e30f83dc19..fdfbe007b84f 100644 --- a/drivers/pinctrl/mediatek/pinctrl-moore.c +++ b/drivers/pinctrl/mediatek/pinctrl-moore.c @@ -10,6 +10,7 @@ #include #include +#include #include @@ -594,7 +595,7 @@ static int mtk_build_gpiochip(struct mtk_pinctrl *hw) chip->base = -1; chip->ngpio = hw->soc->npins; - ret = gpiochip_add_data(chip, hw); + ret = devm_gpiochip_add_data(hw->dev, chip, hw); if (ret < 0) return ret; @@ -608,10 +609,8 @@ static int mtk_build_gpiochip(struct mtk_pinctrl *hw) if (!of_property_present(hw->dev->of_node, "gpio-ranges")) { ret = gpiochip_add_pin_range(chip, dev_name(hw->dev), 0, 0, chip->ngpio); - if (ret < 0) { - gpiochip_remove(chip); + if (ret < 0) return ret; - } } return 0; @@ -745,3 +744,7 @@ int mtk_moore_pinctrl_probe(struct platform_device *pdev, return 0; } +EXPORT_SYMBOL_NS_GPL(mtk_moore_pinctrl_probe, "MTK_PINCTRL"); + +MODULE_DESCRIPTION("MediaTek Pinctrl Common Driver V2 Moore"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/pinctrl/mediatek/pinctrl-mt2701.c b/drivers/pinctrl/mediatek/pinctrl-mt2701.c index 6b1c7122b0fb..9e04f5b7cbba 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt2701.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt2701.c @@ -542,3 +542,7 @@ static int __init mtk_pinctrl_init(void) return platform_driver_register(&mtk_pinctrl_driver); } arch_initcall(mtk_pinctrl_init); + +MODULE_DESCRIPTION("MediaTek MT2701 Pinctrl Driver"); +MODULE_LICENSE("GPL v2"); +MODULE_IMPORT_NS("MTK_PINCTRL"); diff --git a/drivers/pinctrl/mediatek/pinctrl-mt2712.c b/drivers/pinctrl/mediatek/pinctrl-mt2712.c index bb7394ae252b..c7df168c314d 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt2712.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt2712.c @@ -591,3 +591,7 @@ static int __init mtk_pinctrl_init(void) } arch_initcall(mtk_pinctrl_init); + +MODULE_DESCRIPTION("MediaTek MT2712 Pinctrl Driver"); +MODULE_LICENSE("GPL v2"); +MODULE_IMPORT_NS("MTK_PINCTRL"); diff --git a/drivers/pinctrl/mediatek/pinctrl-mt6397.c b/drivers/pinctrl/mediatek/pinctrl-mt6397.c index 03d0f65d7bcc..13cee2a209c2 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt6397.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt6397.c @@ -49,6 +49,7 @@ static const struct of_device_id mt6397_pctrl_match[] = { { .compatible = "mediatek,mt6397-pinctrl", }, { } }; +MODULE_DEVICE_TABLE(of, mt6397_pctrl_match); static struct platform_driver mtk_pinctrl_driver = { .probe = mt6397_pinctrl_probe, @@ -59,3 +60,7 @@ static struct platform_driver mtk_pinctrl_driver = { }; builtin_platform_driver(mtk_pinctrl_driver); + +MODULE_DESCRIPTION("MediaTek MT6397 Pinctrl Driver"); +MODULE_LICENSE("GPL v2"); +MODULE_IMPORT_NS("MTK_PINCTRL"); diff --git a/drivers/pinctrl/mediatek/pinctrl-mt6795.c b/drivers/pinctrl/mediatek/pinctrl-mt6795.c index ee3ae3d2fa7e..82df5cafc3d3 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt6795.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt6795.c @@ -607,6 +607,7 @@ static const struct of_device_id mt6795_pctrl_match[] = { { .compatible = "mediatek,mt6795-pinctrl", .data = &mt6795_data }, { } }; +MODULE_DEVICE_TABLE(of, mt6795_pctrl_match); static struct platform_driver mt6795_pinctrl_driver = { .driver = { @@ -622,3 +623,6 @@ static int __init mtk_pinctrl_init(void) return platform_driver_register(&mt6795_pinctrl_driver); } arch_initcall(mtk_pinctrl_init); + +MODULE_DESCRIPTION("MediaTek MT6795 Pinctrl Driver"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/pinctrl/mediatek/pinctrl-mt6797.c b/drivers/pinctrl/mediatek/pinctrl-mt6797.c index 53f240491259..6d4a5b16035f 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt6797.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt6797.c @@ -61,6 +61,7 @@ static const struct of_device_id mt6797_pinctrl_of_match[] = { { .compatible = "mediatek,mt6797-pinctrl", .data = &mt6797_data }, { } }; +MODULE_DEVICE_TABLE(of, mt6797_pinctrl_of_match); static struct platform_driver mt6797_pinctrl_driver = { .driver = { @@ -75,3 +76,6 @@ static int __init mt6797_pinctrl_init(void) return platform_driver_register(&mt6797_pinctrl_driver); } arch_initcall(mt6797_pinctrl_init); + +MODULE_DESCRIPTION("MediaTek MT6797 Pinctrl Driver"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/pinctrl/mediatek/pinctrl-mt6858.c b/drivers/pinctrl/mediatek/pinctrl-mt6858.c new file mode 100644 index 000000000000..996b826e00d0 --- /dev/null +++ b/drivers/pinctrl/mediatek/pinctrl-mt6858.c @@ -0,0 +1,1409 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2025 MediaTek Inc. + * Alice Chao + * Copyright (c) 2026 Jolla Mobile Ltd + * Nikolai Burov + */ + +#include +#include "pinctrl-mtk-mt6858.h" +#include "pinctrl-paris.h" + +/* MT6858 have multiple bases to program pin configuration listed as the below: + * GPIO_BASE: 0x10005000 + * IOCFG_LM_BASE: 0x11B20000 + * IOCFG_RB_BASE: 0x11C10000 + * IOCFG_BM2_BASE: 0x11D10000 + * IOCFG_BM_BASE: 0x11D30000 + * IOCFG_BM1_BASE: 0x11D40000 + * IOCFG_LT_BASE: 0x11E20000 + * IOCFG_LT1_BASE: 0x11E30000 + * IOCFG_RT_BASE: 0x11ED0000 + * IOCFG_RT1_BASE: 0x11EE0000 + * _i_based could be used to indicate what base the pin should be mapped into. + */ + +#define PIN_FIELD_BASE(s_pin, e_pin, i_base, s_addr, x_addrs, s_bit, x_bits) \ + PIN_FIELD_CALC(s_pin, e_pin, i_base, s_addr, x_addrs, s_bit, x_bits, \ + 32, 0) + +static const struct mtk_pin_field_calc mt6858_pin_mode_range[] = { + /* Pin mode field is 5 bits with 8 bit stride */ + PIN_FIELD(0, 196, 0x0300, 0x10, 0, 8), +}; + +static const struct mtk_pin_field_calc mt6858_pin_dir_range[] = { + PIN_FIELD(0, 196, 0x0000, 0x10, 0, 1), +}; + +static const struct mtk_pin_field_calc mt6858_pin_di_range[] = { + PIN_FIELD(0, 196, 0x0200, 0x10, 0, 1), +}; + +static const struct mtk_pin_field_calc mt6858_pin_do_range[] = { + PIN_FIELD(0, 196, 0x0100, 0x10, 0, 1), +}; + +static const struct mtk_pin_field_calc mt6858_pin_ies_range[] = { + PIN_FIELD_BASE(0, 0, 8, 0x0060, 0x10, 4, 1), + PIN_FIELD_BASE(1, 1, 8, 0x0060, 0x10, 5, 1), + PIN_FIELD_BASE(2, 2, 8, 0x0060, 0x10, 6, 1), + PIN_FIELD_BASE(3, 3, 8, 0x0060, 0x10, 8, 1), + PIN_FIELD_BASE(4, 4, 8, 0x0060, 0x10, 9, 1), + PIN_FIELD_BASE(5, 5, 8, 0x0060, 0x10, 10, 1), + PIN_FIELD_BASE(6, 6, 8, 0x0060, 0x10, 11, 1), + PIN_FIELD_BASE(7, 7, 8, 0x0060, 0x10, 12, 1), + PIN_FIELD_BASE(8, 8, 5, 0x0060, 0x10, 15, 1), + PIN_FIELD_BASE(9, 9, 5, 0x0060, 0x10, 16, 1), + PIN_FIELD_BASE(10, 10, 5, 0x0060, 0x10, 9, 1), + PIN_FIELD_BASE(11, 11, 5, 0x0060, 0x10, 10, 1), + PIN_FIELD_BASE(12, 12, 5, 0x0060, 0x10, 11, 1), + PIN_FIELD_BASE(13, 13, 7, 0x0030, 0x10, 0, 1), + PIN_FIELD_BASE(14, 14, 7, 0x0030, 0x10, 1, 1), + PIN_FIELD_BASE(15, 15, 7, 0x0030, 0x10, 2, 1), + PIN_FIELD_BASE(16, 16, 7, 0x0030, 0x10, 3, 1), + PIN_FIELD_BASE(17, 17, 7, 0x0030, 0x10, 4, 1), + PIN_FIELD_BASE(18, 18, 6, 0x0020, 0x10, 0, 1), + PIN_FIELD_BASE(19, 19, 6, 0x0020, 0x10, 1, 1), + PIN_FIELD_BASE(20, 20, 6, 0x0020, 0x10, 2, 1), + PIN_FIELD_BASE(21, 21, 5, 0x0060, 0x10, 12, 1), + PIN_FIELD_BASE(22, 22, 5, 0x0060, 0x10, 13, 1), + PIN_FIELD_BASE(23, 23, 8, 0x0060, 0x10, 7, 1), + PIN_FIELD_BASE(24, 24, 5, 0x0060, 0x10, 14, 1), + PIN_FIELD_BASE(25, 25, 2, 0x0050, 0x10, 14, 1), + PIN_FIELD_BASE(26, 26, 3, 0x0060, 0x10, 1, 1), + PIN_FIELD_BASE(27, 27, 2, 0x0050, 0x10, 0, 1), + PIN_FIELD_BASE(28, 28, 2, 0x0050, 0x10, 1, 1), + PIN_FIELD_BASE(29, 29, 2, 0x0050, 0x10, 2, 1), + PIN_FIELD_BASE(30, 30, 2, 0x0050, 0x10, 3, 1), + PIN_FIELD_BASE(31, 31, 2, 0x0050, 0x10, 4, 1), + PIN_FIELD_BASE(32, 32, 2, 0x0050, 0x10, 5, 1), + PIN_FIELD_BASE(33, 33, 2, 0x0050, 0x10, 6, 1), + PIN_FIELD_BASE(34, 34, 2, 0x0050, 0x10, 7, 1), + PIN_FIELD_BASE(35, 35, 4, 0x0050, 0x10, 4, 1), + PIN_FIELD_BASE(36, 36, 8, 0x0060, 0x10, 0, 1), + PIN_FIELD_BASE(37, 37, 8, 0x0060, 0x10, 1, 1), + PIN_FIELD_BASE(38, 38, 8, 0x0060, 0x10, 2, 1), + PIN_FIELD_BASE(39, 39, 8, 0x0060, 0x10, 3, 1), + PIN_FIELD_BASE(40, 40, 1, 0x0050, 0x10, 11, 1), + PIN_FIELD_BASE(41, 41, 1, 0x0050, 0x10, 8, 1), + PIN_FIELD_BASE(42, 42, 1, 0x0050, 0x10, 10, 1), + PIN_FIELD_BASE(43, 43, 1, 0x0050, 0x10, 12, 1), + PIN_FIELD_BASE(44, 44, 1, 0x0050, 0x10, 9, 1), + PIN_FIELD_BASE(45, 45, 5, 0x0060, 0x10, 17, 1), + PIN_FIELD_BASE(46, 46, 5, 0x0060, 0x10, 19, 1), + PIN_FIELD_BASE(47, 47, 5, 0x0060, 0x10, 20, 1), + PIN_FIELD_BASE(48, 48, 5, 0x0060, 0x10, 18, 1), + PIN_FIELD_BASE(49, 49, 4, 0x0050, 0x10, 26, 1), + PIN_FIELD_BASE(50, 50, 4, 0x0050, 0x10, 25, 1), + PIN_FIELD_BASE(51, 51, 1, 0x0050, 0x10, 28, 1), + PIN_FIELD_BASE(52, 52, 1, 0x0050, 0x10, 27, 1), + PIN_FIELD_BASE(53, 53, 5, 0x0060, 0x10, 25, 1), + PIN_FIELD_BASE(54, 54, 5, 0x0060, 0x10, 21, 1), + PIN_FIELD_BASE(55, 55, 5, 0x0060, 0x10, 24, 1), + PIN_FIELD_BASE(56, 56, 5, 0x0060, 0x10, 22, 1), + PIN_FIELD_BASE(57, 57, 5, 0x0060, 0x10, 23, 1), + PIN_FIELD_BASE(58, 58, 3, 0x0060, 0x10, 21, 1), + PIN_FIELD_BASE(59, 59, 3, 0x0060, 0x10, 22, 1), + PIN_FIELD_BASE(60, 60, 3, 0x0060, 0x10, 24, 1), + PIN_FIELD_BASE(61, 61, 3, 0x0060, 0x10, 23, 1), + PIN_FIELD_BASE(62, 62, 8, 0x0060, 0x10, 25, 1), + PIN_FIELD_BASE(63, 63, 8, 0x0060, 0x10, 26, 1), + PIN_FIELD_BASE(64, 64, 8, 0x0060, 0x10, 28, 1), + PIN_FIELD_BASE(65, 65, 8, 0x0060, 0x10, 27, 1), + PIN_FIELD_BASE(66, 66, 1, 0x0050, 0x10, 17, 1), + PIN_FIELD_BASE(67, 67, 1, 0x0050, 0x10, 18, 1), + PIN_FIELD_BASE(68, 68, 1, 0x0050, 0x10, 20, 1), + PIN_FIELD_BASE(69, 69, 1, 0x0050, 0x10, 19, 1), + PIN_FIELD_BASE(70, 70, 1, 0x0050, 0x10, 21, 1), + PIN_FIELD_BASE(71, 71, 1, 0x0050, 0x10, 22, 1), + PIN_FIELD_BASE(72, 72, 1, 0x0050, 0x10, 24, 1), + PIN_FIELD_BASE(73, 73, 1, 0x0050, 0x10, 23, 1), + PIN_FIELD_BASE(74, 74, 1, 0x0050, 0x10, 13, 1), + PIN_FIELD_BASE(75, 75, 1, 0x0050, 0x10, 14, 1), + PIN_FIELD_BASE(76, 76, 1, 0x0050, 0x10, 16, 1), + PIN_FIELD_BASE(77, 77, 1, 0x0050, 0x10, 15, 1), + PIN_FIELD_BASE(78, 78, 3, 0x0060, 0x10, 25, 1), + PIN_FIELD_BASE(79, 79, 3, 0x0060, 0x10, 26, 1), + PIN_FIELD_BASE(80, 80, 3, 0x0060, 0x10, 28, 1), + PIN_FIELD_BASE(81, 81, 3, 0x0060, 0x10, 27, 1), + PIN_FIELD_BASE(82, 82, 8, 0x0060, 0x10, 13, 1), + PIN_FIELD_BASE(83, 83, 8, 0x0060, 0x10, 14, 1), + PIN_FIELD_BASE(84, 84, 8, 0x0060, 0x10, 15, 1), + PIN_FIELD_BASE(85, 85, 8, 0x0060, 0x10, 16, 1), + PIN_FIELD_BASE(86, 86, 8, 0x0060, 0x10, 17, 1), + PIN_FIELD_BASE(87, 87, 8, 0x0060, 0x10, 18, 1), + PIN_FIELD_BASE(88, 88, 4, 0x0050, 0x10, 19, 1), + PIN_FIELD_BASE(89, 89, 4, 0x0050, 0x10, 21, 1), + PIN_FIELD_BASE(90, 90, 4, 0x0050, 0x10, 20, 1), + PIN_FIELD_BASE(91, 91, 4, 0x0050, 0x10, 22, 1), + PIN_FIELD_BASE(92, 92, 4, 0x0050, 0x10, 24, 1), + PIN_FIELD_BASE(93, 93, 4, 0x0050, 0x10, 23, 1), + PIN_FIELD_BASE(94, 94, 4, 0x0050, 0x10, 7, 1), + PIN_FIELD_BASE(95, 95, 4, 0x0050, 0x10, 8, 1), + PIN_FIELD_BASE(96, 96, 4, 0x0050, 0x10, 6, 1), + PIN_FIELD_BASE(97, 97, 4, 0x0050, 0x10, 9, 1), + PIN_FIELD_BASE(98, 98, 5, 0x0060, 0x10, 8, 1), + PIN_FIELD_BASE(99, 99, 9, 0x0040, 0x10, 0, 1), + PIN_FIELD_BASE(100, 100, 9, 0x0040, 0x10, 1, 1), + PIN_FIELD_BASE(101, 101, 9, 0x0040, 0x10, 2, 1), + PIN_FIELD_BASE(102, 102, 9, 0x0040, 0x10, 3, 1), + PIN_FIELD_BASE(103, 103, 9, 0x0040, 0x10, 4, 1), + PIN_FIELD_BASE(104, 104, 9, 0x0040, 0x10, 5, 1), + PIN_FIELD_BASE(105, 105, 9, 0x0040, 0x10, 6, 1), + PIN_FIELD_BASE(106, 106, 5, 0x0060, 0x10, 0, 1), + PIN_FIELD_BASE(107, 107, 4, 0x0050, 0x10, 0, 1), + PIN_FIELD_BASE(108, 108, 4, 0x0050, 0x10, 1, 1), + PIN_FIELD_BASE(109, 109, 5, 0x0060, 0x10, 1, 1), + PIN_FIELD_BASE(110, 110, 5, 0x0060, 0x10, 2, 1), + PIN_FIELD_BASE(111, 111, 5, 0x0060, 0x10, 3, 1), + PIN_FIELD_BASE(112, 112, 5, 0x0060, 0x10, 4, 1), + PIN_FIELD_BASE(113, 113, 4, 0x0050, 0x10, 2, 1), + PIN_FIELD_BASE(114, 114, 4, 0x0050, 0x10, 3, 1), + PIN_FIELD_BASE(115, 115, 5, 0x0060, 0x10, 5, 1), + PIN_FIELD_BASE(116, 116, 4, 0x0050, 0x10, 10, 1), + PIN_FIELD_BASE(117, 117, 4, 0x0050, 0x10, 5, 1), + PIN_FIELD_BASE(118, 118, 3, 0x0060, 0x10, 4, 1), + PIN_FIELD_BASE(119, 119, 3, 0x0060, 0x10, 0, 1), + PIN_FIELD_BASE(120, 120, 3, 0x0060, 0x10, 5, 1), + PIN_FIELD_BASE(121, 121, 3, 0x0060, 0x10, 6, 1), + PIN_FIELD_BASE(122, 122, 7, 0x0030, 0x10, 7, 1), + PIN_FIELD_BASE(123, 123, 3, 0x0060, 0x10, 7, 1), + PIN_FIELD_BASE(124, 124, 1, 0x0050, 0x10, 26, 1), + PIN_FIELD_BASE(125, 125, 7, 0x0030, 0x10, 8, 1), + PIN_FIELD_BASE(126, 126, 2, 0x0050, 0x10, 15, 1), + PIN_FIELD_BASE(127, 127, 2, 0x0050, 0x10, 16, 1), + PIN_FIELD_BASE(128, 128, 2, 0x0050, 0x10, 17, 1), + PIN_FIELD_BASE(129, 129, 2, 0x0050, 0x10, 18, 1), + PIN_FIELD_BASE(130, 130, 3, 0x0060, 0x10, 8, 1), + PIN_FIELD_BASE(131, 131, 3, 0x0060, 0x10, 9, 1), + PIN_FIELD_BASE(132, 132, 3, 0x0060, 0x10, 10, 1), + PIN_FIELD_BASE(133, 133, 3, 0x0060, 0x10, 11, 1), + PIN_FIELD_BASE(134, 134, 3, 0x0060, 0x10, 12, 1), + PIN_FIELD_BASE(135, 135, 8, 0x0060, 0x10, 19, 1), + PIN_FIELD_BASE(136, 136, 8, 0x0060, 0x10, 20, 1), + PIN_FIELD_BASE(137, 137, 7, 0x0030, 0x10, 5, 1), + PIN_FIELD_BASE(138, 138, 7, 0x0030, 0x10, 6, 1), + PIN_FIELD_BASE(139, 139, 3, 0x0060, 0x10, 13, 1), + PIN_FIELD_BASE(140, 140, 3, 0x0060, 0x10, 17, 1), + PIN_FIELD_BASE(141, 141, 3, 0x0060, 0x10, 14, 1), + PIN_FIELD_BASE(142, 142, 3, 0x0060, 0x10, 18, 1), + PIN_FIELD_BASE(143, 143, 3, 0x0060, 0x10, 2, 1), + PIN_FIELD_BASE(144, 144, 3, 0x0060, 0x10, 3, 1), + PIN_FIELD_BASE(145, 145, 3, 0x0060, 0x10, 15, 1), + PIN_FIELD_BASE(146, 146, 3, 0x0060, 0x10, 19, 1), + PIN_FIELD_BASE(147, 147, 2, 0x0050, 0x10, 8, 1), + PIN_FIELD_BASE(148, 148, 2, 0x0050, 0x10, 11, 1), + PIN_FIELD_BASE(149, 149, 5, 0x0060, 0x10, 6, 1), + PIN_FIELD_BASE(150, 150, 5, 0x0060, 0x10, 7, 1), + PIN_FIELD_BASE(151, 151, 3, 0x0060, 0x10, 16, 1), + PIN_FIELD_BASE(152, 152, 3, 0x0060, 0x10, 20, 1), + PIN_FIELD_BASE(153, 153, 2, 0x0050, 0x10, 9, 1), + PIN_FIELD_BASE(154, 154, 2, 0x0050, 0x10, 12, 1), + PIN_FIELD_BASE(155, 155, 2, 0x0050, 0x10, 10, 1), + PIN_FIELD_BASE(156, 156, 2, 0x0050, 0x10, 13, 1), + PIN_FIELD_BASE(157, 157, 8, 0x0060, 0x10, 21, 1), + PIN_FIELD_BASE(158, 158, 8, 0x0060, 0x10, 23, 1), + PIN_FIELD_BASE(159, 159, 8, 0x0060, 0x10, 22, 1), + PIN_FIELD_BASE(160, 160, 8, 0x0060, 0x10, 24, 1), + PIN_FIELD_BASE(161, 161, 5, 0x0060, 0x10, 26, 1), + PIN_FIELD_BASE(162, 162, 5, 0x0060, 0x10, 28, 1), + PIN_FIELD_BASE(163, 163, 5, 0x0060, 0x10, 27, 1), + PIN_FIELD_BASE(164, 164, 5, 0x0060, 0x10, 29, 1), + PIN_FIELD_BASE(165, 165, 4, 0x0050, 0x10, 11, 1), + PIN_FIELD_BASE(166, 166, 4, 0x0050, 0x10, 12, 1), + PIN_FIELD_BASE(167, 167, 4, 0x0050, 0x10, 13, 1), + PIN_FIELD_BASE(168, 168, 4, 0x0050, 0x10, 14, 1), + PIN_FIELD_BASE(169, 169, 4, 0x0050, 0x10, 15, 1), + PIN_FIELD_BASE(170, 170, 4, 0x0050, 0x10, 16, 1), + PIN_FIELD_BASE(171, 171, 4, 0x0050, 0x10, 17, 1), + PIN_FIELD_BASE(172, 172, 4, 0x0050, 0x10, 18, 1), + PIN_FIELD_BASE(173, 173, 1, 0x0050, 0x10, 0, 1), + PIN_FIELD_BASE(174, 174, 1, 0x0050, 0x10, 7, 1), + PIN_FIELD_BASE(175, 175, 1, 0x0050, 0x10, 3, 1), + PIN_FIELD_BASE(176, 176, 1, 0x0050, 0x10, 4, 1), + PIN_FIELD_BASE(177, 177, 1, 0x0050, 0x10, 5, 1), + PIN_FIELD_BASE(178, 178, 1, 0x0050, 0x10, 6, 1), + PIN_FIELD_BASE(179, 179, 1, 0x0050, 0x10, 1, 1), + PIN_FIELD_BASE(180, 180, 1, 0x0050, 0x10, 2, 1), + PIN_FIELD_BASE(181, 181, 1, 0x0050, 0x10, 25, 1), + PIN_FIELD_BASE(182, 182, 9, 0x0040, 0x10, 11, 1), + PIN_FIELD_BASE(183, 183, 9, 0x0040, 0x10, 13, 1), + PIN_FIELD_BASE(184, 184, 9, 0x0040, 0x10, 7, 1), + PIN_FIELD_BASE(185, 185, 9, 0x0040, 0x10, 8, 1), + PIN_FIELD_BASE(186, 186, 9, 0x0040, 0x10, 9, 1), + PIN_FIELD_BASE(187, 187, 9, 0x0040, 0x10, 15, 1), + PIN_FIELD_BASE(188, 188, 9, 0x0040, 0x10, 16, 1), + PIN_FIELD_BASE(189, 189, 9, 0x0040, 0x10, 17, 1), + PIN_FIELD_BASE(190, 190, 9, 0x0040, 0x10, 18, 1), + PIN_FIELD_BASE(191, 191, 9, 0x0040, 0x10, 12, 1), + PIN_FIELD_BASE(192, 192, 9, 0x0040, 0x10, 14, 1), + PIN_FIELD_BASE(193, 193, 9, 0x0040, 0x10, 10, 1), + PIN_FIELD_BASE(194, 194, 9, 0x0040, 0x10, 19, 1), + PIN_FIELD_BASE(195, 195, 9, 0x0040, 0x10, 20, 1), + PIN_FIELD_BASE(196, 196, 6, 0x0020, 0x10, 3, 1), +}; + +static const struct mtk_pin_field_calc mt6858_pin_smt_range[] = { + PIN_FIELD_BASE(0, 0, 8, 0x0110, 0x10, 4, 1), + PIN_FIELD_BASE(1, 1, 8, 0x0110, 0x10, 5, 1), + PIN_FIELD_BASE(2, 2, 8, 0x0110, 0x10, 6, 1), + PIN_FIELD_BASE(3, 3, 8, 0x0110, 0x10, 8, 1), + PIN_FIELD_BASE(4, 4, 8, 0x0110, 0x10, 9, 1), + PIN_FIELD_BASE(5, 5, 8, 0x0110, 0x10, 10, 1), + PIN_FIELD_BASE(6, 6, 8, 0x0110, 0x10, 11, 1), + PIN_FIELD_BASE(7, 7, 8, 0x0110, 0x10, 12, 1), + PIN_FIELD_BASE(8, 8, 5, 0x00e0, 0x10, 15, 1), + PIN_FIELD_BASE(9, 9, 5, 0x00e0, 0x10, 16, 1), + PIN_FIELD_BASE(10, 10, 5, 0x00e0, 0x10, 9, 1), + PIN_FIELD_BASE(11, 11, 5, 0x00e0, 0x10, 10, 1), + PIN_FIELD_BASE(12, 12, 5, 0x00e0, 0x10, 11, 1), + PIN_FIELD_BASE(13, 13, 7, 0x0090, 0x10, 0, 1), + PIN_FIELD_BASE(14, 14, 7, 0x0090, 0x10, 1, 1), + PIN_FIELD_BASE(15, 15, 7, 0x0090, 0x10, 2, 1), + PIN_FIELD_BASE(16, 16, 7, 0x0090, 0x10, 3, 1), + PIN_FIELD_BASE(17, 17, 7, 0x0090, 0x10, 4, 1), + PIN_FIELD_BASE(18, 18, 6, 0x00c0, 0x10, 0, 1), + PIN_FIELD_BASE(19, 19, 6, 0x00c0, 0x10, 1, 1), + PIN_FIELD_BASE(20, 20, 6, 0x00c0, 0x10, 2, 1), + PIN_FIELD_BASE(21, 21, 5, 0x00e0, 0x10, 12, 1), + PIN_FIELD_BASE(22, 22, 5, 0x00e0, 0x10, 13, 1), + PIN_FIELD_BASE(23, 23, 8, 0x0110, 0x10, 7, 1), + PIN_FIELD_BASE(24, 24, 5, 0x00e0, 0x10, 14, 1), + PIN_FIELD_BASE(25, 25, 2, 0x00c0, 0x10, 14, 1), + PIN_FIELD_BASE(26, 26, 3, 0x00f0, 0x10, 1, 1), + PIN_FIELD_BASE(27, 27, 2, 0x00c0, 0x10, 0, 1), + PIN_FIELD_BASE(28, 28, 2, 0x00c0, 0x10, 1, 1), + PIN_FIELD_BASE(29, 29, 2, 0x00c0, 0x10, 2, 1), + PIN_FIELD_BASE(30, 30, 2, 0x00c0, 0x10, 3, 1), + PIN_FIELD_BASE(31, 31, 2, 0x00c0, 0x10, 4, 1), + PIN_FIELD_BASE(32, 32, 2, 0x00c0, 0x10, 5, 1), + PIN_FIELD_BASE(33, 33, 2, 0x00c0, 0x10, 6, 1), + PIN_FIELD_BASE(34, 34, 2, 0x00c0, 0x10, 7, 1), + PIN_FIELD_BASE(35, 35, 4, 0x0100, 0x10, 4, 1), + PIN_FIELD_BASE(36, 36, 8, 0x0110, 0x10, 0, 1), + PIN_FIELD_BASE(37, 37, 8, 0x0110, 0x10, 1, 1), + PIN_FIELD_BASE(38, 38, 8, 0x0110, 0x10, 2, 1), + PIN_FIELD_BASE(39, 39, 8, 0x0110, 0x10, 3, 1), + PIN_FIELD_BASE(40, 40, 1, 0x00b0, 0x10, 2, 1), + PIN_FIELD_BASE(41, 41, 1, 0x00b0, 0x10, 1, 1), + PIN_FIELD_BASE(42, 42, 1, 0x00b0, 0x10, 1, 1), + PIN_FIELD_BASE(43, 43, 1, 0x00b0, 0x10, 1, 1), + PIN_FIELD_BASE(44, 44, 1, 0x00b0, 0x10, 1, 1), + PIN_FIELD_BASE(45, 45, 5, 0x00e0, 0x10, 17, 1), + PIN_FIELD_BASE(46, 46, 5, 0x00e0, 0x10, 17, 1), + PIN_FIELD_BASE(47, 47, 5, 0x00e0, 0x10, 17, 1), + PIN_FIELD_BASE(48, 48, 5, 0x00e0, 0x10, 17, 1), + PIN_FIELD_BASE(49, 49, 4, 0x0100, 0x10, 18, 1), + PIN_FIELD_BASE(50, 50, 4, 0x0100, 0x10, 17, 1), + PIN_FIELD_BASE(51, 51, 1, 0x00b0, 0x10, 18, 1), + PIN_FIELD_BASE(52, 52, 1, 0x00b0, 0x10, 17, 1), + PIN_FIELD_BASE(53, 53, 5, 0x00e0, 0x10, 22, 1), + PIN_FIELD_BASE(54, 54, 5, 0x00e0, 0x10, 18, 1), + PIN_FIELD_BASE(55, 55, 5, 0x00e0, 0x10, 21, 1), + PIN_FIELD_BASE(56, 56, 5, 0x00e0, 0x10, 19, 1), + PIN_FIELD_BASE(57, 57, 5, 0x00e0, 0x10, 20, 1), + PIN_FIELD_BASE(58, 58, 3, 0x00f0, 0x10, 21, 1), + PIN_FIELD_BASE(59, 59, 3, 0x00f0, 0x10, 22, 1), + PIN_FIELD_BASE(60, 60, 3, 0x00f0, 0x10, 24, 1), + PIN_FIELD_BASE(61, 61, 3, 0x00f0, 0x10, 23, 1), + PIN_FIELD_BASE(62, 62, 8, 0x0110, 0x10, 25, 1), + PIN_FIELD_BASE(63, 63, 8, 0x0110, 0x10, 26, 1), + PIN_FIELD_BASE(64, 64, 8, 0x0110, 0x10, 28, 1), + PIN_FIELD_BASE(65, 65, 8, 0x0110, 0x10, 27, 1), + PIN_FIELD_BASE(66, 66, 1, 0x00b0, 0x10, 7, 1), + PIN_FIELD_BASE(67, 67, 1, 0x00b0, 0x10, 8, 1), + PIN_FIELD_BASE(68, 68, 1, 0x00b0, 0x10, 10, 1), + PIN_FIELD_BASE(69, 69, 1, 0x00b0, 0x10, 9, 1), + PIN_FIELD_BASE(70, 70, 1, 0x00b0, 0x10, 11, 1), + PIN_FIELD_BASE(71, 71, 1, 0x00b0, 0x10, 12, 1), + PIN_FIELD_BASE(72, 72, 1, 0x00b0, 0x10, 14, 1), + PIN_FIELD_BASE(73, 73, 1, 0x00b0, 0x10, 13, 1), + PIN_FIELD_BASE(74, 74, 1, 0x00b0, 0x10, 3, 1), + PIN_FIELD_BASE(75, 75, 1, 0x00b0, 0x10, 4, 1), + PIN_FIELD_BASE(76, 76, 1, 0x00b0, 0x10, 6, 1), + PIN_FIELD_BASE(77, 77, 1, 0x00b0, 0x10, 5, 1), + PIN_FIELD_BASE(78, 78, 3, 0x00f0, 0x10, 25, 1), + PIN_FIELD_BASE(79, 79, 3, 0x00f0, 0x10, 26, 1), + PIN_FIELD_BASE(80, 80, 3, 0x00f0, 0x10, 28, 1), + PIN_FIELD_BASE(81, 81, 3, 0x00f0, 0x10, 27, 1), + PIN_FIELD_BASE(82, 82, 8, 0x0110, 0x10, 13, 1), + PIN_FIELD_BASE(83, 83, 8, 0x0110, 0x10, 14, 1), + PIN_FIELD_BASE(84, 84, 8, 0x0110, 0x10, 15, 1), + PIN_FIELD_BASE(85, 85, 8, 0x0110, 0x10, 16, 1), + PIN_FIELD_BASE(86, 86, 8, 0x0110, 0x10, 17, 1), + PIN_FIELD_BASE(87, 87, 8, 0x0110, 0x10, 18, 1), + PIN_FIELD_BASE(88, 88, 4, 0x0100, 0x10, 15, 1), + PIN_FIELD_BASE(89, 89, 4, 0x0100, 0x10, 15, 1), + PIN_FIELD_BASE(90, 90, 4, 0x0100, 0x10, 15, 1), + PIN_FIELD_BASE(91, 91, 4, 0x0100, 0x10, 16, 1), + PIN_FIELD_BASE(92, 92, 4, 0x0100, 0x10, 16, 1), + PIN_FIELD_BASE(93, 93, 4, 0x0100, 0x10, 16, 1), + PIN_FIELD_BASE(94, 94, 4, 0x0100, 0x10, 7, 1), + PIN_FIELD_BASE(95, 95, 4, 0x0100, 0x10, 8, 1), + PIN_FIELD_BASE(96, 96, 4, 0x0100, 0x10, 6, 1), + PIN_FIELD_BASE(97, 97, 4, 0x0100, 0x10, 9, 1), + PIN_FIELD_BASE(98, 98, 5, 0x00e0, 0x10, 8, 1), + PIN_FIELD_BASE(99, 99, 9, 0x00a0, 0x10, 0, 1), + PIN_FIELD_BASE(100, 100, 9, 0x00a0, 0x10, 1, 1), + PIN_FIELD_BASE(101, 101, 9, 0x00a0, 0x10, 2, 1), + PIN_FIELD_BASE(102, 102, 9, 0x00a0, 0x10, 3, 1), + PIN_FIELD_BASE(103, 103, 9, 0x00a0, 0x10, 4, 1), + PIN_FIELD_BASE(104, 104, 9, 0x00a0, 0x10, 5, 1), + PIN_FIELD_BASE(105, 105, 9, 0x00a0, 0x10, 6, 1), + PIN_FIELD_BASE(106, 106, 5, 0x00e0, 0x10, 0, 1), + PIN_FIELD_BASE(107, 107, 4, 0x0100, 0x10, 0, 1), + PIN_FIELD_BASE(108, 108, 4, 0x0100, 0x10, 1, 1), + PIN_FIELD_BASE(109, 109, 5, 0x00e0, 0x10, 1, 1), + PIN_FIELD_BASE(110, 110, 5, 0x00e0, 0x10, 2, 1), + PIN_FIELD_BASE(111, 111, 5, 0x00e0, 0x10, 3, 1), + PIN_FIELD_BASE(112, 112, 5, 0x00e0, 0x10, 4, 1), + PIN_FIELD_BASE(113, 113, 4, 0x0100, 0x10, 2, 1), + PIN_FIELD_BASE(114, 114, 4, 0x0100, 0x10, 3, 1), + PIN_FIELD_BASE(115, 115, 5, 0x00e0, 0x10, 5, 1), + PIN_FIELD_BASE(116, 116, 4, 0x0100, 0x10, 10, 1), + PIN_FIELD_BASE(117, 117, 4, 0x0100, 0x10, 5, 1), + PIN_FIELD_BASE(118, 118, 3, 0x00f0, 0x10, 4, 1), + PIN_FIELD_BASE(119, 119, 3, 0x00f0, 0x10, 0, 1), + PIN_FIELD_BASE(120, 120, 3, 0x00f0, 0x10, 5, 1), + PIN_FIELD_BASE(121, 121, 3, 0x00f0, 0x10, 6, 1), + PIN_FIELD_BASE(122, 122, 7, 0x0090, 0x10, 7, 1), + PIN_FIELD_BASE(123, 123, 3, 0x00f0, 0x10, 7, 1), + PIN_FIELD_BASE(124, 124, 1, 0x00b0, 0x10, 16, 1), + PIN_FIELD_BASE(125, 125, 7, 0x0090, 0x10, 8, 1), + PIN_FIELD_BASE(126, 126, 2, 0x00c0, 0x10, 15, 1), + PIN_FIELD_BASE(127, 127, 2, 0x00c0, 0x10, 16, 1), + PIN_FIELD_BASE(128, 128, 2, 0x00c0, 0x10, 17, 1), + PIN_FIELD_BASE(129, 129, 2, 0x00c0, 0x10, 18, 1), + PIN_FIELD_BASE(130, 130, 3, 0x00f0, 0x10, 8, 1), + PIN_FIELD_BASE(131, 131, 3, 0x00f0, 0x10, 9, 1), + PIN_FIELD_BASE(132, 132, 3, 0x00f0, 0x10, 10, 1), + PIN_FIELD_BASE(133, 133, 3, 0x00f0, 0x10, 11, 1), + PIN_FIELD_BASE(134, 134, 3, 0x00f0, 0x10, 12, 1), + PIN_FIELD_BASE(135, 135, 8, 0x0110, 0x10, 19, 1), + PIN_FIELD_BASE(136, 136, 8, 0x0110, 0x10, 20, 1), + PIN_FIELD_BASE(137, 137, 7, 0x0090, 0x10, 5, 1), + PIN_FIELD_BASE(138, 138, 7, 0x0090, 0x10, 6, 1), + PIN_FIELD_BASE(139, 139, 3, 0x00f0, 0x10, 13, 1), + PIN_FIELD_BASE(140, 140, 3, 0x00f0, 0x10, 17, 1), + PIN_FIELD_BASE(141, 141, 3, 0x00f0, 0x10, 14, 1), + PIN_FIELD_BASE(142, 142, 3, 0x00f0, 0x10, 18, 1), + PIN_FIELD_BASE(143, 143, 3, 0x00f0, 0x10, 2, 1), + PIN_FIELD_BASE(144, 144, 3, 0x00f0, 0x10, 3, 1), + PIN_FIELD_BASE(145, 145, 3, 0x00f0, 0x10, 15, 1), + PIN_FIELD_BASE(146, 146, 3, 0x00f0, 0x10, 19, 1), + PIN_FIELD_BASE(147, 147, 2, 0x00c0, 0x10, 8, 1), + PIN_FIELD_BASE(148, 148, 2, 0x00c0, 0x10, 11, 1), + PIN_FIELD_BASE(149, 149, 5, 0x00e0, 0x10, 6, 1), + PIN_FIELD_BASE(150, 150, 5, 0x00e0, 0x10, 7, 1), + PIN_FIELD_BASE(151, 151, 3, 0x00f0, 0x10, 16, 1), + PIN_FIELD_BASE(152, 152, 3, 0x00f0, 0x10, 20, 1), + PIN_FIELD_BASE(153, 153, 2, 0x00c0, 0x10, 9, 1), + PIN_FIELD_BASE(154, 154, 2, 0x00c0, 0x10, 12, 1), + PIN_FIELD_BASE(155, 155, 2, 0x00c0, 0x10, 10, 1), + PIN_FIELD_BASE(156, 156, 2, 0x00c0, 0x10, 13, 1), + PIN_FIELD_BASE(157, 157, 8, 0x0110, 0x10, 21, 1), + PIN_FIELD_BASE(158, 158, 8, 0x0110, 0x10, 23, 1), + PIN_FIELD_BASE(159, 159, 8, 0x0110, 0x10, 22, 1), + PIN_FIELD_BASE(160, 160, 8, 0x0110, 0x10, 24, 1), + PIN_FIELD_BASE(161, 161, 5, 0x00e0, 0x10, 23, 1), + PIN_FIELD_BASE(162, 162, 5, 0x00e0, 0x10, 25, 1), + PIN_FIELD_BASE(163, 163, 5, 0x00e0, 0x10, 24, 1), + PIN_FIELD_BASE(164, 164, 5, 0x00e0, 0x10, 26, 1), + PIN_FIELD_BASE(165, 165, 4, 0x0100, 0x10, 11, 1), + PIN_FIELD_BASE(166, 166, 4, 0x0100, 0x10, 11, 1), + PIN_FIELD_BASE(167, 167, 4, 0x0100, 0x10, 12, 1), + PIN_FIELD_BASE(168, 168, 4, 0x0100, 0x10, 12, 1), + PIN_FIELD_BASE(169, 169, 4, 0x0100, 0x10, 13, 1), + PIN_FIELD_BASE(170, 170, 4, 0x0100, 0x10, 13, 1), + PIN_FIELD_BASE(171, 171, 4, 0x0100, 0x10, 14, 1), + PIN_FIELD_BASE(172, 172, 4, 0x0100, 0x10, 14, 1), + PIN_FIELD_BASE(173, 173, 1, 0x00b0, 0x10, 0, 1), + PIN_FIELD_BASE(174, 174, 1, 0x00b0, 0x10, 0, 1), + PIN_FIELD_BASE(175, 175, 1, 0x00b0, 0x10, 0, 1), + PIN_FIELD_BASE(176, 176, 1, 0x00b0, 0x10, 0, 1), + PIN_FIELD_BASE(177, 177, 1, 0x00b0, 0x10, 0, 1), + PIN_FIELD_BASE(178, 178, 1, 0x00b0, 0x10, 0, 1), + PIN_FIELD_BASE(179, 179, 1, 0x00b0, 0x10, 0, 1), + PIN_FIELD_BASE(180, 180, 1, 0x00b0, 0x10, 0, 1), + PIN_FIELD_BASE(181, 181, 1, 0x00b0, 0x10, 15, 1), + PIN_FIELD_BASE(182, 182, 9, 0x00a0, 0x10, 11, 1), + PIN_FIELD_BASE(183, 183, 9, 0x00a0, 0x10, 13, 1), + PIN_FIELD_BASE(184, 184, 9, 0x00a0, 0x10, 7, 1), + PIN_FIELD_BASE(185, 185, 9, 0x00a0, 0x10, 8, 1), + PIN_FIELD_BASE(186, 186, 9, 0x00a0, 0x10, 9, 1), + PIN_FIELD_BASE(187, 187, 9, 0x00a0, 0x10, 15, 1), + PIN_FIELD_BASE(188, 188, 9, 0x00a0, 0x10, 16, 1), + PIN_FIELD_BASE(189, 189, 9, 0x00a0, 0x10, 17, 1), + PIN_FIELD_BASE(190, 190, 9, 0x00a0, 0x10, 18, 1), + PIN_FIELD_BASE(191, 191, 9, 0x00a0, 0x10, 12, 1), + PIN_FIELD_BASE(192, 192, 9, 0x00a0, 0x10, 14, 1), + PIN_FIELD_BASE(193, 193, 9, 0x00a0, 0x10, 10, 1), + PIN_FIELD_BASE(194, 194, 9, 0x00a0, 0x10, 19, 1), + PIN_FIELD_BASE(195, 195, 9, 0x00a0, 0x10, 20, 1), + PIN_FIELD_BASE(196, 196, 6, 0x00c0, 0x10, 3, 1), +}; + +static const struct mtk_pin_field_calc mt6858_pin_pu_range[] = { + PIN_FIELD_BASE(0, 0, 8, 0x00b0, 0x10, 4, 1), + PIN_FIELD_BASE(1, 1, 8, 0x00b0, 0x10, 5, 1), + PIN_FIELD_BASE(2, 2, 8, 0x00b0, 0x10, 6, 1), + PIN_FIELD_BASE(3, 3, 8, 0x00b0, 0x10, 8, 1), + PIN_FIELD_BASE(4, 4, 8, 0x00b0, 0x10, 9, 1), + PIN_FIELD_BASE(5, 5, 8, 0x00b0, 0x10, 10, 1), + PIN_FIELD_BASE(6, 6, 8, 0x00b0, 0x10, 11, 1), + PIN_FIELD_BASE(7, 7, 8, 0x00b0, 0x10, 12, 1), + PIN_FIELD_BASE(8, 8, 5, 0x00a0, 0x10, 15, 1), + PIN_FIELD_BASE(9, 9, 5, 0x00a0, 0x10, 16, 1), + PIN_FIELD_BASE(10, 10, 5, 0x00a0, 0x10, 9, 1), + PIN_FIELD_BASE(11, 11, 5, 0x00a0, 0x10, 10, 1), + PIN_FIELD_BASE(12, 12, 5, 0x00a0, 0x10, 11, 1), + PIN_FIELD_BASE(13, 13, 7, 0x0070, 0x10, 0, 1), + PIN_FIELD_BASE(14, 14, 7, 0x0070, 0x10, 1, 1), + PIN_FIELD_BASE(15, 15, 7, 0x0070, 0x10, 2, 1), + PIN_FIELD_BASE(16, 16, 7, 0x0070, 0x10, 3, 1), + PIN_FIELD_BASE(17, 17, 7, 0x0070, 0x10, 4, 1), + PIN_FIELD_BASE(21, 21, 5, 0x00a0, 0x10, 12, 1), + PIN_FIELD_BASE(22, 22, 5, 0x00a0, 0x10, 13, 1), + PIN_FIELD_BASE(23, 23, 8, 0x00b0, 0x10, 7, 1), + PIN_FIELD_BASE(24, 24, 5, 0x00a0, 0x10, 14, 1), + PIN_FIELD_BASE(25, 25, 2, 0x0090, 0x10, 14, 1), + PIN_FIELD_BASE(26, 26, 3, 0x00a0, 0x10, 1, 1), + PIN_FIELD_BASE(27, 27, 2, 0x0090, 0x10, 0, 1), + PIN_FIELD_BASE(28, 28, 2, 0x0090, 0x10, 1, 1), + PIN_FIELD_BASE(29, 29, 2, 0x0090, 0x10, 2, 1), + PIN_FIELD_BASE(30, 30, 2, 0x0090, 0x10, 3, 1), + PIN_FIELD_BASE(31, 31, 2, 0x0090, 0x10, 4, 1), + PIN_FIELD_BASE(32, 32, 2, 0x0090, 0x10, 5, 1), + PIN_FIELD_BASE(33, 33, 2, 0x0090, 0x10, 6, 1), + PIN_FIELD_BASE(34, 34, 2, 0x0090, 0x10, 7, 1), + PIN_FIELD_BASE(35, 35, 4, 0x00b0, 0x10, 4, 1), + PIN_FIELD_BASE(36, 36, 8, 0x00b0, 0x10, 0, 1), + PIN_FIELD_BASE(37, 37, 8, 0x00b0, 0x10, 1, 1), + PIN_FIELD_BASE(38, 38, 8, 0x00b0, 0x10, 2, 1), + PIN_FIELD_BASE(39, 39, 8, 0x00b0, 0x10, 3, 1), + PIN_FIELD_BASE(40, 40, 1, 0x0090, 0x10, 11, 1), + PIN_FIELD_BASE(41, 41, 1, 0x0090, 0x10, 8, 1), + PIN_FIELD_BASE(42, 42, 1, 0x0090, 0x10, 10, 1), + PIN_FIELD_BASE(43, 43, 1, 0x0090, 0x10, 12, 1), + PIN_FIELD_BASE(44, 44, 1, 0x0090, 0x10, 9, 1), + PIN_FIELD_BASE(45, 45, 5, 0x00a0, 0x10, 17, 1), + PIN_FIELD_BASE(46, 46, 5, 0x00a0, 0x10, 19, 1), + PIN_FIELD_BASE(47, 47, 5, 0x00a0, 0x10, 20, 1), + PIN_FIELD_BASE(48, 48, 5, 0x00a0, 0x10, 18, 1), + PIN_FIELD_BASE(49, 49, 4, 0x00b0, 0x10, 20, 1), + PIN_FIELD_BASE(50, 50, 4, 0x00b0, 0x10, 19, 1), + PIN_FIELD_BASE(51, 51, 1, 0x0090, 0x10, 28, 1), + PIN_FIELD_BASE(52, 52, 1, 0x0090, 0x10, 27, 1), + PIN_FIELD_BASE(53, 53, 5, 0x00a0, 0x10, 25, 1), + PIN_FIELD_BASE(54, 54, 5, 0x00a0, 0x10, 21, 1), + PIN_FIELD_BASE(55, 55, 5, 0x00a0, 0x10, 24, 1), + PIN_FIELD_BASE(56, 56, 5, 0x00a0, 0x10, 22, 1), + PIN_FIELD_BASE(57, 57, 5, 0x00a0, 0x10, 23, 1), + PIN_FIELD_BASE(58, 58, 3, 0x00a0, 0x10, 21, 1), + PIN_FIELD_BASE(59, 59, 3, 0x00a0, 0x10, 22, 1), + PIN_FIELD_BASE(60, 60, 3, 0x00a0, 0x10, 24, 1), + PIN_FIELD_BASE(61, 61, 3, 0x00a0, 0x10, 23, 1), + PIN_FIELD_BASE(62, 62, 8, 0x00b0, 0x10, 19, 1), + PIN_FIELD_BASE(63, 63, 8, 0x00b0, 0x10, 20, 1), + PIN_FIELD_BASE(64, 64, 8, 0x00b0, 0x10, 22, 1), + PIN_FIELD_BASE(65, 65, 8, 0x00b0, 0x10, 21, 1), + PIN_FIELD_BASE(66, 66, 1, 0x0090, 0x10, 17, 1), + PIN_FIELD_BASE(67, 67, 1, 0x0090, 0x10, 18, 1), + PIN_FIELD_BASE(68, 68, 1, 0x0090, 0x10, 20, 1), + PIN_FIELD_BASE(69, 69, 1, 0x0090, 0x10, 19, 1), + PIN_FIELD_BASE(70, 70, 1, 0x0090, 0x10, 21, 1), + PIN_FIELD_BASE(71, 71, 1, 0x0090, 0x10, 22, 1), + PIN_FIELD_BASE(72, 72, 1, 0x0090, 0x10, 24, 1), + PIN_FIELD_BASE(73, 73, 1, 0x0090, 0x10, 23, 1), + PIN_FIELD_BASE(74, 74, 1, 0x0090, 0x10, 13, 1), + PIN_FIELD_BASE(75, 75, 1, 0x0090, 0x10, 14, 1), + PIN_FIELD_BASE(76, 76, 1, 0x0090, 0x10, 16, 1), + PIN_FIELD_BASE(77, 77, 1, 0x0090, 0x10, 15, 1), + PIN_FIELD_BASE(78, 78, 3, 0x00a0, 0x10, 25, 1), + PIN_FIELD_BASE(79, 79, 3, 0x00a0, 0x10, 26, 1), + PIN_FIELD_BASE(80, 80, 3, 0x00a0, 0x10, 28, 1), + PIN_FIELD_BASE(81, 81, 3, 0x00a0, 0x10, 27, 1), + PIN_FIELD_BASE(94, 94, 4, 0x00b0, 0x10, 7, 1), + PIN_FIELD_BASE(95, 95, 4, 0x00b0, 0x10, 8, 1), + PIN_FIELD_BASE(96, 96, 4, 0x00b0, 0x10, 6, 1), + PIN_FIELD_BASE(97, 97, 4, 0x00b0, 0x10, 9, 1), + PIN_FIELD_BASE(98, 98, 5, 0x00a0, 0x10, 8, 1), + PIN_FIELD_BASE(99, 99, 9, 0x0080, 0x10, 0, 1), + PIN_FIELD_BASE(100, 100, 9, 0x0080, 0x10, 1, 1), + PIN_FIELD_BASE(101, 101, 9, 0x0080, 0x10, 2, 1), + PIN_FIELD_BASE(102, 102, 9, 0x0080, 0x10, 3, 1), + PIN_FIELD_BASE(103, 103, 9, 0x0080, 0x10, 4, 1), + PIN_FIELD_BASE(104, 104, 9, 0x0080, 0x10, 5, 1), + PIN_FIELD_BASE(105, 105, 9, 0x0080, 0x10, 6, 1), + PIN_FIELD_BASE(106, 106, 5, 0x00a0, 0x10, 0, 1), + PIN_FIELD_BASE(107, 107, 4, 0x00b0, 0x10, 0, 1), + PIN_FIELD_BASE(108, 108, 4, 0x00b0, 0x10, 1, 1), + PIN_FIELD_BASE(109, 109, 5, 0x00a0, 0x10, 1, 1), + PIN_FIELD_BASE(110, 110, 5, 0x00a0, 0x10, 2, 1), + PIN_FIELD_BASE(111, 111, 5, 0x00a0, 0x10, 3, 1), + PIN_FIELD_BASE(112, 112, 5, 0x00a0, 0x10, 4, 1), + PIN_FIELD_BASE(113, 113, 4, 0x00b0, 0x10, 2, 1), + PIN_FIELD_BASE(114, 114, 4, 0x00b0, 0x10, 3, 1), + PIN_FIELD_BASE(115, 115, 5, 0x00a0, 0x10, 5, 1), + PIN_FIELD_BASE(116, 116, 4, 0x00b0, 0x10, 10, 1), + PIN_FIELD_BASE(117, 117, 4, 0x00b0, 0x10, 5, 1), + PIN_FIELD_BASE(118, 118, 3, 0x00a0, 0x10, 4, 1), + PIN_FIELD_BASE(119, 119, 3, 0x00a0, 0x10, 0, 1), + PIN_FIELD_BASE(120, 120, 3, 0x00a0, 0x10, 5, 1), + PIN_FIELD_BASE(121, 121, 3, 0x00a0, 0x10, 6, 1), + PIN_FIELD_BASE(122, 122, 7, 0x0070, 0x10, 9, 1), + PIN_FIELD_BASE(123, 123, 3, 0x00a0, 0x10, 7, 1), + PIN_FIELD_BASE(124, 124, 1, 0x0090, 0x10, 26, 1), + PIN_FIELD_BASE(125, 125, 7, 0x0070, 0x10, 10, 1), + PIN_FIELD_BASE(126, 126, 2, 0x0090, 0x10, 15, 1), + PIN_FIELD_BASE(127, 127, 2, 0x0090, 0x10, 16, 1), + PIN_FIELD_BASE(128, 128, 2, 0x0090, 0x10, 17, 1), + PIN_FIELD_BASE(129, 129, 2, 0x0090, 0x10, 18, 1), + PIN_FIELD_BASE(130, 130, 3, 0x00a0, 0x10, 8, 1), + PIN_FIELD_BASE(131, 131, 3, 0x00a0, 0x10, 9, 1), + PIN_FIELD_BASE(132, 132, 3, 0x00a0, 0x10, 10, 1), + PIN_FIELD_BASE(133, 133, 3, 0x00a0, 0x10, 11, 1), + PIN_FIELD_BASE(134, 134, 3, 0x00a0, 0x10, 12, 1), + PIN_FIELD_BASE(135, 135, 8, 0x00b0, 0x10, 13, 1), + PIN_FIELD_BASE(136, 136, 8, 0x00b0, 0x10, 14, 1), + PIN_FIELD_BASE(137, 137, 7, 0x0070, 0x10, 5, 1), + PIN_FIELD_BASE(138, 138, 7, 0x0070, 0x10, 6, 1), + PIN_FIELD_BASE(139, 139, 3, 0x00a0, 0x10, 13, 1), + PIN_FIELD_BASE(140, 140, 3, 0x00a0, 0x10, 17, 1), + PIN_FIELD_BASE(141, 141, 3, 0x00a0, 0x10, 14, 1), + PIN_FIELD_BASE(142, 142, 3, 0x00a0, 0x10, 18, 1), + PIN_FIELD_BASE(143, 143, 3, 0x00a0, 0x10, 2, 1), + PIN_FIELD_BASE(144, 144, 3, 0x00a0, 0x10, 3, 1), + PIN_FIELD_BASE(145, 145, 3, 0x00a0, 0x10, 15, 1), + PIN_FIELD_BASE(146, 146, 3, 0x00a0, 0x10, 19, 1), + PIN_FIELD_BASE(147, 147, 2, 0x0090, 0x10, 8, 1), + PIN_FIELD_BASE(148, 148, 2, 0x0090, 0x10, 11, 1), + PIN_FIELD_BASE(149, 149, 5, 0x00a0, 0x10, 6, 1), + PIN_FIELD_BASE(150, 150, 5, 0x00a0, 0x10, 7, 1), + PIN_FIELD_BASE(151, 151, 3, 0x00a0, 0x10, 16, 1), + PIN_FIELD_BASE(152, 152, 3, 0x00a0, 0x10, 20, 1), + PIN_FIELD_BASE(153, 153, 2, 0x0090, 0x10, 9, 1), + PIN_FIELD_BASE(154, 154, 2, 0x0090, 0x10, 12, 1), + PIN_FIELD_BASE(155, 155, 2, 0x0090, 0x10, 10, 1), + PIN_FIELD_BASE(156, 156, 2, 0x0090, 0x10, 13, 1), + PIN_FIELD_BASE(157, 157, 8, 0x00b0, 0x10, 15, 1), + PIN_FIELD_BASE(158, 158, 8, 0x00b0, 0x10, 17, 1), + PIN_FIELD_BASE(159, 159, 8, 0x00b0, 0x10, 16, 1), + PIN_FIELD_BASE(160, 160, 8, 0x00b0, 0x10, 18, 1), + PIN_FIELD_BASE(161, 161, 5, 0x00a0, 0x10, 26, 1), + PIN_FIELD_BASE(162, 162, 5, 0x00a0, 0x10, 28, 1), + PIN_FIELD_BASE(163, 163, 5, 0x00a0, 0x10, 27, 1), + PIN_FIELD_BASE(164, 164, 5, 0x00a0, 0x10, 29, 1), + PIN_FIELD_BASE(165, 165, 4, 0x00b0, 0x10, 11, 1), + PIN_FIELD_BASE(166, 166, 4, 0x00b0, 0x10, 12, 1), + PIN_FIELD_BASE(167, 167, 4, 0x00b0, 0x10, 13, 1), + PIN_FIELD_BASE(168, 168, 4, 0x00b0, 0x10, 14, 1), + PIN_FIELD_BASE(169, 169, 4, 0x00b0, 0x10, 15, 1), + PIN_FIELD_BASE(170, 170, 4, 0x00b0, 0x10, 16, 1), + PIN_FIELD_BASE(171, 171, 4, 0x00b0, 0x10, 17, 1), + PIN_FIELD_BASE(172, 172, 4, 0x00b0, 0x10, 18, 1), + PIN_FIELD_BASE(173, 173, 1, 0x0090, 0x10, 0, 1), + PIN_FIELD_BASE(174, 174, 1, 0x0090, 0x10, 7, 1), + PIN_FIELD_BASE(175, 175, 1, 0x0090, 0x10, 3, 1), + PIN_FIELD_BASE(176, 176, 1, 0x0090, 0x10, 4, 1), + PIN_FIELD_BASE(177, 177, 1, 0x0090, 0x10, 5, 1), + PIN_FIELD_BASE(178, 178, 1, 0x0090, 0x10, 6, 1), + PIN_FIELD_BASE(179, 179, 1, 0x0090, 0x10, 1, 1), + PIN_FIELD_BASE(180, 180, 1, 0x0090, 0x10, 2, 1), + PIN_FIELD_BASE(181, 181, 1, 0x0090, 0x10, 25, 1), + PIN_FIELD_BASE(182, 182, 9, 0x0080, 0x10, 11, 1), + PIN_FIELD_BASE(183, 183, 9, 0x0080, 0x10, 13, 1), + PIN_FIELD_BASE(184, 184, 9, 0x0080, 0x10, 7, 1), + PIN_FIELD_BASE(185, 185, 9, 0x0080, 0x10, 8, 1), + PIN_FIELD_BASE(186, 186, 9, 0x0080, 0x10, 9, 1), + PIN_FIELD_BASE(187, 187, 9, 0x0080, 0x10, 15, 1), + PIN_FIELD_BASE(188, 188, 9, 0x0080, 0x10, 16, 1), + PIN_FIELD_BASE(189, 189, 9, 0x0080, 0x10, 17, 1), + PIN_FIELD_BASE(190, 190, 9, 0x0080, 0x10, 18, 1), + PIN_FIELD_BASE(191, 191, 9, 0x0080, 0x10, 12, 1), + PIN_FIELD_BASE(192, 192, 9, 0x0080, 0x10, 14, 1), + PIN_FIELD_BASE(193, 193, 9, 0x0080, 0x10, 10, 1), + PIN_FIELD_BASE(194, 194, 9, 0x0080, 0x10, 19, 1), + PIN_FIELD_BASE(195, 195, 9, 0x0080, 0x10, 20, 1), + PIN_FIELD_BASE(196, 196, 6, 0x0080, 0x10, 0, 1), +}; + +static const struct mtk_pin_field_calc mt6858_pin_pd_range[] = { + PIN_FIELD_BASE(0, 0, 8, 0x0090, 0x10, 4, 1), + PIN_FIELD_BASE(1, 1, 8, 0x0090, 0x10, 5, 1), + PIN_FIELD_BASE(2, 2, 8, 0x0090, 0x10, 6, 1), + PIN_FIELD_BASE(3, 3, 8, 0x0090, 0x10, 8, 1), + PIN_FIELD_BASE(4, 4, 8, 0x0090, 0x10, 9, 1), + PIN_FIELD_BASE(5, 5, 8, 0x0090, 0x10, 10, 1), + PIN_FIELD_BASE(6, 6, 8, 0x0090, 0x10, 11, 1), + PIN_FIELD_BASE(7, 7, 8, 0x0090, 0x10, 12, 1), + PIN_FIELD_BASE(8, 8, 5, 0x0090, 0x10, 15, 1), + PIN_FIELD_BASE(9, 9, 5, 0x0090, 0x10, 16, 1), + PIN_FIELD_BASE(10, 10, 5, 0x0090, 0x10, 9, 1), + PIN_FIELD_BASE(11, 11, 5, 0x0090, 0x10, 10, 1), + PIN_FIELD_BASE(12, 12, 5, 0x0090, 0x10, 11, 1), + PIN_FIELD_BASE(13, 13, 7, 0x0060, 0x10, 0, 1), + PIN_FIELD_BASE(14, 14, 7, 0x0060, 0x10, 1, 1), + PIN_FIELD_BASE(15, 15, 7, 0x0060, 0x10, 2, 1), + PIN_FIELD_BASE(16, 16, 7, 0x0060, 0x10, 3, 1), + PIN_FIELD_BASE(17, 17, 7, 0x0060, 0x10, 4, 1), + PIN_FIELD_BASE(21, 21, 5, 0x0090, 0x10, 12, 1), + PIN_FIELD_BASE(22, 22, 5, 0x0090, 0x10, 13, 1), + PIN_FIELD_BASE(23, 23, 8, 0x0090, 0x10, 7, 1), + PIN_FIELD_BASE(24, 24, 5, 0x0090, 0x10, 14, 1), + PIN_FIELD_BASE(25, 25, 2, 0x0080, 0x10, 14, 1), + PIN_FIELD_BASE(26, 26, 3, 0x0090, 0x10, 1, 1), + PIN_FIELD_BASE(27, 27, 2, 0x0080, 0x10, 0, 1), + PIN_FIELD_BASE(28, 28, 2, 0x0080, 0x10, 1, 1), + PIN_FIELD_BASE(29, 29, 2, 0x0080, 0x10, 2, 1), + PIN_FIELD_BASE(30, 30, 2, 0x0080, 0x10, 3, 1), + PIN_FIELD_BASE(31, 31, 2, 0x0080, 0x10, 4, 1), + PIN_FIELD_BASE(32, 32, 2, 0x0080, 0x10, 5, 1), + PIN_FIELD_BASE(33, 33, 2, 0x0080, 0x10, 6, 1), + PIN_FIELD_BASE(34, 34, 2, 0x0080, 0x10, 7, 1), + PIN_FIELD_BASE(35, 35, 4, 0x0090, 0x10, 4, 1), + PIN_FIELD_BASE(36, 36, 8, 0x0090, 0x10, 0, 1), + PIN_FIELD_BASE(37, 37, 8, 0x0090, 0x10, 1, 1), + PIN_FIELD_BASE(38, 38, 8, 0x0090, 0x10, 2, 1), + PIN_FIELD_BASE(39, 39, 8, 0x0090, 0x10, 3, 1), + PIN_FIELD_BASE(40, 40, 1, 0x0080, 0x10, 11, 1), + PIN_FIELD_BASE(41, 41, 1, 0x0080, 0x10, 8, 1), + PIN_FIELD_BASE(42, 42, 1, 0x0080, 0x10, 10, 1), + PIN_FIELD_BASE(43, 43, 1, 0x0080, 0x10, 12, 1), + PIN_FIELD_BASE(44, 44, 1, 0x0080, 0x10, 9, 1), + PIN_FIELD_BASE(45, 45, 5, 0x0090, 0x10, 17, 1), + PIN_FIELD_BASE(46, 46, 5, 0x0090, 0x10, 19, 1), + PIN_FIELD_BASE(47, 47, 5, 0x0090, 0x10, 20, 1), + PIN_FIELD_BASE(48, 48, 5, 0x0090, 0x10, 18, 1), + PIN_FIELD_BASE(49, 49, 4, 0x0090, 0x10, 20, 1), + PIN_FIELD_BASE(50, 50, 4, 0x0090, 0x10, 19, 1), + PIN_FIELD_BASE(51, 51, 1, 0x0080, 0x10, 28, 1), + PIN_FIELD_BASE(52, 52, 1, 0x0080, 0x10, 27, 1), + PIN_FIELD_BASE(53, 53, 5, 0x0090, 0x10, 25, 1), + PIN_FIELD_BASE(54, 54, 5, 0x0090, 0x10, 21, 1), + PIN_FIELD_BASE(55, 55, 5, 0x0090, 0x10, 24, 1), + PIN_FIELD_BASE(56, 56, 5, 0x0090, 0x10, 22, 1), + PIN_FIELD_BASE(57, 57, 5, 0x0090, 0x10, 23, 1), + PIN_FIELD_BASE(58, 58, 3, 0x0090, 0x10, 21, 1), + PIN_FIELD_BASE(59, 59, 3, 0x0090, 0x10, 22, 1), + PIN_FIELD_BASE(60, 60, 3, 0x0090, 0x10, 24, 1), + PIN_FIELD_BASE(61, 61, 3, 0x0090, 0x10, 23, 1), + PIN_FIELD_BASE(62, 62, 8, 0x0090, 0x10, 19, 1), + PIN_FIELD_BASE(63, 63, 8, 0x0090, 0x10, 20, 1), + PIN_FIELD_BASE(64, 64, 8, 0x0090, 0x10, 22, 1), + PIN_FIELD_BASE(65, 65, 8, 0x0090, 0x10, 21, 1), + PIN_FIELD_BASE(66, 66, 1, 0x0080, 0x10, 17, 1), + PIN_FIELD_BASE(67, 67, 1, 0x0080, 0x10, 18, 1), + PIN_FIELD_BASE(68, 68, 1, 0x0080, 0x10, 20, 1), + PIN_FIELD_BASE(69, 69, 1, 0x0080, 0x10, 19, 1), + PIN_FIELD_BASE(70, 70, 1, 0x0080, 0x10, 21, 1), + PIN_FIELD_BASE(71, 71, 1, 0x0080, 0x10, 22, 1), + PIN_FIELD_BASE(72, 72, 1, 0x0080, 0x10, 24, 1), + PIN_FIELD_BASE(73, 73, 1, 0x0080, 0x10, 23, 1), + PIN_FIELD_BASE(74, 74, 1, 0x0080, 0x10, 13, 1), + PIN_FIELD_BASE(75, 75, 1, 0x0080, 0x10, 14, 1), + PIN_FIELD_BASE(76, 76, 1, 0x0080, 0x10, 16, 1), + PIN_FIELD_BASE(77, 77, 1, 0x0080, 0x10, 15, 1), + PIN_FIELD_BASE(78, 78, 3, 0x0090, 0x10, 25, 1), + PIN_FIELD_BASE(79, 79, 3, 0x0090, 0x10, 26, 1), + PIN_FIELD_BASE(80, 80, 3, 0x0090, 0x10, 28, 1), + PIN_FIELD_BASE(81, 81, 3, 0x0090, 0x10, 27, 1), + PIN_FIELD_BASE(94, 94, 4, 0x0090, 0x10, 7, 1), + PIN_FIELD_BASE(95, 95, 4, 0x0090, 0x10, 8, 1), + PIN_FIELD_BASE(96, 96, 4, 0x0090, 0x10, 6, 1), + PIN_FIELD_BASE(97, 97, 4, 0x0090, 0x10, 9, 1), + PIN_FIELD_BASE(98, 98, 5, 0x0090, 0x10, 8, 1), + PIN_FIELD_BASE(99, 99, 9, 0x0070, 0x10, 0, 1), + PIN_FIELD_BASE(100, 100, 9, 0x0070, 0x10, 1, 1), + PIN_FIELD_BASE(101, 101, 9, 0x0070, 0x10, 2, 1), + PIN_FIELD_BASE(102, 102, 9, 0x0070, 0x10, 3, 1), + PIN_FIELD_BASE(103, 103, 9, 0x0070, 0x10, 4, 1), + PIN_FIELD_BASE(104, 104, 9, 0x0070, 0x10, 5, 1), + PIN_FIELD_BASE(105, 105, 9, 0x0070, 0x10, 6, 1), + PIN_FIELD_BASE(106, 106, 5, 0x0090, 0x10, 0, 1), + PIN_FIELD_BASE(107, 107, 4, 0x0090, 0x10, 0, 1), + PIN_FIELD_BASE(108, 108, 4, 0x0090, 0x10, 1, 1), + PIN_FIELD_BASE(109, 109, 5, 0x0090, 0x10, 1, 1), + PIN_FIELD_BASE(110, 110, 5, 0x0090, 0x10, 2, 1), + PIN_FIELD_BASE(111, 111, 5, 0x0090, 0x10, 3, 1), + PIN_FIELD_BASE(112, 112, 5, 0x0090, 0x10, 4, 1), + PIN_FIELD_BASE(113, 113, 4, 0x0090, 0x10, 2, 1), + PIN_FIELD_BASE(114, 114, 4, 0x0090, 0x10, 3, 1), + PIN_FIELD_BASE(115, 115, 5, 0x0090, 0x10, 5, 1), + PIN_FIELD_BASE(116, 116, 4, 0x0090, 0x10, 10, 1), + PIN_FIELD_BASE(117, 117, 4, 0x0090, 0x10, 5, 1), + PIN_FIELD_BASE(118, 118, 3, 0x0090, 0x10, 4, 1), + PIN_FIELD_BASE(119, 119, 3, 0x0090, 0x10, 0, 1), + PIN_FIELD_BASE(120, 120, 3, 0x0090, 0x10, 5, 1), + PIN_FIELD_BASE(121, 121, 3, 0x0090, 0x10, 6, 1), + PIN_FIELD_BASE(122, 122, 7, 0x0060, 0x10, 9, 1), + PIN_FIELD_BASE(123, 123, 3, 0x0090, 0x10, 7, 1), + PIN_FIELD_BASE(124, 124, 1, 0x0080, 0x10, 26, 1), + PIN_FIELD_BASE(125, 125, 7, 0x0060, 0x10, 10, 1), + PIN_FIELD_BASE(126, 126, 2, 0x0080, 0x10, 15, 1), + PIN_FIELD_BASE(127, 127, 2, 0x0080, 0x10, 16, 1), + PIN_FIELD_BASE(128, 128, 2, 0x0080, 0x10, 17, 1), + PIN_FIELD_BASE(129, 129, 2, 0x0080, 0x10, 18, 1), + PIN_FIELD_BASE(130, 130, 3, 0x0090, 0x10, 8, 1), + PIN_FIELD_BASE(131, 131, 3, 0x0090, 0x10, 9, 1), + PIN_FIELD_BASE(132, 132, 3, 0x0090, 0x10, 10, 1), + PIN_FIELD_BASE(133, 133, 3, 0x0090, 0x10, 11, 1), + PIN_FIELD_BASE(134, 134, 3, 0x0090, 0x10, 12, 1), + PIN_FIELD_BASE(135, 135, 8, 0x0090, 0x10, 13, 1), + PIN_FIELD_BASE(136, 136, 8, 0x0090, 0x10, 14, 1), + PIN_FIELD_BASE(137, 137, 7, 0x0060, 0x10, 5, 1), + PIN_FIELD_BASE(138, 138, 7, 0x0060, 0x10, 6, 1), + PIN_FIELD_BASE(139, 139, 3, 0x0090, 0x10, 13, 1), + PIN_FIELD_BASE(140, 140, 3, 0x0090, 0x10, 17, 1), + PIN_FIELD_BASE(141, 141, 3, 0x0090, 0x10, 14, 1), + PIN_FIELD_BASE(142, 142, 3, 0x0090, 0x10, 18, 1), + PIN_FIELD_BASE(143, 143, 3, 0x0090, 0x10, 2, 1), + PIN_FIELD_BASE(144, 144, 3, 0x0090, 0x10, 3, 1), + PIN_FIELD_BASE(145, 145, 3, 0x0090, 0x10, 15, 1), + PIN_FIELD_BASE(146, 146, 3, 0x0090, 0x10, 19, 1), + PIN_FIELD_BASE(147, 147, 2, 0x0080, 0x10, 8, 1), + PIN_FIELD_BASE(148, 148, 2, 0x0080, 0x10, 11, 1), + PIN_FIELD_BASE(149, 149, 5, 0x0090, 0x10, 6, 1), + PIN_FIELD_BASE(150, 150, 5, 0x0090, 0x10, 7, 1), + PIN_FIELD_BASE(151, 151, 3, 0x0090, 0x10, 16, 1), + PIN_FIELD_BASE(152, 152, 3, 0x0090, 0x10, 20, 1), + PIN_FIELD_BASE(153, 153, 2, 0x0080, 0x10, 9, 1), + PIN_FIELD_BASE(154, 154, 2, 0x0080, 0x10, 12, 1), + PIN_FIELD_BASE(155, 155, 2, 0x0080, 0x10, 10, 1), + PIN_FIELD_BASE(156, 156, 2, 0x0080, 0x10, 13, 1), + PIN_FIELD_BASE(157, 157, 8, 0x0090, 0x10, 15, 1), + PIN_FIELD_BASE(158, 158, 8, 0x0090, 0x10, 17, 1), + PIN_FIELD_BASE(159, 159, 8, 0x0090, 0x10, 16, 1), + PIN_FIELD_BASE(160, 160, 8, 0x0090, 0x10, 18, 1), + PIN_FIELD_BASE(161, 161, 5, 0x0090, 0x10, 26, 1), + PIN_FIELD_BASE(162, 162, 5, 0x0090, 0x10, 28, 1), + PIN_FIELD_BASE(163, 163, 5, 0x0090, 0x10, 27, 1), + PIN_FIELD_BASE(164, 164, 5, 0x0090, 0x10, 29, 1), + PIN_FIELD_BASE(165, 165, 4, 0x0090, 0x10, 11, 1), + PIN_FIELD_BASE(166, 166, 4, 0x0090, 0x10, 12, 1), + PIN_FIELD_BASE(167, 167, 4, 0x0090, 0x10, 13, 1), + PIN_FIELD_BASE(168, 168, 4, 0x0090, 0x10, 14, 1), + PIN_FIELD_BASE(169, 169, 4, 0x0090, 0x10, 15, 1), + PIN_FIELD_BASE(170, 170, 4, 0x0090, 0x10, 16, 1), + PIN_FIELD_BASE(171, 171, 4, 0x0090, 0x10, 17, 1), + PIN_FIELD_BASE(172, 172, 4, 0x0090, 0x10, 18, 1), + PIN_FIELD_BASE(173, 173, 1, 0x0080, 0x10, 0, 1), + PIN_FIELD_BASE(174, 174, 1, 0x0080, 0x10, 7, 1), + PIN_FIELD_BASE(175, 175, 1, 0x0080, 0x10, 3, 1), + PIN_FIELD_BASE(176, 176, 1, 0x0080, 0x10, 4, 1), + PIN_FIELD_BASE(177, 177, 1, 0x0080, 0x10, 5, 1), + PIN_FIELD_BASE(178, 178, 1, 0x0080, 0x10, 6, 1), + PIN_FIELD_BASE(179, 179, 1, 0x0080, 0x10, 1, 1), + PIN_FIELD_BASE(180, 180, 1, 0x0080, 0x10, 2, 1), + PIN_FIELD_BASE(181, 181, 1, 0x0080, 0x10, 25, 1), + PIN_FIELD_BASE(182, 182, 9, 0x0070, 0x10, 11, 1), + PIN_FIELD_BASE(183, 183, 9, 0x0070, 0x10, 13, 1), + PIN_FIELD_BASE(184, 184, 9, 0x0070, 0x10, 7, 1), + PIN_FIELD_BASE(185, 185, 9, 0x0070, 0x10, 8, 1), + PIN_FIELD_BASE(186, 186, 9, 0x0070, 0x10, 9, 1), + PIN_FIELD_BASE(187, 187, 9, 0x0070, 0x10, 15, 1), + PIN_FIELD_BASE(188, 188, 9, 0x0070, 0x10, 16, 1), + PIN_FIELD_BASE(189, 189, 9, 0x0070, 0x10, 17, 1), + PIN_FIELD_BASE(190, 190, 9, 0x0070, 0x10, 18, 1), + PIN_FIELD_BASE(191, 191, 9, 0x0070, 0x10, 12, 1), + PIN_FIELD_BASE(192, 192, 9, 0x0070, 0x10, 14, 1), + PIN_FIELD_BASE(193, 193, 9, 0x0070, 0x10, 10, 1), + PIN_FIELD_BASE(194, 194, 9, 0x0070, 0x10, 19, 1), + PIN_FIELD_BASE(195, 195, 9, 0x0070, 0x10, 20, 1), + PIN_FIELD_BASE(196, 196, 6, 0x0060, 0x10, 0, 1), +}; + +static const struct mtk_pin_field_calc mt6858_pin_pupd_range[] = { + PIN_FIELD_BASE(18, 18, 6, 0x0070, 0x10, 0, 1), + PIN_FIELD_BASE(19, 19, 6, 0x0070, 0x10, 1, 1), + PIN_FIELD_BASE(20, 20, 6, 0x0070, 0x10, 2, 1), + PIN_FIELD_BASE(82, 82, 8, 0x00a0, 0x10, 0, 1), + PIN_FIELD_BASE(83, 83, 8, 0x00a0, 0x10, 1, 1), + PIN_FIELD_BASE(84, 84, 8, 0x00a0, 0x10, 2, 1), + PIN_FIELD_BASE(85, 85, 8, 0x00a0, 0x10, 3, 1), + PIN_FIELD_BASE(86, 86, 8, 0x00a0, 0x10, 4, 1), + PIN_FIELD_BASE(87, 87, 8, 0x00a0, 0x10, 5, 1), + PIN_FIELD_BASE(88, 88, 4, 0x00a0, 0x10, 0, 1), + PIN_FIELD_BASE(89, 89, 4, 0x00a0, 0x10, 2, 1), + PIN_FIELD_BASE(90, 90, 4, 0x00a0, 0x10, 1, 1), + PIN_FIELD_BASE(91, 91, 4, 0x00a0, 0x10, 3, 1), + PIN_FIELD_BASE(92, 92, 4, 0x00a0, 0x10, 5, 1), + PIN_FIELD_BASE(93, 93, 4, 0x00a0, 0x10, 4, 1), +}; + +static const struct mtk_pin_field_calc mt6858_pin_r0_range[] = { + PIN_FIELD_BASE(18, 18, 6, 0x0090, 0x10, 0, 1), + PIN_FIELD_BASE(19, 19, 6, 0x0090, 0x10, 1, 1), + PIN_FIELD_BASE(20, 20, 6, 0x0090, 0x10, 2, 1), + PIN_FIELD_BASE(82, 82, 8, 0x00c0, 0x10, 0, 1), + PIN_FIELD_BASE(83, 83, 8, 0x00c0, 0x10, 1, 1), + PIN_FIELD_BASE(84, 84, 8, 0x00c0, 0x10, 2, 1), + PIN_FIELD_BASE(85, 85, 8, 0x00c0, 0x10, 3, 1), + PIN_FIELD_BASE(86, 86, 8, 0x00c0, 0x10, 4, 1), + PIN_FIELD_BASE(87, 87, 8, 0x00c0, 0x10, 5, 1), + PIN_FIELD_BASE(88, 88, 4, 0x00c0, 0x10, 0, 1), + PIN_FIELD_BASE(89, 89, 4, 0x00c0, 0x10, 2, 1), + PIN_FIELD_BASE(90, 90, 4, 0x00c0, 0x10, 1, 1), + PIN_FIELD_BASE(91, 91, 4, 0x00c0, 0x10, 3, 1), + PIN_FIELD_BASE(92, 92, 4, 0x00c0, 0x10, 5, 1), + PIN_FIELD_BASE(93, 93, 4, 0x00c0, 0x10, 4, 1), +}; + +static const struct mtk_pin_field_calc mt6858_pin_r1_range[] = { + PIN_FIELD_BASE(18, 18, 6, 0x00a0, 0x10, 0, 1), + PIN_FIELD_BASE(19, 19, 6, 0x00a0, 0x10, 1, 1), + PIN_FIELD_BASE(20, 20, 6, 0x00a0, 0x10, 2, 1), + PIN_FIELD_BASE(82, 82, 8, 0x00d0, 0x10, 0, 1), + PIN_FIELD_BASE(83, 83, 8, 0x00d0, 0x10, 1, 1), + PIN_FIELD_BASE(84, 84, 8, 0x00d0, 0x10, 2, 1), + PIN_FIELD_BASE(85, 85, 8, 0x00d0, 0x10, 3, 1), + PIN_FIELD_BASE(86, 86, 8, 0x00d0, 0x10, 4, 1), + PIN_FIELD_BASE(87, 87, 8, 0x00d0, 0x10, 5, 1), + PIN_FIELD_BASE(88, 88, 4, 0x00d0, 0x10, 0, 1), + PIN_FIELD_BASE(89, 89, 4, 0x00d0, 0x10, 2, 1), + PIN_FIELD_BASE(90, 90, 4, 0x00d0, 0x10, 1, 1), + PIN_FIELD_BASE(91, 91, 4, 0x00d0, 0x10, 3, 1), + PIN_FIELD_BASE(92, 92, 4, 0x00d0, 0x10, 5, 1), + PIN_FIELD_BASE(93, 93, 4, 0x00d0, 0x10, 4, 1), +}; + +static const struct mtk_pin_field_calc mt6858_pin_drv_range[] = { + PIN_FIELD_BASE(0, 0, 8, 0x0000, 0x10, 12, 3), + PIN_FIELD_BASE(1, 1, 8, 0x0000, 0x10, 15, 3), + PIN_FIELD_BASE(2, 2, 8, 0x0000, 0x10, 21, 3), + PIN_FIELD_BASE(3, 3, 8, 0x0000, 0x10, 24, 3), + PIN_FIELD_BASE(4, 4, 8, 0x0000, 0x10, 27, 3), + PIN_FIELD_BASE(5, 5, 8, 0x0010, 0x10, 0, 3), + PIN_FIELD_BASE(6, 6, 8, 0x0010, 0x10, 3, 3), + PIN_FIELD_BASE(7, 7, 8, 0x0010, 0x10, 6, 3), + PIN_FIELD_BASE(8, 8, 5, 0x0010, 0x10, 15, 3), + PIN_FIELD_BASE(9, 9, 5, 0x0010, 0x10, 18, 3), + PIN_FIELD_BASE(10, 10, 5, 0x0000, 0x10, 27, 3), + PIN_FIELD_BASE(11, 11, 5, 0x0010, 0x10, 0, 3), + PIN_FIELD_BASE(12, 12, 5, 0x0010, 0x10, 3, 3), + PIN_FIELD_BASE(13, 13, 7, 0x0000, 0x10, 0, 3), + PIN_FIELD_BASE(14, 14, 7, 0x0000, 0x10, 3, 3), + PIN_FIELD_BASE(15, 15, 7, 0x0000, 0x10, 6, 3), + PIN_FIELD_BASE(16, 16, 7, 0x0000, 0x10, 9, 3), + PIN_FIELD_BASE(17, 17, 7, 0x0000, 0x10, 12, 3), + PIN_FIELD_BASE(18, 18, 6, 0x0000, 0x10, 0, 3), + PIN_FIELD_BASE(19, 19, 6, 0x0000, 0x10, 3, 3), + PIN_FIELD_BASE(20, 20, 6, 0x0000, 0x10, 6, 3), + PIN_FIELD_BASE(21, 21, 5, 0x0010, 0x10, 6, 3), + PIN_FIELD_BASE(22, 22, 5, 0x0010, 0x10, 9, 3), + PIN_FIELD_BASE(23, 23, 8, 0x0000, 0x10, 18, 3), + PIN_FIELD_BASE(24, 24, 5, 0x0010, 0x10, 12, 3), + PIN_FIELD_BASE(25, 25, 2, 0x0010, 0x10, 12, 3), + PIN_FIELD_BASE(26, 26, 3, 0x0000, 0x10, 3, 3), + PIN_FIELD_BASE(27, 27, 2, 0x0000, 0x10, 0, 3), + PIN_FIELD_BASE(28, 28, 2, 0x0000, 0x10, 3, 3), + PIN_FIELD_BASE(29, 29, 2, 0x0000, 0x10, 6, 3), + PIN_FIELD_BASE(30, 30, 2, 0x0000, 0x10, 9, 3), + PIN_FIELD_BASE(31, 31, 2, 0x0000, 0x10, 12, 3), + PIN_FIELD_BASE(32, 32, 2, 0x0000, 0x10, 15, 3), + PIN_FIELD_BASE(33, 33, 2, 0x0000, 0x10, 18, 3), + PIN_FIELD_BASE(34, 34, 2, 0x0000, 0x10, 21, 3), + PIN_FIELD_BASE(35, 35, 4, 0x0000, 0x10, 12, 3), + PIN_FIELD_BASE(36, 36, 8, 0x0000, 0x10, 0, 3), + PIN_FIELD_BASE(37, 37, 8, 0x0000, 0x10, 3, 3), + PIN_FIELD_BASE(38, 38, 8, 0x0000, 0x10, 6, 3), + PIN_FIELD_BASE(39, 39, 8, 0x0000, 0x10, 9, 3), + PIN_FIELD_BASE(40, 40, 1, 0x0000, 0x10, 3, 3), + PIN_FIELD_BASE(41, 41, 1, 0x0000, 0x10, 3, 3), + PIN_FIELD_BASE(42, 42, 1, 0x0000, 0x10, 3, 3), + PIN_FIELD_BASE(43, 43, 1, 0x0000, 0x10, 3, 3), + PIN_FIELD_BASE(44, 44, 1, 0x0000, 0x10, 3, 3), + PIN_FIELD_BASE(45, 45, 5, 0x0010, 0x10, 21, 3), + PIN_FIELD_BASE(46, 46, 5, 0x0010, 0x10, 21, 3), + PIN_FIELD_BASE(47, 47, 5, 0x0010, 0x10, 21, 3), + PIN_FIELD_BASE(48, 48, 5, 0x0010, 0x10, 21, 3), + PIN_FIELD_BASE(49, 49, 4, 0x0010, 0x10, 24, 3), + PIN_FIELD_BASE(50, 50, 4, 0x0010, 0x10, 21, 3), + PIN_FIELD_BASE(51, 51, 1, 0x0010, 0x10, 21, 3), + PIN_FIELD_BASE(52, 52, 1, 0x0010, 0x10, 18, 3), + PIN_FIELD_BASE(53, 53, 5, 0x0020, 0x10, 6, 3), + PIN_FIELD_BASE(54, 54, 5, 0x0010, 0x10, 24, 3), + PIN_FIELD_BASE(55, 55, 5, 0x0020, 0x10, 3, 3), + PIN_FIELD_BASE(56, 56, 5, 0x0010, 0x10, 27, 3), + PIN_FIELD_BASE(57, 57, 5, 0x0020, 0x10, 0, 3), + PIN_FIELD_BASE(58, 58, 3, 0x0020, 0x10, 3, 3), + PIN_FIELD_BASE(59, 59, 3, 0x0020, 0x10, 6, 3), + PIN_FIELD_BASE(60, 60, 3, 0x0020, 0x10, 12, 3), + PIN_FIELD_BASE(61, 61, 3, 0x0020, 0x10, 9, 3), + PIN_FIELD_BASE(62, 62, 8, 0x0020, 0x10, 15, 3), + PIN_FIELD_BASE(63, 63, 8, 0x0020, 0x10, 18, 3), + PIN_FIELD_BASE(64, 64, 8, 0x0020, 0x10, 24, 3), + PIN_FIELD_BASE(65, 65, 8, 0x0020, 0x10, 21, 3), + PIN_FIELD_BASE(66, 66, 1, 0x0000, 0x10, 18, 3), + PIN_FIELD_BASE(67, 67, 1, 0x0000, 0x10, 21, 3), + PIN_FIELD_BASE(68, 68, 1, 0x0000, 0x10, 27, 3), + PIN_FIELD_BASE(69, 69, 1, 0x0000, 0x10, 24, 3), + PIN_FIELD_BASE(70, 70, 1, 0x0010, 0x10, 0, 3), + PIN_FIELD_BASE(71, 71, 1, 0x0010, 0x10, 3, 3), + PIN_FIELD_BASE(72, 72, 1, 0x0010, 0x10, 9, 3), + PIN_FIELD_BASE(73, 73, 1, 0x0010, 0x10, 6, 3), + PIN_FIELD_BASE(74, 74, 1, 0x0000, 0x10, 6, 3), + PIN_FIELD_BASE(75, 75, 1, 0x0000, 0x10, 9, 3), + PIN_FIELD_BASE(76, 76, 1, 0x0000, 0x10, 15, 3), + PIN_FIELD_BASE(77, 77, 1, 0x0000, 0x10, 12, 3), + PIN_FIELD_BASE(78, 78, 3, 0x0020, 0x10, 15, 3), + PIN_FIELD_BASE(79, 79, 3, 0x0020, 0x10, 18, 3), + PIN_FIELD_BASE(80, 80, 3, 0x0020, 0x10, 24, 3), + PIN_FIELD_BASE(81, 81, 3, 0x0020, 0x10, 21, 3), + PIN_FIELD_BASE(82, 82, 8, 0x0010, 0x10, 9, 3), + PIN_FIELD_BASE(83, 83, 8, 0x0010, 0x10, 12, 3), + PIN_FIELD_BASE(84, 84, 8, 0x0010, 0x10, 15, 3), + PIN_FIELD_BASE(85, 85, 8, 0x0010, 0x10, 18, 3), + PIN_FIELD_BASE(86, 86, 8, 0x0010, 0x10, 21, 3), + PIN_FIELD_BASE(87, 87, 8, 0x0010, 0x10, 24, 3), + PIN_FIELD_BASE(88, 88, 4, 0x0010, 0x10, 15, 3), + PIN_FIELD_BASE(89, 89, 4, 0x0010, 0x10, 15, 3), + PIN_FIELD_BASE(90, 90, 4, 0x0010, 0x10, 15, 3), + PIN_FIELD_BASE(91, 91, 4, 0x0010, 0x10, 18, 3), + PIN_FIELD_BASE(92, 92, 4, 0x0010, 0x10, 18, 3), + PIN_FIELD_BASE(93, 93, 4, 0x0010, 0x10, 18, 3), + PIN_FIELD_BASE(94, 94, 4, 0x0000, 0x10, 21, 3), + PIN_FIELD_BASE(95, 95, 4, 0x0000, 0x10, 24, 3), + PIN_FIELD_BASE(96, 96, 4, 0x0000, 0x10, 18, 3), + PIN_FIELD_BASE(97, 97, 4, 0x0000, 0x10, 27, 3), + PIN_FIELD_BASE(98, 98, 5, 0x0000, 0x10, 24, 3), + PIN_FIELD_BASE(99, 99, 9, 0x0000, 0x10, 0, 3), + PIN_FIELD_BASE(100, 100, 9, 0x0000, 0x10, 3, 3), + PIN_FIELD_BASE(101, 101, 9, 0x0000, 0x10, 6, 3), + PIN_FIELD_BASE(102, 102, 9, 0x0000, 0x10, 9, 3), + PIN_FIELD_BASE(103, 103, 9, 0x0000, 0x10, 12, 3), + PIN_FIELD_BASE(104, 104, 9, 0x0000, 0x10, 15, 3), + PIN_FIELD_BASE(105, 105, 9, 0x0000, 0x10, 18, 3), + PIN_FIELD_BASE(106, 106, 5, 0x0000, 0x10, 0, 3), + PIN_FIELD_BASE(107, 107, 4, 0x0000, 0x10, 0, 3), + PIN_FIELD_BASE(108, 108, 4, 0x0000, 0x10, 3, 3), + PIN_FIELD_BASE(109, 109, 5, 0x0000, 0x10, 3, 3), + PIN_FIELD_BASE(110, 110, 5, 0x0000, 0x10, 6, 3), + PIN_FIELD_BASE(111, 111, 5, 0x0000, 0x10, 9, 3), + PIN_FIELD_BASE(112, 112, 5, 0x0000, 0x10, 12, 3), + PIN_FIELD_BASE(113, 113, 4, 0x0000, 0x10, 6, 3), + PIN_FIELD_BASE(114, 114, 4, 0x0000, 0x10, 9, 3), + PIN_FIELD_BASE(115, 115, 5, 0x0000, 0x10, 15, 3), + PIN_FIELD_BASE(116, 116, 4, 0x0010, 0x10, 0, 3), + PIN_FIELD_BASE(117, 117, 4, 0x0000, 0x10, 15, 3), + PIN_FIELD_BASE(118, 118, 3, 0x0000, 0x10, 12, 3), + PIN_FIELD_BASE(119, 119, 3, 0x0000, 0x10, 0, 3), + PIN_FIELD_BASE(120, 120, 3, 0x0000, 0x10, 15, 3), + PIN_FIELD_BASE(121, 121, 3, 0x0000, 0x10, 18, 3), + PIN_FIELD_BASE(122, 122, 7, 0x0000, 0x10, 21, 3), + PIN_FIELD_BASE(123, 123, 3, 0x0000, 0x10, 21, 3), + PIN_FIELD_BASE(124, 124, 1, 0x0010, 0x10, 15, 3), + PIN_FIELD_BASE(125, 125, 7, 0x0000, 0x10, 24, 3), + PIN_FIELD_BASE(126, 126, 2, 0x0010, 0x10, 15, 3), + PIN_FIELD_BASE(127, 127, 2, 0x0010, 0x10, 18, 3), + PIN_FIELD_BASE(128, 128, 2, 0x0010, 0x10, 21, 3), + PIN_FIELD_BASE(129, 129, 2, 0x0010, 0x10, 24, 3), + PIN_FIELD_BASE(130, 130, 3, 0x0000, 0x10, 24, 3), + PIN_FIELD_BASE(131, 131, 3, 0x0000, 0x10, 27, 3), + PIN_FIELD_BASE(132, 132, 3, 0x0010, 0x10, 0, 3), + PIN_FIELD_BASE(133, 133, 3, 0x0010, 0x10, 3, 3), + PIN_FIELD_BASE(134, 134, 3, 0x0010, 0x10, 6, 3), + PIN_FIELD_BASE(135, 135, 8, 0x0010, 0x10, 27, 3), + PIN_FIELD_BASE(136, 136, 8, 0x0020, 0x10, 0, 3), + PIN_FIELD_BASE(137, 137, 7, 0x0000, 0x10, 15, 3), + PIN_FIELD_BASE(138, 138, 7, 0x0000, 0x10, 18, 3), + PIN_FIELD_BASE(139, 139, 3, 0x0010, 0x10, 9, 3), + PIN_FIELD_BASE(140, 140, 3, 0x0010, 0x10, 21, 3), + PIN_FIELD_BASE(141, 141, 3, 0x0010, 0x10, 12, 3), + PIN_FIELD_BASE(142, 142, 3, 0x0010, 0x10, 24, 3), + PIN_FIELD_BASE(143, 143, 3, 0x0000, 0x10, 6, 3), + PIN_FIELD_BASE(144, 144, 3, 0x0000, 0x10, 9, 3), + PIN_FIELD_BASE(145, 145, 3, 0x0010, 0x10, 15, 3), + PIN_FIELD_BASE(146, 146, 3, 0x0010, 0x10, 27, 3), + PIN_FIELD_BASE(147, 147, 2, 0x0000, 0x10, 24, 3), + PIN_FIELD_BASE(148, 148, 2, 0x0010, 0x10, 3, 3), + PIN_FIELD_BASE(149, 149, 5, 0x0000, 0x10, 18, 3), + PIN_FIELD_BASE(150, 150, 5, 0x0000, 0x10, 21, 3), + PIN_FIELD_BASE(151, 151, 3, 0x0010, 0x10, 18, 3), + PIN_FIELD_BASE(152, 152, 3, 0x0020, 0x10, 0, 3), + PIN_FIELD_BASE(153, 153, 2, 0x0000, 0x10, 27, 3), + PIN_FIELD_BASE(154, 154, 2, 0x0010, 0x10, 6, 3), + PIN_FIELD_BASE(155, 155, 2, 0x0010, 0x10, 0, 3), + PIN_FIELD_BASE(156, 156, 2, 0x0010, 0x10, 9, 3), + PIN_FIELD_BASE(157, 157, 8, 0x0020, 0x10, 3, 3), + PIN_FIELD_BASE(158, 158, 8, 0x0020, 0x10, 9, 3), + PIN_FIELD_BASE(159, 159, 8, 0x0020, 0x10, 6, 3), + PIN_FIELD_BASE(160, 160, 8, 0x0020, 0x10, 12, 3), + PIN_FIELD_BASE(161, 161, 5, 0x0020, 0x10, 9, 3), + PIN_FIELD_BASE(162, 162, 5, 0x0020, 0x10, 15, 3), + PIN_FIELD_BASE(163, 163, 5, 0x0020, 0x10, 12, 3), + PIN_FIELD_BASE(164, 164, 5, 0x0020, 0x10, 18, 3), + PIN_FIELD_BASE(165, 165, 4, 0x0010, 0x10, 3, 3), + PIN_FIELD_BASE(166, 166, 4, 0x0010, 0x10, 3, 3), + PIN_FIELD_BASE(167, 167, 4, 0x0010, 0x10, 9, 3), + PIN_FIELD_BASE(168, 168, 4, 0x0010, 0x10, 9, 3), + PIN_FIELD_BASE(169, 169, 4, 0x0010, 0x10, 12, 3), + PIN_FIELD_BASE(170, 170, 4, 0x0010, 0x10, 12, 3), + PIN_FIELD_BASE(171, 171, 4, 0x0010, 0x10, 6, 3), + PIN_FIELD_BASE(172, 172, 4, 0x0010, 0x10, 6, 3), + PIN_FIELD_BASE(173, 173, 1, 0x0000, 0x10, 0, 3), + PIN_FIELD_BASE(174, 174, 1, 0x0000, 0x10, 0, 3), + PIN_FIELD_BASE(175, 175, 1, 0x0000, 0x10, 0, 3), + PIN_FIELD_BASE(176, 176, 1, 0x0000, 0x10, 0, 3), + PIN_FIELD_BASE(177, 177, 1, 0x0000, 0x10, 0, 3), + PIN_FIELD_BASE(178, 178, 1, 0x0000, 0x10, 0, 3), + PIN_FIELD_BASE(179, 179, 1, 0x0000, 0x10, 0, 3), + PIN_FIELD_BASE(180, 180, 1, 0x0000, 0x10, 0, 3), + PIN_FIELD_BASE(181, 181, 1, 0x0010, 0x10, 12, 3), + PIN_FIELD_BASE(182, 182, 9, 0x0010, 0x10, 3, 3), + PIN_FIELD_BASE(183, 183, 9, 0x0010, 0x10, 9, 3), + PIN_FIELD_BASE(184, 184, 9, 0x0000, 0x10, 21, 3), + PIN_FIELD_BASE(185, 185, 9, 0x0000, 0x10, 24, 3), + PIN_FIELD_BASE(186, 186, 9, 0x0000, 0x10, 27, 3), + PIN_FIELD_BASE(187, 187, 9, 0x0010, 0x10, 15, 3), + PIN_FIELD_BASE(188, 188, 9, 0x0010, 0x10, 18, 3), + PIN_FIELD_BASE(189, 189, 9, 0x0010, 0x10, 21, 3), + PIN_FIELD_BASE(190, 190, 9, 0x0010, 0x10, 24, 3), + PIN_FIELD_BASE(191, 191, 9, 0x0010, 0x10, 6, 3), + PIN_FIELD_BASE(192, 192, 9, 0x0010, 0x10, 12, 3), + PIN_FIELD_BASE(193, 193, 9, 0x0010, 0x10, 0, 3), + PIN_FIELD_BASE(194, 194, 9, 0x0010, 0x10, 27, 3), + PIN_FIELD_BASE(195, 195, 9, 0x0020, 0x10, 0, 3), + PIN_FIELD_BASE(196, 196, 6, 0x0000, 0x10, 9, 3), +}; + +static const struct mtk_pin_field_calc mt6858_pin_drv_adv_range[] = { + PIN_FIELD_BASE(36, 36, 8, 0x0030, 0x10, 0, 5), + PIN_FIELD_BASE(37, 37, 8, 0x0030, 0x10, 5, 5), + PIN_FIELD_BASE(38, 38, 8, 0x0030, 0x10, 10, 5), + PIN_FIELD_BASE(39, 39, 8, 0x0030, 0x10, 15, 5), + PIN_FIELD_BASE(126, 126, 2, 0x0020, 0x10, 18, 5), + PIN_FIELD_BASE(127, 127, 2, 0x0020, 0x10, 23, 5), + PIN_FIELD_BASE(128, 128, 2, 0x0030, 0x10, 0, 5), + PIN_FIELD_BASE(129, 129, 2, 0x0030, 0x10, 5, 5), + PIN_FIELD_BASE(139, 139, 3, 0x0030, 0x10, 6, 3), + PIN_FIELD_BASE(140, 140, 3, 0x0030, 0x10, 18, 3), + PIN_FIELD_BASE(141, 141, 3, 0x0030, 0x10, 9, 3), + PIN_FIELD_BASE(142, 142, 3, 0x0030, 0x10, 21, 3), + PIN_FIELD_BASE(143, 143, 3, 0x0030, 0x10, 0, 3), + PIN_FIELD_BASE(144, 144, 3, 0x0030, 0x10, 3, 3), + PIN_FIELD_BASE(145, 145, 3, 0x0030, 0x10, 12, 3), + PIN_FIELD_BASE(146, 146, 3, 0x0030, 0x10, 24, 3), + PIN_FIELD_BASE(147, 147, 2, 0x0020, 0x10, 0, 3), + PIN_FIELD_BASE(148, 148, 2, 0x0020, 0x10, 9, 3), + PIN_FIELD_BASE(149, 149, 5, 0x0030, 0x10, 0, 3), + PIN_FIELD_BASE(150, 150, 5, 0x0030, 0x10, 3, 3), + PIN_FIELD_BASE(151, 151, 3, 0x0030, 0x10, 15, 3), + PIN_FIELD_BASE(152, 152, 3, 0x0030, 0x10, 27, 3), + PIN_FIELD_BASE(153, 153, 2, 0x0020, 0x10, 3, 3), + PIN_FIELD_BASE(154, 154, 2, 0x0020, 0x10, 12, 3), + PIN_FIELD_BASE(155, 155, 2, 0x0020, 0x10, 6, 3), + PIN_FIELD_BASE(156, 156, 2, 0x0020, 0x10, 15, 3), + PIN_FIELD_BASE(157, 157, 8, 0x0030, 0x10, 20, 3), + PIN_FIELD_BASE(158, 158, 8, 0x0030, 0x10, 26, 3), + PIN_FIELD_BASE(159, 159, 8, 0x0030, 0x10, 23, 3), + PIN_FIELD_BASE(160, 160, 8, 0x0030, 0x10, 29, 3), + PIN_FIELD_BASE(161, 161, 5, 0x0030, 0x10, 6, 3), + PIN_FIELD_BASE(162, 162, 5, 0x0030, 0x10, 12, 3), + PIN_FIELD_BASE(163, 163, 5, 0x0030, 0x10, 9, 3), + PIN_FIELD_BASE(164, 164, 5, 0x0030, 0x10, 15, 3), +}; + +static const struct mtk_pin_field_calc mt6858_pin_rsel_range[] = { + PIN_FIELD_BASE(139, 139, 3, 0x00e0, 0x10, 6, 3), + PIN_FIELD_BASE(140, 140, 3, 0x00e0, 0x10, 18, 3), + PIN_FIELD_BASE(141, 141, 3, 0x00e0, 0x10, 9, 3), + PIN_FIELD_BASE(142, 142, 3, 0x00e0, 0x10, 21, 3), + PIN_FIELD_BASE(143, 143, 3, 0x00e0, 0x10, 0, 3), + PIN_FIELD_BASE(144, 144, 3, 0x00e0, 0x10, 3, 3), + PIN_FIELD_BASE(145, 145, 3, 0x00e0, 0x10, 12, 3), + PIN_FIELD_BASE(146, 146, 3, 0x00e0, 0x10, 24, 3), + PIN_FIELD_BASE(147, 147, 2, 0x00b0, 0x10, 0, 3), + PIN_FIELD_BASE(148, 148, 2, 0x00b0, 0x10, 9, 3), + PIN_FIELD_BASE(149, 149, 5, 0x00d0, 0x10, 0, 3), + PIN_FIELD_BASE(150, 150, 5, 0x00d0, 0x10, 3, 3), + PIN_FIELD_BASE(151, 151, 3, 0x00e0, 0x10, 15, 3), + PIN_FIELD_BASE(152, 152, 3, 0x00e0, 0x10, 27, 3), + PIN_FIELD_BASE(153, 153, 2, 0x00b0, 0x10, 3, 3), + PIN_FIELD_BASE(154, 154, 2, 0x00b0, 0x10, 12, 3), + PIN_FIELD_BASE(155, 155, 2, 0x00b0, 0x10, 6, 3), + PIN_FIELD_BASE(156, 156, 2, 0x00b0, 0x10, 15, 3), + PIN_FIELD_BASE(157, 157, 8, 0x0100, 0x10, 0, 3), + PIN_FIELD_BASE(158, 158, 8, 0x0100, 0x10, 6, 3), + PIN_FIELD_BASE(159, 159, 8, 0x0100, 0x10, 3, 3), + PIN_FIELD_BASE(160, 160, 8, 0x0100, 0x10, 9, 3), + PIN_FIELD_BASE(161, 161, 5, 0x00d0, 0x10, 6, 3), + PIN_FIELD_BASE(162, 162, 5, 0x00d0, 0x10, 12, 3), + PIN_FIELD_BASE(163, 163, 5, 0x00d0, 0x10, 9, 3), + PIN_FIELD_BASE(164, 164, 5, 0x00d0, 0x10, 15, 3), +}; + +static const unsigned int mt6858_pull_type[] = { + MTK_PULL_PU_PD_TYPE, /* 0 */ + MTK_PULL_PU_PD_TYPE, /* 1 */ + MTK_PULL_PU_PD_TYPE, /* 2 */ + MTK_PULL_PU_PD_TYPE, /* 3 */ + MTK_PULL_PU_PD_TYPE, /* 4 */ + MTK_PULL_PU_PD_TYPE, /* 5 */ + MTK_PULL_PU_PD_TYPE, /* 6 */ + MTK_PULL_PU_PD_TYPE, /* 7 */ + MTK_PULL_PU_PD_TYPE, /* 8 */ + MTK_PULL_PU_PD_TYPE, /* 9 */ + MTK_PULL_PU_PD_TYPE, /* 10 */ + MTK_PULL_PU_PD_TYPE, /* 11 */ + MTK_PULL_PU_PD_TYPE, /* 12 */ + MTK_PULL_PU_PD_TYPE, /* 13 */ + MTK_PULL_PU_PD_TYPE, /* 14 */ + MTK_PULL_PU_PD_TYPE, /* 15 */ + MTK_PULL_PU_PD_TYPE, /* 16 */ + MTK_PULL_PU_PD_TYPE, /* 17 */ + MTK_PULL_PUPD_R1R0_TYPE, /* 18 */ + MTK_PULL_PUPD_R1R0_TYPE, /* 19 */ + MTK_PULL_PUPD_R1R0_TYPE, /* 20 */ + MTK_PULL_PU_PD_TYPE, /* 21 */ + MTK_PULL_PU_PD_TYPE, /* 22 */ + MTK_PULL_PU_PD_TYPE, /* 23 */ + MTK_PULL_PU_PD_TYPE, /* 24 */ + MTK_PULL_PU_PD_TYPE, /* 25 */ + MTK_PULL_PU_PD_TYPE, /* 26 */ + MTK_PULL_PU_PD_TYPE, /* 27 */ + MTK_PULL_PU_PD_TYPE, /* 28 */ + MTK_PULL_PU_PD_TYPE, /* 29 */ + MTK_PULL_PU_PD_TYPE, /* 30 */ + MTK_PULL_PU_PD_TYPE, /* 31 */ + MTK_PULL_PU_PD_TYPE, /* 32 */ + MTK_PULL_PU_PD_TYPE, /* 33 */ + MTK_PULL_PU_PD_TYPE, /* 34 */ + MTK_PULL_PU_PD_TYPE, /* 35 */ + MTK_PULL_PU_PD_TYPE, /* 36 */ + MTK_PULL_PU_PD_TYPE, /* 37 */ + MTK_PULL_PU_PD_TYPE, /* 38 */ + MTK_PULL_PU_PD_TYPE, /* 39 */ + MTK_PULL_PU_PD_TYPE, /* 40 */ + MTK_PULL_PU_PD_TYPE, /* 41 */ + MTK_PULL_PU_PD_TYPE, /* 42 */ + MTK_PULL_PU_PD_TYPE, /* 43 */ + MTK_PULL_PU_PD_TYPE, /* 44 */ + MTK_PULL_PU_PD_TYPE, /* 45 */ + MTK_PULL_PU_PD_TYPE, /* 46 */ + MTK_PULL_PU_PD_TYPE, /* 47 */ + MTK_PULL_PU_PD_TYPE, /* 48 */ + MTK_PULL_PU_PD_TYPE, /* 49 */ + MTK_PULL_PU_PD_TYPE, /* 50 */ + MTK_PULL_PU_PD_TYPE, /* 51 */ + MTK_PULL_PU_PD_TYPE, /* 52 */ + MTK_PULL_PU_PD_TYPE, /* 53 */ + MTK_PULL_PU_PD_TYPE, /* 54 */ + MTK_PULL_PU_PD_TYPE, /* 55 */ + MTK_PULL_PU_PD_TYPE, /* 56 */ + MTK_PULL_PU_PD_TYPE, /* 57 */ + MTK_PULL_PU_PD_TYPE, /* 58 */ + MTK_PULL_PU_PD_TYPE, /* 59 */ + MTK_PULL_PU_PD_TYPE, /* 60 */ + MTK_PULL_PU_PD_TYPE, /* 61 */ + MTK_PULL_PU_PD_TYPE, /* 62 */ + MTK_PULL_PU_PD_TYPE, /* 63 */ + MTK_PULL_PU_PD_TYPE, /* 64 */ + MTK_PULL_PU_PD_TYPE, /* 65 */ + MTK_PULL_PU_PD_TYPE, /* 66 */ + MTK_PULL_PU_PD_TYPE, /* 67 */ + MTK_PULL_PU_PD_TYPE, /* 68 */ + MTK_PULL_PU_PD_TYPE, /* 69 */ + MTK_PULL_PU_PD_TYPE, /* 70 */ + MTK_PULL_PU_PD_TYPE, /* 71 */ + MTK_PULL_PU_PD_TYPE, /* 72 */ + MTK_PULL_PU_PD_TYPE, /* 73 */ + MTK_PULL_PU_PD_TYPE, /* 74 */ + MTK_PULL_PU_PD_TYPE, /* 75 */ + MTK_PULL_PU_PD_TYPE, /* 76 */ + MTK_PULL_PU_PD_TYPE, /* 77 */ + MTK_PULL_PU_PD_TYPE, /* 78 */ + MTK_PULL_PU_PD_TYPE, /* 79 */ + MTK_PULL_PU_PD_TYPE, /* 80 */ + MTK_PULL_PU_PD_TYPE, /* 81 */ + MTK_PULL_PUPD_R1R0_TYPE, /* 82 */ + MTK_PULL_PUPD_R1R0_TYPE, /* 83 */ + MTK_PULL_PUPD_R1R0_TYPE, /* 84 */ + MTK_PULL_PUPD_R1R0_TYPE, /* 85 */ + MTK_PULL_PUPD_R1R0_TYPE, /* 86 */ + MTK_PULL_PUPD_R1R0_TYPE, /* 87 */ + MTK_PULL_PUPD_R1R0_TYPE, /* 88 */ + MTK_PULL_PUPD_R1R0_TYPE, /* 89 */ + MTK_PULL_PUPD_R1R0_TYPE, /* 90 */ + MTK_PULL_PUPD_R1R0_TYPE, /* 91 */ + MTK_PULL_PUPD_R1R0_TYPE, /* 92 */ + MTK_PULL_PUPD_R1R0_TYPE, /* 93 */ + MTK_PULL_PU_PD_TYPE, /* 94 */ + MTK_PULL_PU_PD_TYPE, /* 95 */ + MTK_PULL_PU_PD_TYPE, /* 96 */ + MTK_PULL_PU_PD_TYPE, /* 97 */ + MTK_PULL_PU_PD_TYPE, /* 98 */ + MTK_PULL_PU_PD_TYPE, /* 99 */ + MTK_PULL_PU_PD_TYPE, /* 100 */ + MTK_PULL_PU_PD_TYPE, /* 101 */ + MTK_PULL_PU_PD_TYPE, /* 102 */ + MTK_PULL_PU_PD_TYPE, /* 103 */ + MTK_PULL_PU_PD_TYPE, /* 104 */ + MTK_PULL_PU_PD_TYPE, /* 105 */ + MTK_PULL_PU_PD_TYPE, /* 106 */ + MTK_PULL_PU_PD_TYPE, /* 107 */ + MTK_PULL_PU_PD_TYPE, /* 108 */ + MTK_PULL_PU_PD_TYPE, /* 109 */ + MTK_PULL_PU_PD_TYPE, /* 110 */ + MTK_PULL_PU_PD_TYPE, /* 111 */ + MTK_PULL_PU_PD_TYPE, /* 112 */ + MTK_PULL_PU_PD_TYPE, /* 113 */ + MTK_PULL_PU_PD_TYPE, /* 114 */ + MTK_PULL_PU_PD_TYPE, /* 115 */ + MTK_PULL_PU_PD_TYPE, /* 116 */ + MTK_PULL_PU_PD_TYPE, /* 117 */ + MTK_PULL_PU_PD_TYPE, /* 118 */ + MTK_PULL_PU_PD_TYPE, /* 119 */ + MTK_PULL_PU_PD_TYPE, /* 120 */ + MTK_PULL_PU_PD_TYPE, /* 121 */ + MTK_PULL_PU_PD_TYPE, /* 122 */ + MTK_PULL_PU_PD_TYPE, /* 123 */ + MTK_PULL_PU_PD_TYPE, /* 124 */ + MTK_PULL_PU_PD_TYPE, /* 125 */ + MTK_PULL_PU_PD_TYPE, /* 126 */ + MTK_PULL_PU_PD_TYPE, /* 127 */ + MTK_PULL_PU_PD_TYPE, /* 128 */ + MTK_PULL_PU_PD_TYPE, /* 129 */ + MTK_PULL_PU_PD_TYPE, /* 130 */ + MTK_PULL_PU_PD_TYPE, /* 131 */ + MTK_PULL_PU_PD_TYPE, /* 132 */ + MTK_PULL_PU_PD_TYPE, /* 133 */ + MTK_PULL_PU_PD_TYPE, /* 134 */ + MTK_PULL_PU_PD_TYPE, /* 135 */ + MTK_PULL_PU_PD_TYPE, /* 136 */ + MTK_PULL_PU_PD_TYPE, /* 137 */ + MTK_PULL_PU_PD_TYPE, /* 138 */ + MTK_PULL_PU_PD_RSEL_TYPE, /* 139 */ + MTK_PULL_PU_PD_RSEL_TYPE, /* 140 */ + MTK_PULL_PU_PD_RSEL_TYPE, /* 141 */ + MTK_PULL_PU_PD_RSEL_TYPE, /* 142 */ + MTK_PULL_PU_PD_RSEL_TYPE, /* 143 */ + MTK_PULL_PU_PD_RSEL_TYPE, /* 144 */ + MTK_PULL_PU_PD_RSEL_TYPE, /* 145 */ + MTK_PULL_PU_PD_RSEL_TYPE, /* 146 */ + MTK_PULL_PU_PD_RSEL_TYPE, /* 147 */ + MTK_PULL_PU_PD_RSEL_TYPE, /* 148 */ + MTK_PULL_PU_PD_RSEL_TYPE, /* 149 */ + MTK_PULL_PU_PD_RSEL_TYPE, /* 150 */ + MTK_PULL_PU_PD_RSEL_TYPE, /* 151 */ + MTK_PULL_PU_PD_RSEL_TYPE, /* 152 */ + MTK_PULL_PU_PD_RSEL_TYPE, /* 153 */ + MTK_PULL_PU_PD_RSEL_TYPE, /* 154 */ + MTK_PULL_PU_PD_RSEL_TYPE, /* 155 */ + MTK_PULL_PU_PD_RSEL_TYPE, /* 156 */ + MTK_PULL_PU_PD_RSEL_TYPE, /* 157 */ + MTK_PULL_PU_PD_RSEL_TYPE, /* 158 */ + MTK_PULL_PU_PD_RSEL_TYPE, /* 159 */ + MTK_PULL_PU_PD_RSEL_TYPE, /* 160 */ + MTK_PULL_PU_PD_RSEL_TYPE, /* 161 */ + MTK_PULL_PU_PD_RSEL_TYPE, /* 162 */ + MTK_PULL_PU_PD_RSEL_TYPE, /* 163 */ + MTK_PULL_PU_PD_RSEL_TYPE, /* 164 */ + MTK_PULL_PU_PD_TYPE, /* 165 */ + MTK_PULL_PU_PD_TYPE, /* 166 */ + MTK_PULL_PU_PD_TYPE, /* 167 */ + MTK_PULL_PU_PD_TYPE, /* 168 */ + MTK_PULL_PU_PD_TYPE, /* 169 */ + MTK_PULL_PU_PD_TYPE, /* 170 */ + MTK_PULL_PU_PD_TYPE, /* 171 */ + MTK_PULL_PU_PD_TYPE, /* 172 */ + MTK_PULL_PU_PD_TYPE, /* 173 */ + MTK_PULL_PU_PD_TYPE, /* 174 */ + MTK_PULL_PU_PD_TYPE, /* 175 */ + MTK_PULL_PU_PD_TYPE, /* 176 */ + MTK_PULL_PU_PD_TYPE, /* 177 */ + MTK_PULL_PU_PD_TYPE, /* 178 */ + MTK_PULL_PU_PD_TYPE, /* 179 */ + MTK_PULL_PU_PD_TYPE, /* 180 */ + MTK_PULL_PU_PD_TYPE, /* 181 */ + MTK_PULL_PU_PD_TYPE, /* 182 */ + MTK_PULL_PU_PD_TYPE, /* 183 */ + MTK_PULL_PU_PD_TYPE, /* 184 */ + MTK_PULL_PU_PD_TYPE, /* 185 */ + MTK_PULL_PU_PD_TYPE, /* 186 */ + MTK_PULL_PU_PD_TYPE, /* 187 */ + MTK_PULL_PU_PD_TYPE, /* 188 */ + MTK_PULL_PU_PD_TYPE, /* 189 */ + MTK_PULL_PU_PD_TYPE, /* 190 */ + MTK_PULL_PU_PD_TYPE, /* 191 */ + MTK_PULL_PU_PD_TYPE, /* 192 */ + MTK_PULL_PU_PD_TYPE, /* 193 */ + MTK_PULL_PU_PD_TYPE, /* 194 */ + MTK_PULL_PU_PD_TYPE, /* 195 */ + MTK_PULL_PU_PD_TYPE, /* 196 */ +}; + +static const struct mtk_pin_reg_calc mt6858_reg_cals[PINCTRL_PIN_REG_MAX] = { + [PINCTRL_PIN_REG_MODE] = MTK_RANGE(mt6858_pin_mode_range), + [PINCTRL_PIN_REG_DIR] = MTK_RANGE(mt6858_pin_dir_range), + [PINCTRL_PIN_REG_DI] = MTK_RANGE(mt6858_pin_di_range), + [PINCTRL_PIN_REG_DO] = MTK_RANGE(mt6858_pin_do_range), + [PINCTRL_PIN_REG_SMT] = MTK_RANGE(mt6858_pin_smt_range), + [PINCTRL_PIN_REG_IES] = MTK_RANGE(mt6858_pin_ies_range), + [PINCTRL_PIN_REG_PU] = MTK_RANGE(mt6858_pin_pu_range), + [PINCTRL_PIN_REG_PD] = MTK_RANGE(mt6858_pin_pd_range), + [PINCTRL_PIN_REG_DRV] = MTK_RANGE(mt6858_pin_drv_range), + [PINCTRL_PIN_REG_PUPD] = MTK_RANGE(mt6858_pin_pupd_range), + [PINCTRL_PIN_REG_R0] = MTK_RANGE(mt6858_pin_r0_range), + [PINCTRL_PIN_REG_R1] = MTK_RANGE(mt6858_pin_r1_range), + [PINCTRL_PIN_REG_DRV_ADV] = MTK_RANGE(mt6858_pin_drv_adv_range), + [PINCTRL_PIN_REG_RSEL] = MTK_RANGE(mt6858_pin_rsel_range), +}; + +static const char * const mt6858_pinctrl_register_base_names[] = { + "base", "lm", "rb", "bm2", "bm", "bm1", "lt", "lt1", "rt", "rt1", +}; + +static const struct mtk_eint_hw mt6858_eint_hw = { + .port_mask = 0xf, + .ports = 3, + .ap_num = 217, + .db_cnt = 36, + .db_time = debounce_time_mt6878, +}; + +static const struct mtk_pin_soc mt6858_data = { + .reg_cal = mt6858_reg_cals, + .pins = mtk_pins_mt6858, + .npins = ARRAY_SIZE(mtk_pins_mt6858), + .ngrps = ARRAY_SIZE(mtk_pins_mt6858), + .eint_hw = &mt6858_eint_hw, + .eint_pin = eint_pins_mt6858, + .nfuncs = 16, + .gpio_m = 0, + .base_names = mt6858_pinctrl_register_base_names, + .nbase_names = ARRAY_SIZE(mt6858_pinctrl_register_base_names), + .pull_type = mt6858_pull_type, + .bias_set_combo = mtk_pinconf_bias_set_combo, + .bias_get_combo = mtk_pinconf_bias_get_combo, + .drive_set = mtk_pinconf_drive_set_rev1, + .drive_get = mtk_pinconf_drive_get_rev1, + .adv_drive_get = mtk_pinconf_adv_drive_get_raw, + .adv_drive_set = mtk_pinconf_adv_drive_set_raw, +}; + +static const struct of_device_id mt6858_pinctrl_of_match[] = { + { .compatible = "mediatek,mt6858-pinctrl", .data = &mt6858_data }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, mt6858_pinctrl_of_match); + +static struct platform_driver mt6858_pinctrl_driver = { + .driver = { + .name = "mt6858-pinctrl", + .of_match_table = mt6858_pinctrl_of_match, + .pm = pm_sleep_ptr(&mtk_paris_pinctrl_pm_ops), + }, + .probe = mtk_paris_pinctrl_probe, +}; + +static int __init mt6858_pinctrl_init(void) +{ + return platform_driver_register(&mt6858_pinctrl_driver); +} +arch_initcall(mt6858_pinctrl_init); + +MODULE_DESCRIPTION("MediaTek MT6858 Pinctrl Driver"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/pinctrl/mediatek/pinctrl-mt6878.c b/drivers/pinctrl/mediatek/pinctrl-mt6878.c index b59ae089128a..7b5a15f4aba1 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt6878.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt6878.c @@ -1459,6 +1459,7 @@ static const struct of_device_id mt6878_pinctrl_of_match[] = { { .compatible = "mediatek,mt6878-pinctrl", .data = &mt6878_data }, { } }; +MODULE_DEVICE_TABLE(of, mt6878_pinctrl_of_match); static struct platform_driver mt6878_pinctrl_driver = { .driver = { @@ -1476,3 +1477,4 @@ static int __init mt6878_pinctrl_init(void) arch_initcall(mt6878_pinctrl_init); MODULE_DESCRIPTION("MediaTek MT6878 Pinctrl Driver"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/pinctrl/mediatek/pinctrl-mt6893.c b/drivers/pinctrl/mediatek/pinctrl-mt6893.c index 468ce0109b07..5ff1e7722889 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt6893.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt6893.c @@ -859,6 +859,7 @@ static const struct of_device_id mt6893_pinctrl_of_match[] = { { .compatible = "mediatek,mt6893-pinctrl", .data = &mt6893_data }, { /* sentinel */ } }; +MODULE_DEVICE_TABLE(of, mt6893_pinctrl_of_match); static struct platform_driver mt6893_pinctrl_driver = { .driver = { @@ -877,3 +878,4 @@ static int __init mt6893_pinctrl_init(void) arch_initcall(mt6893_pinctrl_init); MODULE_DESCRIPTION("MediaTek MT6893 Pinctrl Driver"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/pinctrl/mediatek/pinctrl-mt7620.c b/drivers/pinctrl/mediatek/pinctrl-mt7620.c index d2624b9b5bc4..7bfa6a8a3ce3 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt7620.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt7620.c @@ -135,3 +135,7 @@ static int __init mt7620_pinctrl_init(void) return platform_driver_register(&mt7620_pinctrl_driver); } core_initcall_sync(mt7620_pinctrl_init); + +MODULE_DESCRIPTION("MediaTek MT7620 Pinctrl Driver"); +MODULE_LICENSE("GPL v2"); +MODULE_IMPORT_NS("MTK_PINCTRL"); diff --git a/drivers/pinctrl/mediatek/pinctrl-mt7621.c b/drivers/pinctrl/mediatek/pinctrl-mt7621.c index b18c1a47bbeb..5a893d8505a3 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt7621.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt7621.c @@ -115,3 +115,7 @@ static int __init mt7621_pinctrl_init(void) return platform_driver_register(&mt7621_pinctrl_driver); } core_initcall_sync(mt7621_pinctrl_init); + +MODULE_DESCRIPTION("MediaTek MT7621 Pinctrl Driver"); +MODULE_LICENSE("GPL v2"); +MODULE_IMPORT_NS("MTK_PINCTRL"); diff --git a/drivers/pinctrl/mediatek/pinctrl-mt7622.c b/drivers/pinctrl/mediatek/pinctrl-mt7622.c index d5777889448a..36a9a9f302ca 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt7622.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt7622.c @@ -874,6 +874,7 @@ static const struct of_device_id mt7622_pinctrl_of_match[] = { { .compatible = "mediatek,mt7622-pinctrl", }, { } }; +MODULE_DEVICE_TABLE(of, mt7622_pinctrl_of_match); static int mt7622_pinctrl_probe(struct platform_device *pdev) { @@ -893,3 +894,7 @@ static int __init mt7622_pinctrl_init(void) return platform_driver_register(&mt7622_pinctrl_driver); } arch_initcall(mt7622_pinctrl_init); + +MODULE_DESCRIPTION("MediaTek MT7622 Pinctrl Driver"); +MODULE_LICENSE("GPL v2"); +MODULE_IMPORT_NS("MTK_PINCTRL"); diff --git a/drivers/pinctrl/mediatek/pinctrl-mt7623.c b/drivers/pinctrl/mediatek/pinctrl-mt7623.c index 69c06c2c0e21..26fa489db13c 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt7623.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt7623.c @@ -1413,6 +1413,7 @@ static const struct of_device_id mt7623_pctrl_match[] = { { .compatible = "mediatek,mt7623-moore-pinctrl", }, {} }; +MODULE_DEVICE_TABLE(of, mt7623_pctrl_match); static int mt7623_pinctrl_probe(struct platform_device *pdev) { @@ -1440,3 +1441,7 @@ static int __init mtk_pinctrl_init(void) return platform_driver_register(&mtk_pinctrl_driver); } arch_initcall(mtk_pinctrl_init); + +MODULE_DESCRIPTION("MediaTek MT7623 Pinctrl Driver"); +MODULE_LICENSE("GPL v2"); +MODULE_IMPORT_NS("MTK_PINCTRL"); diff --git a/drivers/pinctrl/mediatek/pinctrl-mt7629.c b/drivers/pinctrl/mediatek/pinctrl-mt7629.c index cc0694881ac9..385d66b8e3fb 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt7629.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt7629.c @@ -430,6 +430,7 @@ static const struct of_device_id mt7629_pinctrl_of_match[] = { { .compatible = "mediatek,mt7629-pinctrl", }, {} }; +MODULE_DEVICE_TABLE(of, mt7629_pinctrl_of_match); static int mt7629_pinctrl_probe(struct platform_device *pdev) { @@ -449,3 +450,7 @@ static int __init mt7629_pinctrl_init(void) return platform_driver_register(&mt7629_pinctrl_driver); } arch_initcall(mt7629_pinctrl_init); + +MODULE_DESCRIPTION("MediaTek MT7629 Pinctrl Driver"); +MODULE_LICENSE("GPL v2"); +MODULE_IMPORT_NS("MTK_PINCTRL"); diff --git a/drivers/pinctrl/mediatek/pinctrl-mt76x8.c b/drivers/pinctrl/mediatek/pinctrl-mt76x8.c index 2bc8d4409ca2..336d4e36e884 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt76x8.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt76x8.c @@ -247,3 +247,7 @@ static int __init mt76x8_pinctrl_init(void) return platform_driver_register(&mt76x8_pinctrl_driver); } core_initcall_sync(mt76x8_pinctrl_init); + +MODULE_DESCRIPTION("MediaTek MT76X8 Pinctrl Driver"); +MODULE_LICENSE("GPL v2"); +MODULE_IMPORT_NS("MTK_PINCTRL"); diff --git a/drivers/pinctrl/mediatek/pinctrl-mt7981.c b/drivers/pinctrl/mediatek/pinctrl-mt7981.c index 22c8f2480346..2325cc8b9345 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt7981.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt7981.c @@ -1039,6 +1039,7 @@ static const struct of_device_id mt7981_pinctrl_of_match[] = { { .compatible = "mediatek,mt7981-pinctrl", }, {} }; +MODULE_DEVICE_TABLE(of, mt7981_pinctrl_of_match); static int mt7981_pinctrl_probe(struct platform_device *pdev) { @@ -1058,3 +1059,7 @@ static int __init mt7981_pinctrl_init(void) return platform_driver_register(&mt7981_pinctrl_driver); } arch_initcall(mt7981_pinctrl_init); + +MODULE_DESCRIPTION("MediaTek MT7981 Pinctrl Driver"); +MODULE_LICENSE("GPL v2"); +MODULE_IMPORT_NS("MTK_PINCTRL"); diff --git a/drivers/pinctrl/mediatek/pinctrl-mt7986.c b/drivers/pinctrl/mediatek/pinctrl-mt7986.c index 5dda4b7467fd..6cbf90879eb5 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt7986.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt7986.c @@ -965,11 +965,13 @@ static const struct of_device_id mt7986a_pinctrl_of_match[] = { {.compatible = "mediatek,mt7986a-pinctrl",}, {} }; +MODULE_DEVICE_TABLE(of, mt7986a_pinctrl_of_match); static const struct of_device_id mt7986b_pinctrl_of_match[] = { {.compatible = "mediatek,mt7986b-pinctrl",}, {} }; +MODULE_DEVICE_TABLE(of, mt7986b_pinctrl_of_match); static int mt7986a_pinctrl_probe(struct platform_device *pdev) { @@ -997,15 +999,18 @@ static struct platform_driver mt7986b_pinctrl_driver = { .probe = mt7986b_pinctrl_probe, }; -static int __init mt7986a_pinctrl_init(void) -{ - return platform_driver_register(&mt7986a_pinctrl_driver); -} +static struct platform_driver * const mt7986_pinctrl_drivers[] = { + &mt7986a_pinctrl_driver, + &mt7986b_pinctrl_driver, +}; -static int __init mt7986b_pinctrl_init(void) +static int __init mt7986_pinctrl_init(void) { - return platform_driver_register(&mt7986b_pinctrl_driver); + return platform_register_drivers(mt7986_pinctrl_drivers, + ARRAY_SIZE(mt7986_pinctrl_drivers)); } +arch_initcall(mt7986_pinctrl_init); -arch_initcall(mt7986a_pinctrl_init); -arch_initcall(mt7986b_pinctrl_init); +MODULE_DESCRIPTION("MediaTek MT7986 Pinctrl Driver"); +MODULE_LICENSE("GPL v2"); +MODULE_IMPORT_NS("MTK_PINCTRL"); diff --git a/drivers/pinctrl/mediatek/pinctrl-mt7988.c b/drivers/pinctrl/mediatek/pinctrl-mt7988.c index fd3a7ff0a04d..14b5f4b695a2 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt7988.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt7988.c @@ -1525,6 +1525,7 @@ static const struct of_device_id mt7988_pinctrl_of_match[] = { { .compatible = "mediatek,mt7988-pinctrl" }, {} }; +MODULE_DEVICE_TABLE(of, mt7988_pinctrl_of_match); static int mt7988_pinctrl_probe(struct platform_device *pdev) { @@ -1544,3 +1545,7 @@ static int __init mt7988_pinctrl_init(void) return platform_driver_register(&mt7988_pinctrl_driver); } arch_initcall(mt7988_pinctrl_init); + +MODULE_DESCRIPTION("MediaTek MT7988 Pinctrl Driver"); +MODULE_LICENSE("GPL v2"); +MODULE_IMPORT_NS("MTK_PINCTRL"); diff --git a/drivers/pinctrl/mediatek/pinctrl-mt8127.c b/drivers/pinctrl/mediatek/pinctrl-mt8127.c index f5030a9ea40b..296eed43c10a 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt8127.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt8127.c @@ -293,6 +293,7 @@ static const struct of_device_id mt8127_pctrl_match[] = { { .compatible = "mediatek,mt8127-pinctrl", .data = &mt8127_pinctrl_data }, { } }; +MODULE_DEVICE_TABLE(of, mt8127_pctrl_match); static struct platform_driver mtk_pinctrl_driver = { .probe = mtk_pctrl_common_probe, @@ -307,3 +308,7 @@ static int __init mtk_pinctrl_init(void) return platform_driver_register(&mtk_pinctrl_driver); } arch_initcall(mtk_pinctrl_init); + +MODULE_DESCRIPTION("MediaTek MT8127 Pinctrl Driver"); +MODULE_LICENSE("GPL v2"); +MODULE_IMPORT_NS("MTK_PINCTRL"); diff --git a/drivers/pinctrl/mediatek/pinctrl-mt8135.c b/drivers/pinctrl/mediatek/pinctrl-mt8135.c index 77c6ac464e86..713b362832db 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt8135.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt8135.c @@ -322,6 +322,7 @@ static const struct of_device_id mt8135_pctrl_match[] = { { .compatible = "mediatek,mt8135-pinctrl", .data = &mt8135_pinctrl_data }, { } }; +MODULE_DEVICE_TABLE(of, mt8135_pctrl_match); static struct platform_driver mtk_pinctrl_driver = { .probe = mtk_pctrl_common_probe, @@ -336,3 +337,7 @@ static int __init mtk_pinctrl_init(void) return platform_driver_register(&mtk_pinctrl_driver); } arch_initcall(mtk_pinctrl_init); + +MODULE_DESCRIPTION("MediaTek MT8135 Pinctrl Driver"); +MODULE_LICENSE("GPL v2"); +MODULE_IMPORT_NS("MTK_PINCTRL"); diff --git a/drivers/pinctrl/mediatek/pinctrl-mt8167.c b/drivers/pinctrl/mediatek/pinctrl-mt8167.c index c812d614e9d4..cc45b0954009 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt8167.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt8167.c @@ -343,3 +343,7 @@ static int __init mtk_pinctrl_init(void) return platform_driver_register(&mtk_pinctrl_driver); } arch_initcall(mtk_pinctrl_init); + +MODULE_DESCRIPTION("MediaTek MT8167 Pinctrl Driver"); +MODULE_LICENSE("GPL v2"); +MODULE_IMPORT_NS("MTK_PINCTRL"); diff --git a/drivers/pinctrl/mediatek/pinctrl-mt8173.c b/drivers/pinctrl/mediatek/pinctrl-mt8173.c index b214deeafbf1..fbb92a1b9d2c 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt8173.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt8173.c @@ -341,6 +341,7 @@ static const struct of_device_id mt8173_pctrl_match[] = { }, { } }; +MODULE_DEVICE_TABLE(of, mt8173_pctrl_match); static struct platform_driver mtk_pinctrl_driver = { .probe = mt8173_pinctrl_probe, @@ -356,3 +357,7 @@ static int __init mtk_pinctrl_init(void) return platform_driver_register(&mtk_pinctrl_driver); } arch_initcall(mtk_pinctrl_init); + +MODULE_DESCRIPTION("MediaTek MT8173 Pinctrl Driver"); +MODULE_LICENSE("GPL v2"); +MODULE_IMPORT_NS("MTK_PINCTRL"); diff --git a/drivers/pinctrl/mediatek/pinctrl-mt8183.c b/drivers/pinctrl/mediatek/pinctrl-mt8183.c index 93e482c6b5fd..edc68f998d8c 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt8183.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt8183.c @@ -571,6 +571,7 @@ static const struct of_device_id mt8183_pinctrl_of_match[] = { { .compatible = "mediatek,mt8183-pinctrl", .data = &mt8183_data }, { } }; +MODULE_DEVICE_TABLE(of, mt8183_pinctrl_of_match); static struct platform_driver mt8183_pinctrl_driver = { .driver = { @@ -586,3 +587,6 @@ static int __init mt8183_pinctrl_init(void) return platform_driver_register(&mt8183_pinctrl_driver); } arch_initcall(mt8183_pinctrl_init); + +MODULE_DESCRIPTION("MediaTek MT8183 Pinctrl Driver"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/pinctrl/mediatek/pinctrl-mt8186.c b/drivers/pinctrl/mediatek/pinctrl-mt8186.c index dd19e74856a9..d4817838c531 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt8186.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt8186.c @@ -1249,6 +1249,7 @@ static const struct of_device_id mt8186_pinctrl_of_match[] = { { .compatible = "mediatek,mt8186-pinctrl", .data = &mt8186_data }, { } }; +MODULE_DEVICE_TABLE(of, mt8186_pinctrl_of_match); static struct platform_driver mt8186_pinctrl_driver = { .driver = { @@ -1265,3 +1266,6 @@ static int __init mt8186_pinctrl_init(void) } arch_initcall(mt8186_pinctrl_init); + +MODULE_DESCRIPTION("MediaTek MT8186 Pinctrl Driver"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/pinctrl/mediatek/pinctrl-mt8188.c b/drivers/pinctrl/mediatek/pinctrl-mt8188.c index 3975e99d9cf4..35dde16ab449 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt8188.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt8188.c @@ -1653,6 +1653,7 @@ static const struct of_device_id mt8188_pinctrl_of_match[] = { { .compatible = "mediatek,mt8188-pinctrl", .data = &mt8188_data }, { } }; +MODULE_DEVICE_TABLE(of, mt8188_pinctrl_of_match); static struct platform_driver mt8188_pinctrl_driver = { .driver = { @@ -1671,3 +1672,4 @@ static int __init mt8188_pinctrl_init(void) arch_initcall(mt8188_pinctrl_init); MODULE_DESCRIPTION("MediaTek MT8188 Pinctrl Driver"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/pinctrl/mediatek/pinctrl-mt8189.c b/drivers/pinctrl/mediatek/pinctrl-mt8189.c index cd4cdff309a1..1b1f9b4b6ad1 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt8189.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt8189.c @@ -1679,6 +1679,7 @@ static const struct of_device_id mt8189_pinctrl_of_match[] = { { .compatible = "mediatek,mt8189-pinctrl", .data = &mt8189_data }, { /* sentinel */ } }; +MODULE_DEVICE_TABLE(of, mt8189_pinctrl_of_match); static struct platform_driver mt8189_pinctrl_driver = { .driver = { @@ -1696,3 +1697,4 @@ static int __init mt8189_pinctrl_init(void) arch_initcall(mt8189_pinctrl_init); MODULE_DESCRIPTION("MediaTek MT8189 Pinctrl Driver"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/pinctrl/mediatek/pinctrl-mt8192.c b/drivers/pinctrl/mediatek/pinctrl-mt8192.c index 3f8a9dbcb704..b2ae3a62418d 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt8192.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt8192.c @@ -1414,6 +1414,7 @@ static const struct of_device_id mt8192_pinctrl_of_match[] = { { .compatible = "mediatek,mt8192-pinctrl", .data = &mt8192_data }, { } }; +MODULE_DEVICE_TABLE(of, mt8192_pinctrl_of_match); static struct platform_driver mt8192_pinctrl_driver = { .driver = { @@ -1431,3 +1432,4 @@ static int __init mt8192_pinctrl_init(void) arch_initcall(mt8192_pinctrl_init); MODULE_DESCRIPTION("MediaTek MT8192 Pinctrl Driver"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/pinctrl/mediatek/pinctrl-mt8195.c b/drivers/pinctrl/mediatek/pinctrl-mt8195.c index 83345c52b2fa..3a9912c0c095 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt8195.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt8195.c @@ -963,6 +963,7 @@ static const struct of_device_id mt8195_pinctrl_of_match[] = { { .compatible = "mediatek,mt8195-pinctrl", .data = &mt8195_data }, { } }; +MODULE_DEVICE_TABLE(of, mt8195_pinctrl_of_match); static struct platform_driver mt8195_pinctrl_driver = { .driver = { @@ -978,3 +979,6 @@ static int __init mt8195_pinctrl_init(void) return platform_driver_register(&mt8195_pinctrl_driver); } arch_initcall(mt8195_pinctrl_init); + +MODULE_DESCRIPTION("MediaTek MT8195 Pinctrl Driver"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/pinctrl/mediatek/pinctrl-mt8196.c b/drivers/pinctrl/mediatek/pinctrl-mt8196.c index dec957c1724b..2e36bf3c45eb 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt8196.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt8196.c @@ -1839,6 +1839,7 @@ static const struct of_device_id mt8196_pinctrl_of_match[] = { { .compatible = "mediatek,mt8196-pinctrl", .data = &mt8196_data }, { /* sentinel */ } }; +MODULE_DEVICE_TABLE(of, mt8196_pinctrl_of_match); static struct platform_driver mt8196_pinctrl_driver = { .driver = { @@ -1856,3 +1857,4 @@ static int __init mt8196_pinctrl_init(void) arch_initcall(mt8196_pinctrl_init); MODULE_DESCRIPTION("MediaTek MT8196 Pinctrl Driver"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/pinctrl/mediatek/pinctrl-mt8365.c b/drivers/pinctrl/mediatek/pinctrl-mt8365.c index c20b9e2e02dd..564227f7ca2d 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt8365.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt8365.c @@ -477,6 +477,7 @@ static const struct of_device_id mt8365_pctrl_match[] = { { .compatible = "mediatek,mt8365-pinctrl", .data = &mt8365_pinctrl_data }, {} }; +MODULE_DEVICE_TABLE(of, mt8365_pctrl_match); static struct platform_driver mtk_pinctrl_driver = { .probe = mtk_pctrl_common_probe, @@ -494,4 +495,6 @@ static int __init mtk_pinctrl_init(void) arch_initcall(mtk_pinctrl_init); MODULE_DESCRIPTION("MediaTek MT8365 Pinctrl Driver"); +MODULE_LICENSE("GPL v2"); MODULE_AUTHOR("Zhiyong Tao "); +MODULE_IMPORT_NS("MTK_PINCTRL"); diff --git a/drivers/pinctrl/mediatek/pinctrl-mt8516.c b/drivers/pinctrl/mediatek/pinctrl-mt8516.c index 68d6638e7f4b..d4f0a0bc5438 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt8516.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt8516.c @@ -343,3 +343,7 @@ static int __init mtk_pinctrl_init(void) return platform_driver_register(&mtk_pinctrl_driver); } arch_initcall(mtk_pinctrl_init); + +MODULE_DESCRIPTION("MediaTek MT8516 Pinctrl Driver"); +MODULE_LICENSE("GPL v2"); +MODULE_IMPORT_NS("MTK_PINCTRL"); diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c b/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c index 4918d38abfc2..faa6dbf0f635 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c +++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c @@ -69,6 +69,7 @@ void mtk_rmw(struct mtk_pinctrl *pctl, u8 i, u32 reg, u32 mask, u32 set) spin_unlock_irqrestore(&pctl->lock, flags); } +EXPORT_SYMBOL_NS_GPL(mtk_rmw, "MTK_PINCTRL"); static int mtk_hw_pin_field_lookup(struct mtk_pinctrl *hw, const struct mtk_pin_desc *desc, @@ -1242,11 +1243,7 @@ int mtk_pinconf_adv_drive_set(struct mtk_pinctrl *hw, if (err) return err; - err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DRV_E1, e1); - if (err) - return err; - - return err; + return mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DRV_E1, e1); } EXPORT_SYMBOL_GPL(mtk_pinconf_adv_drive_set); diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-common.c b/drivers/pinctrl/mediatek/pinctrl-mtk-common.c index dd2c8aa03938..1a977acd6883 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mtk-common.c +++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common.c @@ -7,6 +7,7 @@ #include #include +#include #include #include #include @@ -190,6 +191,7 @@ int mtk_pconf_spec_set_ies_smt_range(struct regmap *regmap, regmap_write(regmap, reg_addr, bit); return 0; } +EXPORT_SYMBOL_NS_GPL(mtk_pconf_spec_set_ies_smt_range, "MTK_PINCTRL"); static const struct mtk_pin_drv_grp *mtk_find_pin_drv_grp_by_pin( struct mtk_pinctrl *pctl, unsigned long pin) { @@ -297,6 +299,7 @@ int mtk_pctrl_spec_pull_set_samereg(struct regmap *regmap, return 0; } +EXPORT_SYMBOL_NS_GPL(mtk_pctrl_spec_pull_set_samereg, "MTK_PINCTRL"); static int mtk_pconf_set_pull_select(struct mtk_pinctrl *pctl, unsigned int pin, bool enable, bool isup, unsigned int arg) @@ -1130,31 +1133,26 @@ int mtk_pctrl_init(struct platform_device *pdev, pctl->chip->parent = &pdev->dev; pctl->chip->base = -1; - ret = gpiochip_add_data(pctl->chip, pctl); + ret = devm_gpiochip_add_data(&pdev->dev, pctl->chip, pctl); if (ret) return -EINVAL; /* Register the GPIO to pin mappings. */ ret = gpiochip_add_pin_range(pctl->chip, dev_name(&pdev->dev), 0, 0, pctl->devdata->npins); - if (ret) { - ret = -EINVAL; - goto chip_error; - } + if (ret) + return -EINVAL; /* Only initialize EINT if we have EINT pins */ if (data->eint_hw.ap_num > 0) { ret = mtk_eint_init(pctl, pdev); if (ret) - goto chip_error; + return ret; } return 0; - -chip_error: - gpiochip_remove(pctl->chip); - return ret; } +EXPORT_SYMBOL_NS_GPL(mtk_pctrl_init, "MTK_PINCTRL"); int mtk_pctrl_common_probe(struct platform_device *pdev) { @@ -1166,3 +1164,7 @@ int mtk_pctrl_common_probe(struct platform_device *pdev) return mtk_pctrl_init(pdev, data, NULL); } +EXPORT_SYMBOL_NS_GPL(mtk_pctrl_common_probe, "MTK_PINCTRL"); + +MODULE_DESCRIPTION("MediaTek Pinctrl Common Driver"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-mt6858.h b/drivers/pinctrl/mediatek/pinctrl-mtk-mt6858.h new file mode 100644 index 000000000000..208db809717f --- /dev/null +++ b/drivers/pinctrl/mediatek/pinctrl-mtk-mt6858.h @@ -0,0 +1,2378 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2025 MediaTek Inc. + * Alice Chao + * Copyright (c) 2026 Jolla Mobile Ltd + * Nikolai Burov + */ + +#ifndef __PINCTRL_MTK_MT6858_H +#define __PINCTRL_MTK_MT6858_H + +#include "pinctrl-paris.h" + +#define EINT_INVALID_BASE 0xff + +#define MTK_PIN_VEINT(_number) \ + MTK_PIN( \ + _number, "veint" #_number, \ + MTK_EINT_FUNCTION(0, _number), \ + DRV_GRP4, \ + MTK_FUNCTION(0, NULL) \ + ) + +static const struct mtk_pin_desc mtk_pins_mt6858[] = { + MTK_PIN( + 0, "GPIO0", + MTK_EINT_FUNCTION(0, 0), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO0"), + MTK_FUNCTION(1, "TP_GPIO0_AO"), + MTK_FUNCTION(3, "MD_INT0"), + MTK_FUNCTION(5, "SCP_SCL4"), + MTK_FUNCTION(7, "DBG_MON_A0"), + MTK_FUNCTION(8, "IOBIST0") + ), + MTK_PIN( + 1, "GPIO1", + MTK_EINT_FUNCTION(0, 1), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO1"), + MTK_FUNCTION(1, "TP_GPIO1_AO"), + MTK_FUNCTION(2, "SRCLKENA2"), + MTK_FUNCTION(3, "MD_INT3"), + MTK_FUNCTION(4, "SCP_DMIC_CLK"), + MTK_FUNCTION(5, "DMIC_CLK"), + MTK_FUNCTION(6, "SCP_SCL5"), + MTK_FUNCTION(7, "DBG_MON_A1"), + MTK_FUNCTION(8, "IOBIST1") + ), + MTK_PIN( + 2, "GPIO2", + MTK_EINT_FUNCTION(0, 2), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO2"), + MTK_FUNCTION(1, "TP_GPIO2_AO"), + MTK_FUNCTION(3, "MD_INT4"), + MTK_FUNCTION(4, "SCP_DMIC_DAT"), + MTK_FUNCTION(5, "DMIC_DAT"), + MTK_FUNCTION(6, "SCP_SDA5"), + MTK_FUNCTION(7, "DBG_MON_A2"), + MTK_FUNCTION(8, "IOBIST2") + ), + MTK_PIN( + 3, "GPIO3", + MTK_EINT_FUNCTION(0, 3), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO3"), + MTK_FUNCTION(1, "TP_GPIO3_AO"), + MTK_FUNCTION(2, "SPI7_CLK"), + MTK_FUNCTION(3, "TP_UTXD2_VLP"), + MTK_FUNCTION(4, "SSPM_UTXD_AO_VLP"), + MTK_FUNCTION(5, "MD_MCIF_UTXD0"), + MTK_FUNCTION(8, "IOBIST3") + ), + MTK_PIN( + 4, "GPIO4", + MTK_EINT_FUNCTION(0, 4), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO4"), + MTK_FUNCTION(1, "TP_GPIO4_AO"), + MTK_FUNCTION(2, "SPI7_CSB"), + MTK_FUNCTION(3, "TP_URXD2_VLP"), + MTK_FUNCTION(4, "SSPM_URXD_AO_VLP"), + MTK_FUNCTION(5, "MD_MCIF_URXD0"), + MTK_FUNCTION(8, "IOBIST4") + ), + MTK_PIN( + 5, "GPIO5", + MTK_EINT_FUNCTION(0, 5), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO5"), + MTK_FUNCTION(1, "TP_GPIO5_AO"), + MTK_FUNCTION(2, "SPI7_MO"), + MTK_FUNCTION(8, "IOBIST5") + ), + MTK_PIN( + 6, "GPIO6", + MTK_EINT_FUNCTION(0, 6), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO6"), + MTK_FUNCTION(1, "TP_GPIO6_AO"), + MTK_FUNCTION(2, "SPI7_MI"), + MTK_FUNCTION(3, "GPS_PPS"), + MTK_FUNCTION(4, "MD32_0_GPIO0"), + MTK_FUNCTION(8, "IOBIST6") + ), + MTK_PIN( + 7, "GPIO7", + MTK_EINT_FUNCTION(0, 7), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO7"), + MTK_FUNCTION(1, "TP_GPIO7_AO"), + MTK_FUNCTION(2, "SRCLKENA1"), + MTK_FUNCTION(3, "PWM_1"), + MTK_FUNCTION(4, "MD32_1_GPIO0"), + MTK_FUNCTION(5, "SCP_SDA4"), + MTK_FUNCTION(6, "MD_INT4"), + MTK_FUNCTION(8, "IOBIST7") + ), + MTK_PIN( + 8, "GPIO8", + MTK_EINT_FUNCTION(0, 8), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO8"), + MTK_FUNCTION(1, "SSPM_JTAG_TRSTN_VCORE"), + MTK_FUNCTION(2, "SCP_JTAG0_TRSTN_VCORE"), + MTK_FUNCTION(6, "CONN_BGF_MCU_TRST_B"), + MTK_FUNCTION(8, "IOBIST8") + ), + MTK_PIN( + 9, "GPIO9", + MTK_EINT_FUNCTION(0, 9), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO9"), + MTK_FUNCTION(1, "SSPM_JTAG_TCK_VCORE"), + MTK_FUNCTION(2, "SCP_JTAG0_TCK_VCORE"), + MTK_FUNCTION(6, "CONN_BGF_MCU_TCK"), + MTK_FUNCTION(8, "IOBIST9") + ), + MTK_PIN( + 10, "GPIO10", + MTK_EINT_FUNCTION(0, 10), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO10"), + MTK_FUNCTION(1, "SSPM_JTAG_TMS_VCORE"), + MTK_FUNCTION(2, "SCP_JTAG0_TMS_VCORE"), + MTK_FUNCTION(6, "CONN_BGF_MCU_TMS"), + MTK_FUNCTION(8, "IOBIST10") + ), + MTK_PIN( + 11, "GPIO11", + MTK_EINT_FUNCTION(0, 11), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO11"), + MTK_FUNCTION(1, "SSPM_JTAG_TDI_VCORE"), + MTK_FUNCTION(2, "SCP_JTAG0_TDI_VCORE"), + MTK_FUNCTION(6, "CONN_BGF_MCU_TDI"), + MTK_FUNCTION(8, "IOBIST11") + ), + MTK_PIN( + 12, "GPIO12", + MTK_EINT_FUNCTION(0, 12), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO12"), + MTK_FUNCTION(1, "SSPM_JTAG_TDO_VCORE"), + MTK_FUNCTION(2, "SCP_JTAG0_TDO_VCORE"), + MTK_FUNCTION(6, "CONN_BGF_MCU_TDO"), + MTK_FUNCTION(8, "IOBIST12") + ), + MTK_PIN( + 13, "GPIO13", + MTK_EINT_FUNCTION(0, 13), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO13"), + MTK_FUNCTION(1, "TP_GPIO8_AO"), + MTK_FUNCTION(2, "HFRP_JTAG0_TRSTN"), + MTK_FUNCTION(3, "MFG_EB_JTAG_TRSTN"), + MTK_FUNCTION(4, "SSPM_JTAG_TRSTN_VLP"), + MTK_FUNCTION(5, "SPM_JTAG_TRSTN_VLP"), + MTK_FUNCTION(6, "SCP_JTAG0_TRSTN_VLP"), + MTK_FUNCTION(7, "IO_JTAG_TRSTN"), + MTK_FUNCTION(8, "IOBIST13") + ), + MTK_PIN( + 14, "GPIO14", + MTK_EINT_FUNCTION(0, 14), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO14"), + MTK_FUNCTION(1, "TP_GPIO9_AO"), + MTK_FUNCTION(2, "HFRP_JTAG0_TCK"), + MTK_FUNCTION(3, "MFG_EB_JTAG_TCK"), + MTK_FUNCTION(4, "SSPM_JTAG_TCK_VLP"), + MTK_FUNCTION(5, "SPM_JTAG_TCK_VLP"), + MTK_FUNCTION(6, "SCP_JTAG0_TCK_VLP"), + MTK_FUNCTION(7, "IO_JTAG_TCK"), + MTK_FUNCTION(8, "IOBIST14") + ), + MTK_PIN( + 15, "GPIO15", + MTK_EINT_FUNCTION(0, 15), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO15"), + MTK_FUNCTION(1, "TP_GPIO10_AO"), + MTK_FUNCTION(2, "HFRP_JTAG0_TMS"), + MTK_FUNCTION(3, "MFG_EB_JTAG_TMS"), + MTK_FUNCTION(4, "SSPM_JTAG_TMS_VLP"), + MTK_FUNCTION(5, "SPM_JTAG_TMS_VLP"), + MTK_FUNCTION(6, "SCP_JTAG0_TMS_VLP"), + MTK_FUNCTION(7, "IO_JTAG_TMS"), + MTK_FUNCTION(8, "IOBIST15") + ), + MTK_PIN( + 16, "GPIO16", + MTK_EINT_FUNCTION(0, 16), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO16"), + MTK_FUNCTION(1, "TP_GPIO11_AO"), + MTK_FUNCTION(2, "HFRP_JTAG0_TDI"), + MTK_FUNCTION(3, "MFG_EB_JTAG_TDI"), + MTK_FUNCTION(4, "SSPM_JTAG_TDI_VLP"), + MTK_FUNCTION(5, "SPM_JTAG_TDI_VLP"), + MTK_FUNCTION(6, "SCP_JTAG0_TDI_VLP"), + MTK_FUNCTION(7, "IO_JTAG_TDI"), + MTK_FUNCTION(8, "IOBIST16") + ), + MTK_PIN( + 17, "GPIO17", + MTK_EINT_FUNCTION(0, 17), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO17"), + MTK_FUNCTION(1, "TP_GPIO12_AO"), + MTK_FUNCTION(2, "HFRP_JTAG0_TDO"), + MTK_FUNCTION(3, "MFG_EB_JTAG_TDO"), + MTK_FUNCTION(4, "SSPM_JTAG_TDO_VLP"), + MTK_FUNCTION(5, "SPM_JTAG_TDO_VLP"), + MTK_FUNCTION(6, "SCP_JTAG0_TDO_VLP"), + MTK_FUNCTION(7, "IO_JTAG_TDO"), + MTK_FUNCTION(8, "IOBIST17") + ), + MTK_PIN( + 18, "GPIO18", + MTK_EINT_FUNCTION(0, 18), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO18"), + MTK_FUNCTION(1, "MD1_SIM2_SRST"), + MTK_FUNCTION(2, "MD1_SIM1_SRST"), + MTK_FUNCTION(5, "IDDIG"), + MTK_FUNCTION(6, "TSFDC_EN"), + MTK_FUNCTION(8, "IOBIST18") + ), + MTK_PIN( + 19, "GPIO19", + MTK_EINT_FUNCTION(0, 19), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO19"), + MTK_FUNCTION(1, "MD1_SIM2_SCLK"), + MTK_FUNCTION(2, "MD1_SIM1_SCLK"), + MTK_FUNCTION(3, "TP_UTXD2_VCORE"), + MTK_FUNCTION(4, "SSPM_UTXD_AO_VCORE"), + MTK_FUNCTION(5, "MD32_1_TXD"), + MTK_FUNCTION(6, "UTXD2"), + MTK_FUNCTION(8, "IOBIST19") + ), + MTK_PIN( + 20, "GPIO20", + MTK_EINT_FUNCTION(0, 20), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO20"), + MTK_FUNCTION(1, "MD1_SIM2_SIO"), + MTK_FUNCTION(2, "MD1_SIM1_SIO"), + MTK_FUNCTION(3, "TP_URXD2_VCORE"), + MTK_FUNCTION(4, "SSPM_URXD_AO_VCORE"), + MTK_FUNCTION(5, "MD32_1_RXD"), + MTK_FUNCTION(6, "URXD2"), + MTK_FUNCTION(8, "IOBIST20") + ), + MTK_PIN( + 21, "GPIO21", + MTK_EINT_FUNCTION(0, 21), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO21"), + MTK_FUNCTION(1, "KPROW1"), + MTK_FUNCTION(2, "CONN_WIFI_TXD"), + MTK_FUNCTION(3, "CONN_BT_TXD"), + MTK_FUNCTION(4, "HFRP_UTXD1"), + MTK_FUNCTION(5, "TP_UTXD1_VCORE"), + MTK_FUNCTION(6, "CONN_BGF_UART0_TXD"), + MTK_FUNCTION(7, "MD_UTXD1"), + MTK_FUNCTION(8, "IOBIST21") + ), + MTK_PIN( + 22, "GPIO22", + MTK_EINT_FUNCTION(0, 22), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO22"), + MTK_FUNCTION(1, "KPCOL1"), + MTK_FUNCTION(3, "PMSR_SMAP"), + MTK_FUNCTION(4, "HFRP_URXD1"), + MTK_FUNCTION(5, "TP_URXD1_VCORE"), + MTK_FUNCTION(6, "CONN_BGF_UART0_RXD"), + MTK_FUNCTION(7, "MD_URXD1"), + MTK_FUNCTION(8, "IOBIST22") + ), + MTK_PIN( + 23, "GPIO23", + MTK_EINT_FUNCTION(0, 23), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO23"), + MTK_FUNCTION(3, "CONN_TCXOENA_REQ"), + MTK_FUNCTION(5, "USB_DRVVBUS"), + MTK_FUNCTION(7, "DBG_MON_A6"), + MTK_FUNCTION(8, "IOBIST23") + ), + MTK_PIN( + 24, "GPIO24", + MTK_EINT_FUNCTION(0, 24), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO24"), + MTK_FUNCTION(1, "KPROW0"), + MTK_FUNCTION(2, "I2SIN2_MCK"), + MTK_FUNCTION(5, "USB_DRVVBUS"), + MTK_FUNCTION(7, "DBG_MON_B0"), + MTK_FUNCTION(8, "IOBIST24") + ), + MTK_PIN( + 25, "GPIO25", + MTK_EINT_FUNCTION(0, 25), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO25"), + MTK_FUNCTION(4, "PWM_3"), + MTK_FUNCTION(7, "DBG_MON_A8"), + MTK_FUNCTION(8, "IOBIST25") + ), + MTK_PIN( + 26, "GPIO26", + MTK_EINT_FUNCTION(0, 26), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO26"), + MTK_FUNCTION(1, "CMFLASH0"), + MTK_FUNCTION(2, "CONN_TCXOENA_REQ"), + MTK_FUNCTION(3, "MD32_0_GPIO0"), + MTK_FUNCTION(4, "PWM_0"), + MTK_FUNCTION(5, "VBUSVALID"), + MTK_FUNCTION(8, "IOBIST26") + ), + MTK_PIN( + 27, "GPIO27", + MTK_EINT_FUNCTION(0, 27), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO27"), + MTK_FUNCTION(1, "CMFLASH1"), + MTK_FUNCTION(6, "DAP_SONIC_SWCK"), + MTK_FUNCTION(7, "DBG_MON_A10"), + MTK_FUNCTION(8, "IOBIST27") + ), + MTK_PIN( + 28, "GPIO28", + MTK_EINT_FUNCTION(0, 28), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO28"), + MTK_FUNCTION(1, "CMFLASH2"), + MTK_FUNCTION(4, "GPS_PPS"), + MTK_FUNCTION(6, "DAP_SONIC_SWD"), + MTK_FUNCTION(7, "DBG_MON_A11"), + MTK_FUNCTION(8, "IOBIST28") + ), + MTK_PIN( + 29, "GPIO29", + MTK_EINT_FUNCTION(0, 29), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO29"), + MTK_FUNCTION(1, "CMFLASH3"), + MTK_FUNCTION(3, "SCL10"), + MTK_FUNCTION(6, "DAP_MD32_SWCK"), + MTK_FUNCTION(7, "DBG_MON_A12"), + MTK_FUNCTION(8, "IOBIST29") + ), + MTK_PIN( + 30, "GPIO30", + MTK_EINT_FUNCTION(0, 30), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO30"), + MTK_FUNCTION(3, "SDA10"), + MTK_FUNCTION(6, "DAP_MD32_SWD"), + MTK_FUNCTION(7, "DBG_MON_A13"), + MTK_FUNCTION(8, "IOBIST30") + ), + MTK_PIN( + 31, "GPIO31", + MTK_EINT_FUNCTION(0, 31), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO31"), + MTK_FUNCTION(1, "CMVREF0"), + MTK_FUNCTION(3, "SCL12"), + MTK_FUNCTION(7, "DBG_MON_A14"), + MTK_FUNCTION(8, "IOBIST31") + ), + MTK_PIN( + 32, "GPIO32", + MTK_EINT_FUNCTION(0, 32), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO32"), + MTK_FUNCTION(1, "CMVREF1"), + MTK_FUNCTION(3, "SDA12"), + MTK_FUNCTION(7, "DBG_MON_A15"), + MTK_FUNCTION(8, "IOBIST32") + ), + MTK_PIN( + 33, "GPIO33", + MTK_EINT_FUNCTION(0, 33), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO33"), + MTK_FUNCTION(1, "CMVREF2"), + MTK_FUNCTION(3, "USB_DRVVBUS"), + MTK_FUNCTION(7, "DBG_MON_A16"), + MTK_FUNCTION(8, "IOBIST33") + ), + MTK_PIN( + 34, "GPIO34", + MTK_EINT_FUNCTION(0, 34), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO34"), + MTK_FUNCTION(1, "CMVREF3"), + MTK_FUNCTION(3, "VBUSVALID"), + MTK_FUNCTION(7, "DBG_MON_A17"), + MTK_FUNCTION(8, "IOBIST34") + ), + MTK_PIN( + 35, "GPIO35", + MTK_EINT_FUNCTION(0, 35), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO35"), + MTK_FUNCTION(1, "CMVREF4"), + MTK_FUNCTION(3, "IDDIG"), + MTK_FUNCTION(7, "DBG_MON_A18"), + MTK_FUNCTION(8, "IOBIST35") + ), + MTK_PIN( + 36, "GPIO36", + MTK_EINT_FUNCTION(0, 36), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO36"), + MTK_FUNCTION(1, "CMMCLK0"), + MTK_FUNCTION(2, "CLKM0"), + MTK_FUNCTION(7, "DBG_MON_A19"), + MTK_FUNCTION(8, "IOBIST36") + ), + MTK_PIN( + 37, "GPIO37", + MTK_EINT_FUNCTION(0, 37), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO37"), + MTK_FUNCTION(1, "CMMCLK1"), + MTK_FUNCTION(2, "CLKM1"), + MTK_FUNCTION(4, "MD32_1_GPIO0"), + MTK_FUNCTION(7, "DBG_MON_A20"), + MTK_FUNCTION(8, "IOBIST37") + ), + MTK_PIN( + 38, "GPIO38", + MTK_EINT_FUNCTION(0, 38), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO38"), + MTK_FUNCTION(1, "CMMCLK2"), + MTK_FUNCTION(2, "CLKM2"), + MTK_FUNCTION(7, "DBG_MON_A21"), + MTK_FUNCTION(8, "IOBIST38") + ), + MTK_PIN( + 39, "GPIO39", + MTK_EINT_FUNCTION(0, 39), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO39"), + MTK_FUNCTION(1, "CMMCLK3"), + MTK_FUNCTION(2, "CLKM3"), + MTK_FUNCTION(7, "DBG_MON_A22"), + MTK_FUNCTION(8, "IOBIST39") + ), + MTK_PIN( + 40, "GPIO40", + MTK_EINT_FUNCTION(0, 40), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO40"), + MTK_FUNCTION(1, "I2SIN1_MCK"), + MTK_FUNCTION(2, "IDDIG"), + MTK_FUNCTION(3, "IRRX_IN"), + MTK_FUNCTION(4, "GPS_PPS"), + MTK_FUNCTION(6, "ANT_SEL8"), + MTK_FUNCTION(8, "IOBIST40") + ), + MTK_PIN( + 41, "GPIO41", + MTK_EINT_FUNCTION(0, 41), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO41"), + MTK_FUNCTION(1, "I2SIN1_BCK"), + MTK_FUNCTION(4, "CONN_WF_MCU_AICE_TMSC"), + MTK_FUNCTION(6, "ANT_SEL9"), + MTK_FUNCTION(8, "IOBIST41") + ), + MTK_PIN( + 42, "GPIO42", + MTK_EINT_FUNCTION(0, 42), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO42"), + MTK_FUNCTION(1, "I2SIN1_LRCK"), + MTK_FUNCTION(4, "CONN_WF_MCU_AICE_TCKC"), + MTK_FUNCTION(6, "ANT_SEL10"), + MTK_FUNCTION(8, "IOBIST42") + ), + MTK_PIN( + 43, "GPIO43", + MTK_EINT_FUNCTION(0, 43), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO43"), + MTK_FUNCTION(1, "I2SOUT1_DO"), + MTK_FUNCTION(4, "CONN_BGF_MCU_AICE_TMSC"), + MTK_FUNCTION(6, "ANT_SEL11"), + MTK_FUNCTION(8, "IOBIST43") + ), + MTK_PIN( + 44, "GPIO44", + MTK_EINT_FUNCTION(0, 44), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO44"), + MTK_FUNCTION(1, "I2SIN1_DI"), + MTK_FUNCTION(4, "CONN_BGF_MCU_AICE_TCKC"), + MTK_FUNCTION(6, "ANT_SEL12"), + MTK_FUNCTION(8, "IOBIST44") + ), + MTK_PIN( + 45, "GPIO45", + MTK_EINT_FUNCTION(0, 45), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO45"), + MTK_FUNCTION(1, "I2SIN2_BCK"), + MTK_FUNCTION(2, "SCL11"), + MTK_FUNCTION(3, "BPI_BUS10"), + MTK_FUNCTION(4, "MD_UCTS0"), + MTK_FUNCTION(5, "TP_UCTS1_VCORE"), + MTK_FUNCTION(6, "HFRP_UCTS1"), + MTK_FUNCTION(7, "DBG_MON_B1"), + MTK_FUNCTION(8, "IOBIST45") + ), + MTK_PIN( + 46, "GPIO46", + MTK_EINT_FUNCTION(0, 46), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO46"), + MTK_FUNCTION(1, "I2SIN2_LRCK"), + MTK_FUNCTION(2, "SDA11"), + MTK_FUNCTION(3, "BPI_BUS11"), + MTK_FUNCTION(4, "MD_URTS0"), + MTK_FUNCTION(5, "TP_URTS1_VCORE"), + MTK_FUNCTION(6, "HFRP_URTS1"), + MTK_FUNCTION(7, "DBG_MON_B2"), + MTK_FUNCTION(8, "IOBIST46") + ), + MTK_PIN( + 47, "GPIO47", + MTK_EINT_FUNCTION(0, 47), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO47"), + MTK_FUNCTION(1, "I2SOUT2_DO"), + MTK_FUNCTION(2, "SCL1"), + MTK_FUNCTION(3, "BPI_BUS12"), + MTK_FUNCTION(4, "MD_UCTS1"), + MTK_FUNCTION(5, "TP_UCTS2_VCORE"), + MTK_FUNCTION(6, "UCTS2"), + MTK_FUNCTION(7, "DBG_MON_B3"), + MTK_FUNCTION(8, "IOBIST47") + ), + MTK_PIN( + 48, "GPIO48", + MTK_EINT_FUNCTION(0, 48), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO48"), + MTK_FUNCTION(1, "I2SIN2_DI"), + MTK_FUNCTION(2, "SDA1"), + MTK_FUNCTION(3, "BPI_BUS13"), + MTK_FUNCTION(4, "MD_URTS1"), + MTK_FUNCTION(5, "TP_URTS2_VCORE"), + MTK_FUNCTION(6, "URTS2"), + MTK_FUNCTION(7, "DBG_MON_B4"), + MTK_FUNCTION(8, "IOBIST48") + ), + MTK_PIN( + 49, "GPIO49", + MTK_EINT_FUNCTION(0, 49), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO49"), + MTK_FUNCTION(1, "UTXD0"), + MTK_FUNCTION(2, "MBISTREADEN_TRIGGER"), + MTK_FUNCTION(3, "MD_UTXD1"), + MTK_FUNCTION(4, "HFRP_UTXD1"), + MTK_FUNCTION(5, "MD32_0_TXD"), + MTK_FUNCTION(6, "PTA_TXD"), + MTK_FUNCTION(8, "IOBIST49") + ), + MTK_PIN( + 50, "GPIO50", + MTK_EINT_FUNCTION(0, 50), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO50"), + MTK_FUNCTION(1, "URXD0"), + MTK_FUNCTION(2, "MBISTWRITEEN_TRIGGER"), + MTK_FUNCTION(3, "MD_URXD1"), + MTK_FUNCTION(4, "HFRP_URXD1"), + MTK_FUNCTION(5, "MD32_0_RXD"), + MTK_FUNCTION(6, "PTA_RXD"), + MTK_FUNCTION(8, "IOBIST50") + ), + MTK_PIN( + 51, "GPIO51", + MTK_EINT_FUNCTION(0, 51), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO51"), + MTK_FUNCTION(1, "UTXD1"), + MTK_FUNCTION(2, "TP_UTXD1_VLP"), + MTK_FUNCTION(3, "TP_UTXD2_VLP"), + MTK_FUNCTION(4, "CONN_BGF_UART0_TXD"), + MTK_FUNCTION(5, "SSPM_UTXD_AO_VLP"), + MTK_FUNCTION(6, "MD_MCIF_UTXD0"), + MTK_FUNCTION(7, "MD_UTXD0"), + MTK_FUNCTION(8, "IOBIST51") + ), + MTK_PIN( + 52, "GPIO52", + MTK_EINT_FUNCTION(0, 52), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO52"), + MTK_FUNCTION(1, "URXD1"), + MTK_FUNCTION(2, "TP_URXD1_VLP"), + MTK_FUNCTION(3, "TP_URXD2_VLP"), + MTK_FUNCTION(4, "CONN_BGF_UART0_RXD"), + MTK_FUNCTION(5, "SSPM_URXD_AO_VLP"), + MTK_FUNCTION(6, "MD_MCIF_URXD0"), + MTK_FUNCTION(7, "MD_URXD0"), + MTK_FUNCTION(8, "IOBIST52") + ), + MTK_PIN( + 53, "GPIO53", + MTK_EINT_FUNCTION(0, 53), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO53"), + MTK_FUNCTION(1, "JTRSTN_SEL1_VCORE"), + MTK_FUNCTION(2, "SPM_JTAG_TRSTN_VCORE"), + MTK_FUNCTION(8, "IOBIST53") + ), + MTK_PIN( + 54, "GPIO54", + MTK_EINT_FUNCTION(0, 54), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO54"), + MTK_FUNCTION(1, "JTCK_SEL1_VCORE"), + MTK_FUNCTION(2, "SPM_JTAG_TCK_VCORE"), + MTK_FUNCTION(8, "IOBIST54") + ), + MTK_PIN( + 55, "GPIO55", + MTK_EINT_FUNCTION(0, 55), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO55"), + MTK_FUNCTION(1, "JTMS_SEL1_VCORE"), + MTK_FUNCTION(2, "SPM_JTAG_TMS_VCORE"), + MTK_FUNCTION(8, "IOBIST55") + ), + MTK_PIN( + 56, "GPIO56", + MTK_EINT_FUNCTION(0, 56), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO56"), + MTK_FUNCTION(1, "JTDI_SEL1_VCORE"), + MTK_FUNCTION(2, "SPM_JTAG_TDI_VCORE"), + MTK_FUNCTION(8, "IOBIST56") + ), + MTK_PIN( + 57, "GPIO57", + MTK_EINT_FUNCTION(0, 57), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO57"), + MTK_FUNCTION(1, "JTDO_SEL1_VCORE"), + MTK_FUNCTION(2, "SPM_JTAG_TDO_VCORE"), + MTK_FUNCTION(8, "IOBIST57") + ), + MTK_PIN( + 58, "GPIO58", + MTK_EINT_FUNCTION(0, 58), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO58"), + MTK_FUNCTION(1, "SPI4_CLK"), + MTK_FUNCTION(2, "MD_UTXD0"), + MTK_FUNCTION(3, "UTXD2"), + MTK_FUNCTION(4, "TP_UTXD1_VCORE"), + MTK_FUNCTION(5, "MBISTREADEN_TRIGGER"), + MTK_FUNCTION(6, "EXTIF0_ACT"), + MTK_FUNCTION(7, "DAP_SONIC_SWCK"), + MTK_FUNCTION(8, "IOBIST58") + ), + MTK_PIN( + 59, "GPIO59", + MTK_EINT_FUNCTION(0, 59), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO59"), + MTK_FUNCTION(1, "SPI4_CSB"), + MTK_FUNCTION(2, "MD_URXD0"), + MTK_FUNCTION(3, "URXD2"), + MTK_FUNCTION(4, "TP_URXD1_VCORE"), + MTK_FUNCTION(5, "MBISTWRITEEN_TRIGGER"), + MTK_FUNCTION(6, "EXTIF0_PRI"), + MTK_FUNCTION(7, "DAP_SONIC_SWD"), + MTK_FUNCTION(8, "IOBIST59") + ), + MTK_PIN( + 60, "GPIO60", + MTK_EINT_FUNCTION(0, 60), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO60"), + MTK_FUNCTION(1, "SPI4_MO"), + MTK_FUNCTION(6, "EXTIF0_GNT_B"), + MTK_FUNCTION(7, "DAP_MD32_SWCK"), + MTK_FUNCTION(8, "IOBIST60") + ), + MTK_PIN( + 61, "GPIO61", + MTK_EINT_FUNCTION(0, 61), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO61"), + MTK_FUNCTION(1, "SPI4_MI"), + MTK_FUNCTION(7, "DAP_MD32_SWD"), + MTK_FUNCTION(8, "IOBIST61") + ), + MTK_PIN( + 62, "GPIO62", + MTK_EINT_FUNCTION(0, 62), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO62"), + MTK_FUNCTION(1, "SCP_SPI1_CK"), + MTK_FUNCTION(2, "SPI1_CLK"), + MTK_FUNCTION(3, "TP_UTXD1_VLP"), + MTK_FUNCTION(5, "TP_GPIO0_AO"), + MTK_FUNCTION(6, "UTXD0"), + MTK_FUNCTION(7, "DBG_MON_A25"), + MTK_FUNCTION(8, "IOBIST62") + ), + MTK_PIN( + 63, "GPIO63", + MTK_EINT_FUNCTION(0, 63), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO63"), + MTK_FUNCTION(1, "SCP_SPI1_CS"), + MTK_FUNCTION(2, "SPI1_CSB"), + MTK_FUNCTION(3, "TP_URXD1_VLP"), + MTK_FUNCTION(5, "TP_GPIO1_AO"), + MTK_FUNCTION(6, "URXD0"), + MTK_FUNCTION(7, "DBG_MON_A26"), + MTK_FUNCTION(8, "IOBIST63") + ), + MTK_PIN( + 64, "GPIO64", + MTK_EINT_FUNCTION(0, 64), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO64"), + MTK_FUNCTION(1, "SCP_SPI1_MO"), + MTK_FUNCTION(2, "SPI1_MO"), + MTK_FUNCTION(5, "TP_GPIO2_AO"), + MTK_FUNCTION(7, "DBG_MON_A9"), + MTK_FUNCTION(8, "IOBIST64") + ), + MTK_PIN( + 65, "GPIO65", + MTK_EINT_FUNCTION(0, 65), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO65"), + MTK_FUNCTION(1, "SCP_SPI1_MI"), + MTK_FUNCTION(2, "SPI1_MI"), + MTK_FUNCTION(5, "TP_GPIO3_AO"), + MTK_FUNCTION(8, "IOBIST65") + ), + MTK_PIN( + 66, "GPIO66", + MTK_EINT_FUNCTION(0, 66), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO66"), + MTK_FUNCTION(1, "SCP_SPI2_CK"), + MTK_FUNCTION(2, "SPI2_CLK"), + MTK_FUNCTION(5, "TP_GPIO4_AO"), + MTK_FUNCTION(6, "UTXD1"), + MTK_FUNCTION(7, "DBG_MON_B13"), + MTK_FUNCTION(8, "IOBIST66") + ), + MTK_PIN( + 67, "GPIO67", + MTK_EINT_FUNCTION(0, 67), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO67"), + MTK_FUNCTION(1, "SCP_SPI2_CS"), + MTK_FUNCTION(2, "SPI2_CSB"), + MTK_FUNCTION(5, "TP_GPIO5_AO"), + MTK_FUNCTION(6, "URXD1"), + MTK_FUNCTION(7, "DBG_MON_B14"), + MTK_FUNCTION(8, "IOBIST67") + ), + MTK_PIN( + 68, "GPIO68", + MTK_EINT_FUNCTION(0, 68), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO68"), + MTK_FUNCTION(1, "SCP_SPI2_MO"), + MTK_FUNCTION(2, "SPI2_MO"), + MTK_FUNCTION(5, "TP_GPIO6_AO"), + MTK_FUNCTION(7, "DBG_MON_B15"), + MTK_FUNCTION(8, "IOBIST68") + ), + MTK_PIN( + 69, "GPIO69", + MTK_EINT_FUNCTION(0, 69), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO69"), + MTK_FUNCTION(1, "SCP_SPI2_MI"), + MTK_FUNCTION(2, "SPI2_MI"), + MTK_FUNCTION(5, "TP_GPIO7_AO"), + MTK_FUNCTION(7, "DBG_MON_B16"), + MTK_FUNCTION(8, "IOBIST69") + ), + MTK_PIN( + 70, "GPIO70", + MTK_EINT_FUNCTION(0, 70), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO70"), + MTK_FUNCTION(1, "SCP_SPI3_CK"), + MTK_FUNCTION(2, "SPI3_CLK"), + MTK_FUNCTION(3, "MD_INT4"), + MTK_FUNCTION(5, "TP_GPIO8_AO"), + MTK_FUNCTION(7, "DBG_MON_B17"), + MTK_FUNCTION(8, "IOBIST70") + ), + MTK_PIN( + 71, "GPIO71", + MTK_EINT_FUNCTION(0, 71), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO71"), + MTK_FUNCTION(1, "SCP_SPI3_CS"), + MTK_FUNCTION(2, "SPI3_CSB"), + MTK_FUNCTION(3, "MD_INT3"), + MTK_FUNCTION(5, "TP_GPIO9_AO"), + MTK_FUNCTION(7, "DBG_MON_B18"), + MTK_FUNCTION(8, "IOBIST71") + ), + MTK_PIN( + 72, "GPIO72", + MTK_EINT_FUNCTION(0, 72), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO72"), + MTK_FUNCTION(1, "SCP_SPI3_MO"), + MTK_FUNCTION(2, "SPI3_MO"), + MTK_FUNCTION(5, "TP_GPIO10_AO"), + MTK_FUNCTION(7, "DBG_MON_B19"), + MTK_FUNCTION(8, "IOBIST72") + ), + MTK_PIN( + 73, "GPIO73", + MTK_EINT_FUNCTION(0, 73), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO73"), + MTK_FUNCTION(1, "SCP_SPI3_MI"), + MTK_FUNCTION(2, "SPI3_MI"), + MTK_FUNCTION(5, "TP_GPIO11_AO"), + MTK_FUNCTION(7, "DBG_MON_B20"), + MTK_FUNCTION(8, "IOBIST73") + ), + MTK_PIN( + 74, "GPIO74", + MTK_EINT_FUNCTION(0, 74), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO74"), + MTK_FUNCTION(1, "SCP_SPI0_CK"), + MTK_FUNCTION(2, "SPI0_CLK"), + MTK_FUNCTION(3, "MD_INT0"), + MTK_FUNCTION(4, "BPI_BUS14"), + MTK_FUNCTION(5, "TP_GPIO12_AO"), + MTK_FUNCTION(7, "DBG_MON_B5"), + MTK_FUNCTION(8, "IOBIST74") + ), + MTK_PIN( + 75, "GPIO75", + MTK_EINT_FUNCTION(0, 75), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO75"), + MTK_FUNCTION(1, "SCP_SPI0_CS"), + MTK_FUNCTION(2, "SPI0_CSB"), + MTK_FUNCTION(4, "BPI_BUS15"), + MTK_FUNCTION(5, "TP_GPIO13_AO"), + MTK_FUNCTION(7, "DBG_MON_B6"), + MTK_FUNCTION(8, "IOBIST75") + ), + MTK_PIN( + 76, "GPIO76", + MTK_EINT_FUNCTION(0, 76), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO76"), + MTK_FUNCTION(1, "SCP_SPI0_MO"), + MTK_FUNCTION(2, "SPI0_MO"), + MTK_FUNCTION(4, "BPI_BUS16"), + MTK_FUNCTION(5, "TP_GPIO14_AO"), + MTK_FUNCTION(7, "DBG_MON_B7"), + MTK_FUNCTION(8, "IOBIST76") + ), + MTK_PIN( + 77, "GPIO77", + MTK_EINT_FUNCTION(0, 77), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO77"), + MTK_FUNCTION(1, "SCP_SPI0_MI"), + MTK_FUNCTION(2, "SPI0_MI"), + MTK_FUNCTION(4, "BPI_BUS17"), + MTK_FUNCTION(5, "TP_GPIO15_AO"), + MTK_FUNCTION(7, "DBG_MON_B8"), + MTK_FUNCTION(8, "IOBIST77") + ), + MTK_PIN( + 78, "GPIO78", + MTK_EINT_FUNCTION(0, 78), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO78"), + MTK_FUNCTION(1, "SPI5_CLK"), + MTK_FUNCTION(2, "MD32_0_TXD"), + MTK_FUNCTION(3, "PTA_TXD"), + MTK_FUNCTION(4, "TP_UTXD2_VCORE"), + MTK_FUNCTION(5, "SSPM_UTXD_AO_VCORE"), + MTK_FUNCTION(6, "UTXD2"), + MTK_FUNCTION(7, "DBG_MON_B21"), + MTK_FUNCTION(8, "IOBIST78") + ), + MTK_PIN( + 79, "GPIO79", + MTK_EINT_FUNCTION(0, 79), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO79"), + MTK_FUNCTION(1, "SPI5_CSB"), + MTK_FUNCTION(2, "MD32_0_RXD"), + MTK_FUNCTION(3, "PTA_RXD"), + MTK_FUNCTION(4, "TP_URXD2_VCORE"), + MTK_FUNCTION(5, "SSPM_URXD_AO_VCORE"), + MTK_FUNCTION(6, "URXD2"), + MTK_FUNCTION(7, "DBG_MON_B22"), + MTK_FUNCTION(8, "IOBIST79") + ), + MTK_PIN( + 80, "GPIO80", + MTK_EINT_FUNCTION(0, 80), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO80"), + MTK_FUNCTION(1, "SPI5_MO"), + MTK_FUNCTION(7, "DBG_MON_B23"), + MTK_FUNCTION(8, "IOBIST80") + ), + MTK_PIN( + 81, "GPIO81", + MTK_EINT_FUNCTION(0, 81), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO81"), + MTK_FUNCTION(1, "SPI5_MI"), + MTK_FUNCTION(7, "DBG_MON_B24"), + MTK_FUNCTION(8, "IOBIST81") + ), + MTK_PIN( + 82, "GPIO82", + MTK_EINT_FUNCTION(0, 82), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO82"), + MTK_FUNCTION(1, "MSDC1_CLK"), + MTK_FUNCTION(2, "MFG_EB_JTAG_TCK"), + MTK_FUNCTION(3, "UDI_TCK"), + MTK_FUNCTION(4, "CONN_DSP_JCK"), + MTK_FUNCTION(8, "IOBIST82") + ), + MTK_PIN( + 83, "GPIO83", + MTK_EINT_FUNCTION(0, 83), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO83"), + MTK_FUNCTION(1, "MSDC1_CMD"), + MTK_FUNCTION(2, "MFG_EB_JTAG_TMS"), + MTK_FUNCTION(3, "UDI_TMS"), + MTK_FUNCTION(4, "CONN_DSP_JMS"), + MTK_FUNCTION(6, "TSFDC_VCO_RST"), + MTK_FUNCTION(8, "IOBIST83") + ), + MTK_PIN( + 84, "GPIO84", + MTK_EINT_FUNCTION(0, 84), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO84"), + MTK_FUNCTION(1, "MSDC1_DAT0"), + MTK_FUNCTION(2, "MFG_EB_JTAG_TDI"), + MTK_FUNCTION(3, "UDI_TDI"), + MTK_FUNCTION(4, "CONN_DSP_JDI"), + MTK_FUNCTION(6, "TSFDC_TSSEL2"), + MTK_FUNCTION(8, "IOBIST84") + ), + MTK_PIN( + 85, "GPIO85", + MTK_EINT_FUNCTION(0, 85), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO85"), + MTK_FUNCTION(1, "MSDC1_DAT1"), + MTK_FUNCTION(2, "MFG_EB_JTAG_TDO"), + MTK_FUNCTION(3, "UDI_TDO"), + MTK_FUNCTION(4, "CONN_DSP_JDO"), + MTK_FUNCTION(6, "TSFDC_TSSEL1"), + MTK_FUNCTION(8, "IOBIST85") + ), + MTK_PIN( + 86, "GPIO86", + MTK_EINT_FUNCTION(0, 86), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO86"), + MTK_FUNCTION(1, "MSDC1_DAT2"), + MTK_FUNCTION(2, "MFG_EB_JTAG_TRSTN"), + MTK_FUNCTION(3, "UDI_NTRST"), + MTK_FUNCTION(6, "TSFDC_TSSEL0"), + MTK_FUNCTION(8, "IOBIST86") + ), + MTK_PIN( + 87, "GPIO87", + MTK_EINT_FUNCTION(0, 87), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO87"), + MTK_FUNCTION(1, "MSDC1_DAT3"), + MTK_FUNCTION(2, "IRRX_IN"), + MTK_FUNCTION(4, "CONN_DSP_JINTP"), + MTK_FUNCTION(6, "TSFDC_RCK_SELB"), + MTK_FUNCTION(8, "IOBIST87") + ), + MTK_PIN( + 88, "GPIO88", + MTK_EINT_FUNCTION(0, 88), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO88"), + MTK_FUNCTION(1, "MD1_SIM1_SCLK"), + MTK_FUNCTION(2, "MD1_SIM2_SCLK"), + MTK_FUNCTION(4, "CONN_DSP_L5_JINTP"), + MTK_FUNCTION(6, "TSFDC_26M"), + MTK_FUNCTION(8, "IOBIST88") + ), + MTK_PIN( + 89, "GPIO89", + MTK_EINT_FUNCTION(0, 89), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO89"), + MTK_FUNCTION(1, "MD1_SIM1_SRST"), + MTK_FUNCTION(2, "MD1_SIM2_SRST"), + MTK_FUNCTION(3, "SPM_JTAG_TRSTN_VCORE"), + MTK_FUNCTION(5, "MCUPM_JTAG_TRSTN"), + MTK_FUNCTION(6, "TSFDC_SDO"), + MTK_FUNCTION(8, "IOBIST89") + ), + MTK_PIN( + 90, "GPIO90", + MTK_EINT_FUNCTION(0, 90), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO90"), + MTK_FUNCTION(1, "MD1_SIM1_SIO"), + MTK_FUNCTION(2, "MD1_SIM2_SIO"), + MTK_FUNCTION(3, "SPM_JTAG_TCK_VCORE"), + MTK_FUNCTION(4, "CONN_DSP_L5_JCK"), + MTK_FUNCTION(5, "MCUPM_JTAG_TCK"), + MTK_FUNCTION(6, "TSFDC_FOUT"), + MTK_FUNCTION(8, "IOBIST90") + ), + MTK_PIN( + 91, "GPIO91", + MTK_EINT_FUNCTION(0, 91), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO91"), + MTK_FUNCTION(1, "MD1_SIM2_SCLK"), + MTK_FUNCTION(2, "MD1_SIM1_SCLK"), + MTK_FUNCTION(3, "SPM_JTAG_TMS_VCORE"), + MTK_FUNCTION(4, "CONN_DSP_L5_JMS"), + MTK_FUNCTION(5, "MCUPM_JTAG_TMS"), + MTK_FUNCTION(6, "TSFDC_SCK"), + MTK_FUNCTION(8, "IOBIST91") + ), + MTK_PIN( + 92, "GPIO92", + MTK_EINT_FUNCTION(0, 92), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO92"), + MTK_FUNCTION(1, "MD1_SIM2_SRST"), + MTK_FUNCTION(2, "MD1_SIM1_SRST"), + MTK_FUNCTION(3, "SPM_JTAG_TDI_VCORE"), + MTK_FUNCTION(4, "CONN_DSP_L5_JDI"), + MTK_FUNCTION(5, "MCUPM_JTAG_TDI"), + MTK_FUNCTION(6, "TSFDC_SDI"), + MTK_FUNCTION(8, "IOBIST92") + ), + MTK_PIN( + 93, "GPIO93", + MTK_EINT_FUNCTION(0, 93), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO93"), + MTK_FUNCTION(1, "MD1_SIM2_SIO"), + MTK_FUNCTION(2, "MD1_SIM1_SIO"), + MTK_FUNCTION(3, "SPM_JTAG_TDO_VCORE"), + MTK_FUNCTION(4, "CONN_DSP_L5_JDO"), + MTK_FUNCTION(5, "MCUPM_JTAG_TDO"), + MTK_FUNCTION(6, "TSFDC_SCF"), + MTK_FUNCTION(8, "IOBIST93") + ), + MTK_PIN( + 94, "GPIO94", + MTK_EINT_FUNCTION(0, 94), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO94"), + MTK_FUNCTION(1, "MD_INT1_C2K_UIM0_HOT_PLUG"), + MTK_FUNCTION(2, "MD_INT2_C2K_UIM1_HOT_PLUG"), + MTK_FUNCTION(3, "SRCLKENAI0"), + MTK_FUNCTION(6, "MD_MCIF_UTXD0"), + MTK_FUNCTION(8, "IOBIST94") + ), + MTK_PIN( + 95, "GPIO95", + MTK_EINT_FUNCTION(0, 95), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO95"), + MTK_FUNCTION(1, "MD_INT2_C2K_UIM1_HOT_PLUG"), + MTK_FUNCTION(2, "MD_INT1_C2K_UIM0_HOT_PLUG"), + MTK_FUNCTION(3, "SRCLKENAI1"), + MTK_FUNCTION(4, "SRCLKENA1"), + MTK_FUNCTION(6, "MD_MCIF_URXD0"), + MTK_FUNCTION(8, "IOBIST95") + ), + MTK_PIN( + 96, "GPIO96", + MTK_EINT_FUNCTION(0, 96), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO96"), + MTK_FUNCTION(1, "DSI_TE"), + MTK_FUNCTION(7, "DBG_MON_B25"), + MTK_FUNCTION(8, "IOBIST96") + ), + MTK_PIN( + 97, "GPIO97", + MTK_EINT_FUNCTION(0, 97), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO97"), + MTK_FUNCTION(1, "LCM_RST"), + MTK_FUNCTION(7, "DBG_MON_B26"), + MTK_FUNCTION(8, "IOBIST97") + ), + MTK_PIN( + 98, "GPIO98", + MTK_EINT_FUNCTION(0, 98), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO98"), + MTK_FUNCTION(1, "DISP_PWM"), + MTK_FUNCTION(2, "PWM_2"), + MTK_FUNCTION(7, "DBG_MON_B27"), + MTK_FUNCTION(8, "IOBIST98") + ), + MTK_PIN( + 99, "GPIO99", + MTK_EINT_FUNCTION(0, 99), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO99"), + MTK_FUNCTION(1, "ANT_SEL0"), + MTK_FUNCTION(2, "CONN_BPI_BUS17_ANT0"), + MTK_FUNCTION(3, "GPS_L1_ELNA_EN"), + MTK_FUNCTION(4, "EXT_FRAME_SYNC"), + MTK_FUNCTION(5, "SCL6"), + MTK_FUNCTION(8, "IOBIST99") + ), + MTK_PIN( + 100, "GPIO100", + MTK_EINT_FUNCTION(0, 100), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO100"), + MTK_FUNCTION(1, "ANT_SEL1"), + MTK_FUNCTION(2, "CONN_BPI_BUS18_ANT1"), + MTK_FUNCTION(3, "GPS_L5_ELNA_EN"), + MTK_FUNCTION(4, "AGPS_SYNC"), + MTK_FUNCTION(5, "SDA6"), + MTK_FUNCTION(8, "IOBIST100") + ), + MTK_PIN( + 101, "GPIO101", + MTK_EINT_FUNCTION(0, 101), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO101"), + MTK_FUNCTION(1, "ANT_SEL2"), + MTK_FUNCTION(2, "CONN_BPI_BUS19_ANT2"), + MTK_FUNCTION(3, "UDI_NTRST"), + MTK_FUNCTION(4, "CONN_WF_MCU_TRST_B"), + MTK_FUNCTION(8, "IOBIST101") + ), + MTK_PIN( + 102, "GPIO102", + MTK_EINT_FUNCTION(0, 102), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO102"), + MTK_FUNCTION(1, "ANT_SEL3"), + MTK_FUNCTION(2, "CONN_BPI_BUS20_ANT3"), + MTK_FUNCTION(3, "UDI_TCK"), + MTK_FUNCTION(4, "CONN_WF_MCU_TCK"), + MTK_FUNCTION(8, "IOBIST102") + ), + MTK_PIN( + 103, "GPIO103", + MTK_EINT_FUNCTION(0, 103), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO103"), + MTK_FUNCTION(1, "ANT_SEL4"), + MTK_FUNCTION(2, "CONN_BPI_BUS21_ANT4"), + MTK_FUNCTION(3, "UDI_TMS"), + MTK_FUNCTION(4, "CONN_WF_MCU_TMS"), + MTK_FUNCTION(8, "IOBIST103") + ), + MTK_PIN( + 104, "GPIO104", + MTK_EINT_FUNCTION(0, 104), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO104"), + MTK_FUNCTION(1, "ANT_SEL5"), + MTK_FUNCTION(2, "CONN_BPI_BUS16_OLAT5"), + MTK_FUNCTION(3, "UDI_TDI"), + MTK_FUNCTION(4, "CONN_WF_MCU_TDI"), + MTK_FUNCTION(8, "IOBIST104") + ), + MTK_PIN( + 105, "GPIO105", + MTK_EINT_FUNCTION(0, 105), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO105"), + MTK_FUNCTION(1, "ANT_SEL6"), + MTK_FUNCTION(2, "CONN_TCXOENA_REQ"), + MTK_FUNCTION(3, "UDI_TDO"), + MTK_FUNCTION(4, "CONN_WF_MCU_TDO"), + MTK_FUNCTION(8, "IOBIST105") + ), + MTK_PIN( + 106, "GPIO106", + MTK_EINT_FUNCTION(0, 106), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO106"), + MTK_FUNCTION(1, "BPI_BUS0"), + MTK_FUNCTION(2, "CONN_BPI_BUS10"), + MTK_FUNCTION(4, "MFG_TSFDC_EN"), + MTK_FUNCTION(5, "I2SOUT4_DATA0"), + MTK_FUNCTION(6, "ANT_SEL7"), + MTK_FUNCTION(8, "IOBIST106") + ), + MTK_PIN( + 107, "GPIO107", + MTK_EINT_FUNCTION(0, 107), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO107"), + MTK_FUNCTION(1, "BPI_BUS1"), + MTK_FUNCTION(2, "CONN_BPI_BUS11_OLAT0"), + MTK_FUNCTION(4, "MFG_TSFDC_VCO_RST"), + MTK_FUNCTION(5, "I2SOUT4_DATA1"), + MTK_FUNCTION(6, "ANT_SEL8"), + MTK_FUNCTION(8, "IOBIST107") + ), + MTK_PIN( + 108, "GPIO108", + MTK_EINT_FUNCTION(0, 108), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO108"), + MTK_FUNCTION(1, "BPI_BUS2"), + MTK_FUNCTION(2, "CONN_BPI_BUS12_OLAT1"), + MTK_FUNCTION(3, "CONN_TCXOENA_REQ"), + MTK_FUNCTION(4, "MFG_TSFDC_TSSEL2"), + MTK_FUNCTION(5, "I2SOUT4_DATA2"), + MTK_FUNCTION(6, "ANT_SEL9"), + MTK_FUNCTION(8, "IOBIST108") + ), + MTK_PIN( + 109, "GPIO109", + MTK_EINT_FUNCTION(0, 109), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO109"), + MTK_FUNCTION(1, "BPI_BUS3"), + MTK_FUNCTION(2, "CONN_BPI_BUS13_OLAT2"), + MTK_FUNCTION(4, "MFG_TSFDC_TSSEL1"), + MTK_FUNCTION(5, "I2SOUT4_DATA3"), + MTK_FUNCTION(6, "ANT_SEL10"), + MTK_FUNCTION(8, "IOBIST109") + ), + MTK_PIN( + 110, "GPIO110", + MTK_EINT_FUNCTION(0, 110), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO110"), + MTK_FUNCTION(1, "BPI_BUS4"), + MTK_FUNCTION(2, "CONN_BPI_BUS14_OLAT3"), + MTK_FUNCTION(3, "GPS_L1_ELNA_EN"), + MTK_FUNCTION(4, "MFG_TSFDC_TSSEL0"), + MTK_FUNCTION(5, "I2SIN4_BCK"), + MTK_FUNCTION(6, "ANT_SEL11"), + MTK_FUNCTION(8, "IOBIST110") + ), + MTK_PIN( + 111, "GPIO111", + MTK_EINT_FUNCTION(0, 111), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO111"), + MTK_FUNCTION(1, "BPI_BUS5"), + MTK_FUNCTION(2, "CONN_BPI_BUS15_OLAT4"), + MTK_FUNCTION(3, "GPS_L5_ELNA_EN"), + MTK_FUNCTION(4, "MFG_TSFDC_RCK_SELB"), + MTK_FUNCTION(5, "I2SIN4_DATA0"), + MTK_FUNCTION(6, "ANT_SEL12"), + MTK_FUNCTION(8, "IOBIST111") + ), + MTK_PIN( + 112, "GPIO112", + MTK_EINT_FUNCTION(0, 112), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO112"), + MTK_FUNCTION(1, "BPI_BUS6"), + MTK_FUNCTION(2, "CONN_BPI_BUS6"), + MTK_FUNCTION(3, "MIPI3_D_SDATA"), + MTK_FUNCTION(4, "MFG_TSFDC_SDO"), + MTK_FUNCTION(5, "I2SIN4_DATA1"), + MTK_FUNCTION(6, "ANT_SEL13"), + MTK_FUNCTION(8, "IOBIST112") + ), + MTK_PIN( + 113, "GPIO113", + MTK_EINT_FUNCTION(0, 113), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO113"), + MTK_FUNCTION(1, "BPI_BUS7"), + MTK_FUNCTION(2, "CONN_BPI_BUS7"), + MTK_FUNCTION(3, "MIPI3_D_SCLK"), + MTK_FUNCTION(4, "MFG_TSFDC_FOUT"), + MTK_FUNCTION(5, "I2SIN4_DATA2"), + MTK_FUNCTION(6, "ANT_SEL14"), + MTK_FUNCTION(8, "IOBIST113") + ), + MTK_PIN( + 114, "GPIO114", + MTK_EINT_FUNCTION(0, 114), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO114"), + MTK_FUNCTION(1, "BPI_BUS8"), + MTK_FUNCTION(2, "CONN_BPI_BUS8"), + MTK_FUNCTION(3, "MIPI4_D_SDATA"), + MTK_FUNCTION(4, "SCL9"), + MTK_FUNCTION(5, "I2SIN4_DATA3"), + MTK_FUNCTION(6, "ANT_SEL15"), + MTK_FUNCTION(8, "IOBIST114") + ), + MTK_PIN( + 115, "GPIO115", + MTK_EINT_FUNCTION(0, 115), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO115"), + MTK_FUNCTION(1, "BPI_BUS9"), + MTK_FUNCTION(2, "CONN_BPI_BUS9"), + MTK_FUNCTION(3, "MIPI4_D_SCLK"), + MTK_FUNCTION(4, "SDA9"), + MTK_FUNCTION(5, "I2SIN4_LRCK"), + MTK_FUNCTION(6, "ANT_SEL16"), + MTK_FUNCTION(8, "IOBIST115") + ), + MTK_PIN( + 116, "GPIO116", + MTK_EINT_FUNCTION(0, 116), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO116"), + MTK_FUNCTION(1, "MD_UCNT_A_TGL"), + MTK_FUNCTION(8, "IOBIST116") + ), + MTK_PIN( + 117, "GPIO117", + MTK_EINT_FUNCTION(0, 117), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO117"), + MTK_FUNCTION(1, "DIGRF_IRQ"), + MTK_FUNCTION(8, "IOBIST117") + ), + MTK_PIN( + 118, "GPIO118", + MTK_EINT_FUNCTION(0, 118), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO118"), + MTK_FUNCTION(8, "IOBIST118") + ), + MTK_PIN( + 119, "GPIO119", + MTK_EINT_FUNCTION(0, 119), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO119"), + MTK_FUNCTION(1, "AP_GOOD"), + MTK_FUNCTION(3, "CONN_WIFI_TXD"), + MTK_FUNCTION(4, "GPS_PPS"), + MTK_FUNCTION(5, "PMSR_SMAP"), + MTK_FUNCTION(6, "AGPS_SYNC"), + MTK_FUNCTION(8, "IOBIST119") + ), + MTK_PIN( + 120, "GPIO120", + MTK_EINT_FUNCTION(0, 120), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO120"), + MTK_FUNCTION(1, "KPCOL0_VLP"), + MTK_FUNCTION(8, "IOBIST120") + ), + MTK_PIN( + 121, "GPIO121", + MTK_EINT_FUNCTION(0, 121), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO121"), + MTK_FUNCTION(1, "SRCLKENAI0"), + MTK_FUNCTION(2, "SRCLKENAI1"), + MTK_FUNCTION(8, "IOBIST121") + ), + MTK_PIN( + 122, "GPIO122", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO122"), + MTK_FUNCTION(1, "WATCHDOG"), + MTK_FUNCTION(8, "IOBIST122") + ), + MTK_PIN( + 123, "GPIO123", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO123"), + MTK_FUNCTION(8, "IOBIST123") + ), + MTK_PIN( + 124, "GPIO124", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO124"), + MTK_FUNCTION(1, "SRCLKENA0"), + MTK_FUNCTION(8, "IOBIST124") + ), + MTK_PIN( + 125, "GPIO125", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO125"), + MTK_FUNCTION(1, "RTC32K_CK"), + MTK_FUNCTION(8, "IOBIST125") + ), + MTK_PIN( + 126, "GPIO126", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO126"), + MTK_FUNCTION(1, "SPMI_M_SCL"), + MTK_FUNCTION(8, "IOBIST126") + ), + MTK_PIN( + 127, "GPIO127", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO127"), + MTK_FUNCTION(1, "SPMI_M_SDA"), + MTK_FUNCTION(8, "IOBIST127") + ), + MTK_PIN( + 128, "GPIO128", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO128"), + MTK_FUNCTION(1, "SPMI_P_SCL"), + MTK_FUNCTION(8, "IOBIST128") + ), + MTK_PIN( + 129, "GPIO129", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO129"), + MTK_FUNCTION(1, "SPMI_P_SDA"), + MTK_FUNCTION(8, "IOBIST129") + ), + MTK_PIN( + 130, "GPIO130", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO130"), + MTK_FUNCTION(3, "BPI_BUS13"), + MTK_FUNCTION(8, "IOBIST130") + ), + MTK_PIN( + 131, "GPIO131", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO131"), + MTK_FUNCTION(1, "SPI6_CLK"), + MTK_FUNCTION(2, "KPROW2"), + MTK_FUNCTION(3, "BPI_BUS14"), + MTK_FUNCTION(4, "CONN_BT_TXD"), + MTK_FUNCTION(5, "MD32_1_TXD"), + MTK_FUNCTION(6, "PTA_TXD"), + MTK_FUNCTION(8, "IOBIST131") + ), + MTK_PIN( + 132, "GPIO132", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO132"), + MTK_FUNCTION(1, "SPI6_CSB"), + MTK_FUNCTION(2, "KPCOL2"), + MTK_FUNCTION(3, "BPI_BUS15"), + MTK_FUNCTION(5, "MD32_1_RXD"), + MTK_FUNCTION(6, "PTA_RXD"), + MTK_FUNCTION(8, "IOBIST132") + ), + MTK_PIN( + 133, "GPIO133", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO133"), + MTK_FUNCTION(1, "SPI6_MO"), + MTK_FUNCTION(2, "CLKM0"), + MTK_FUNCTION(3, "BPI_BUS16"), + MTK_FUNCTION(4, "CMFLASH2"), + MTK_FUNCTION(8, "IOBIST133") + ), + MTK_PIN( + 134, "GPIO134", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO134"), + MTK_FUNCTION(1, "SPI6_MI"), + MTK_FUNCTION(2, "CLKM1"), + MTK_FUNCTION(3, "BPI_BUS17"), + MTK_FUNCTION(4, "CMFLASH3"), + MTK_FUNCTION(8, "IOBIST134") + ), + MTK_PIN( + 135, "GPIO135", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO135"), + MTK_FUNCTION(1, "SCP_SCL1"), + MTK_FUNCTION(2, "CLKM2"), + MTK_FUNCTION(3, "SCP_DMIC_CLK"), + MTK_FUNCTION(4, "DMIC_CLK"), + MTK_FUNCTION(5, "TP_GPIO13_AO"), + MTK_FUNCTION(7, "DBG_MON_A23"), + MTK_FUNCTION(8, "IOBIST135") + ), + MTK_PIN( + 136, "GPIO136", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO136"), + MTK_FUNCTION(1, "SCP_SDA1"), + MTK_FUNCTION(2, "CLKM3"), + MTK_FUNCTION(3, "SCP_DMIC_DAT"), + MTK_FUNCTION(4, "DMIC_DAT"), + MTK_FUNCTION(5, "TP_GPIO14_AO"), + MTK_FUNCTION(7, "DBG_MON_A24"), + MTK_FUNCTION(8, "IOBIST136") + ), + MTK_PIN( + 137, "GPIO137", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO137"), + MTK_FUNCTION(2, "IRRX_IN"), + MTK_FUNCTION(3, "MD_INT0"), + MTK_FUNCTION(4, "SPMI_M_TRIG_FLAG"), + MTK_FUNCTION(5, "TP_GPIO15_AO"), + MTK_FUNCTION(6, "UFS_MPHY_SCL"), + MTK_FUNCTION(8, "IOBIST137") + ), + MTK_PIN( + 138, "GPIO138", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO138"), + MTK_FUNCTION(2, "PWM_VLP"), + MTK_FUNCTION(3, "MD_INT3"), + MTK_FUNCTION(5, "TP_GPIO0_AO"), + MTK_FUNCTION(6, "UFS_MPHY_SDA"), + MTK_FUNCTION(8, "IOBIST138") + ), + MTK_PIN( + 139, "GPIO139", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO139"), + MTK_FUNCTION(1, "SCL0"), + MTK_FUNCTION(4, "BPI_BUS18"), + MTK_FUNCTION(7, "DBG_MON_B28"), + MTK_FUNCTION(8, "IOBIST139") + ), + MTK_PIN( + 140, "GPIO140", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO140"), + MTK_FUNCTION(1, "SDA0"), + MTK_FUNCTION(4, "BPI_BUS19"), + MTK_FUNCTION(7, "DBG_MON_B29"), + MTK_FUNCTION(8, "IOBIST140") + ), + MTK_PIN( + 141, "GPIO141", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO141"), + MTK_FUNCTION(1, "SCL1"), + MTK_FUNCTION(2, "SCL9"), + MTK_FUNCTION(4, "BPI_BUS20"), + MTK_FUNCTION(7, "DBG_MON_B30"), + MTK_FUNCTION(8, "IOBIST141") + ), + MTK_PIN( + 142, "GPIO142", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO142"), + MTK_FUNCTION(1, "SDA1"), + MTK_FUNCTION(2, "SDA9"), + MTK_FUNCTION(4, "BPI_BUS21"), + MTK_FUNCTION(7, "DBG_MON_B31"), + MTK_FUNCTION(8, "IOBIST142") + ), + MTK_PIN( + 143, "GPIO143", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO143"), + MTK_FUNCTION(1, "SCL2"), + MTK_FUNCTION(7, "DBG_MON_B9"), + MTK_FUNCTION(8, "IOBIST143") + ), + MTK_PIN( + 144, "GPIO144", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO144"), + MTK_FUNCTION(1, "SDA2"), + MTK_FUNCTION(7, "DBG_MON_B10"), + MTK_FUNCTION(8, "IOBIST144") + ), + MTK_PIN( + 145, "GPIO145", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO145"), + MTK_FUNCTION(1, "SCL3"), + MTK_FUNCTION(3, "DMIC1_CLK"), + MTK_FUNCTION(7, "DBG_MON_B11"), + MTK_FUNCTION(8, "IOBIST145") + ), + MTK_PIN( + 146, "GPIO146", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO146"), + MTK_FUNCTION(1, "SDA3"), + MTK_FUNCTION(3, "DMIC1_DAT"), + MTK_FUNCTION(7, "DBG_MON_B12"), + MTK_FUNCTION(8, "IOBIST146") + ), + MTK_PIN( + 147, "GPIO147", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO147"), + MTK_FUNCTION(1, "SCL4"), + MTK_FUNCTION(7, "DBG_MON_A31"), + MTK_FUNCTION(8, "IOBIST147") + ), + MTK_PIN( + 148, "GPIO148", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO148"), + MTK_FUNCTION(1, "SDA4"), + MTK_FUNCTION(7, "DBG_MON_A7"), + MTK_FUNCTION(8, "IOBIST148") + ), + MTK_PIN( + 149, "GPIO149", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO149"), + MTK_FUNCTION(1, "SCL5"), + MTK_FUNCTION(8, "IOBIST149") + ), + MTK_PIN( + 150, "GPIO150", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO150"), + MTK_FUNCTION(1, "SDA5"), + MTK_FUNCTION(8, "IOBIST150") + ), + MTK_PIN( + 151, "GPIO151", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO151"), + MTK_FUNCTION(1, "SCL6"), + MTK_FUNCTION(2, "SCL11"), + MTK_FUNCTION(8, "IOBIST151") + ), + MTK_PIN( + 152, "GPIO152", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO152"), + MTK_FUNCTION(1, "SDA6"), + MTK_FUNCTION(2, "SDA11"), + MTK_FUNCTION(8, "IOBIST152") + ), + MTK_PIN( + 153, "GPIO153", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO153"), + MTK_FUNCTION(1, "SCL7"), + MTK_FUNCTION(7, "DBG_MON_A3"), + MTK_FUNCTION(8, "IOBIST153") + ), + MTK_PIN( + 154, "GPIO154", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO154"), + MTK_FUNCTION(1, "SDA7"), + MTK_FUNCTION(7, "DBG_MON_A4"), + MTK_FUNCTION(8, "IOBIST154") + ), + MTK_PIN( + 155, "GPIO155", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO155"), + MTK_FUNCTION(1, "SCL8"), + MTK_FUNCTION(7, "DBG_MON_A5"), + MTK_FUNCTION(8, "IOBIST155") + ), + MTK_PIN( + 156, "GPIO156", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO156"), + MTK_FUNCTION(1, "SDA8"), + MTK_FUNCTION(8, "IOBIST156") + ), + MTK_PIN( + 157, "GPIO157", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO157"), + MTK_FUNCTION(1, "SCP_SCL0"), + MTK_FUNCTION(3, "SCP_SCL5"), + MTK_FUNCTION(4, "TP_UCTS1_VLP"), + MTK_FUNCTION(5, "TP_GPIO0_AO"), + MTK_FUNCTION(7, "DBG_MON_A27"), + MTK_FUNCTION(8, "IOBIST157") + ), + MTK_PIN( + 158, "GPIO158", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO158"), + MTK_FUNCTION(1, "SCP_SDA0"), + MTK_FUNCTION(3, "SCP_SDA5"), + MTK_FUNCTION(4, "TP_URTS1_VLP"), + MTK_FUNCTION(5, "TP_GPIO1_AO"), + MTK_FUNCTION(7, "DBG_MON_A28"), + MTK_FUNCTION(8, "IOBIST158") + ), + MTK_PIN( + 159, "GPIO159", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO159"), + MTK_FUNCTION(1, "SCP_SCL1"), + MTK_FUNCTION(3, "SCP_SCL4"), + MTK_FUNCTION(4, "TP_UCTS2_VLP"), + MTK_FUNCTION(5, "TP_GPIO2_AO"), + MTK_FUNCTION(7, "DBG_MON_A29"), + MTK_FUNCTION(8, "IOBIST159") + ), + MTK_PIN( + 160, "GPIO160", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO160"), + MTK_FUNCTION(1, "SCP_SDA1"), + MTK_FUNCTION(3, "SCP_SDA4"), + MTK_FUNCTION(4, "TP_URTS2_VLP"), + MTK_FUNCTION(5, "TP_GPIO3_AO"), + MTK_FUNCTION(7, "DBG_MON_A30"), + MTK_FUNCTION(8, "IOBIST160") + ), + MTK_PIN( + 161, "GPIO161", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO161"), + MTK_FUNCTION(1, "SCP_SCL2"), + MTK_FUNCTION(2, "SCL10"), + MTK_FUNCTION(3, "SCP_DMIC_CLK"), + MTK_FUNCTION(4, "DMIC_CLK"), + MTK_FUNCTION(5, "TP_GPIO4_AO"), + MTK_FUNCTION(6, "EXTIF0_PRI"), + MTK_FUNCTION(8, "IOBIST161") + ), + MTK_PIN( + 162, "GPIO162", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO162"), + MTK_FUNCTION(1, "SCP_SDA2"), + MTK_FUNCTION(2, "SDA10"), + MTK_FUNCTION(3, "SCP_DMIC_DAT"), + MTK_FUNCTION(4, "DMIC_DAT"), + MTK_FUNCTION(5, "TP_GPIO5_AO"), + MTK_FUNCTION(6, "EXTIF0_GNT_B"), + MTK_FUNCTION(8, "IOBIST162") + ), + MTK_PIN( + 163, "GPIO163", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO163"), + MTK_FUNCTION(1, "SCP_SCL3"), + MTK_FUNCTION(2, "SCL12"), + MTK_FUNCTION(5, "TP_GPIO6_AO"), + MTK_FUNCTION(7, "MBISTREADEN_TRIGGER"), + MTK_FUNCTION(8, "IOBIST163") + ), + MTK_PIN( + 164, "GPIO164", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO164"), + MTK_FUNCTION(1, "SCP_SDA3"), + MTK_FUNCTION(2, "SDA12"), + MTK_FUNCTION(5, "TP_GPIO7_AO"), + MTK_FUNCTION(7, "MBISTWRITEEN_TRIGGER"), + MTK_FUNCTION(8, "IOBIST164") + ), + MTK_PIN( + 165, "GPIO165", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO165"), + MTK_FUNCTION(1, "MIPI0_D_SCLK"), + MTK_FUNCTION(2, "CONN_MIPI0_SCLK"), + MTK_FUNCTION(3, "BPI_BUS18"), + MTK_FUNCTION(6, "ANT_SEL17"), + MTK_FUNCTION(8, "IOBIST165") + ), + MTK_PIN( + 166, "GPIO166", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO166"), + MTK_FUNCTION(1, "MIPI0_D_SDATA"), + MTK_FUNCTION(2, "CONN_MIPI0_SDATA"), + MTK_FUNCTION(3, "BPI_BUS19"), + MTK_FUNCTION(6, "ANT_SEL18"), + MTK_FUNCTION(8, "IOBIST166") + ), + MTK_PIN( + 167, "GPIO167", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO167"), + MTK_FUNCTION(1, "MIPI1_D_SCLK"), + MTK_FUNCTION(2, "CONN_MIPI1_SCLK"), + MTK_FUNCTION(3, "BPI_BUS20"), + MTK_FUNCTION(6, "ANT_SEL19"), + MTK_FUNCTION(8, "IOBIST167") + ), + MTK_PIN( + 168, "GPIO168", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO168"), + MTK_FUNCTION(1, "MIPI1_D_SDATA"), + MTK_FUNCTION(2, "CONN_MIPI1_SDATA"), + MTK_FUNCTION(3, "BPI_BUS21"), + MTK_FUNCTION(6, "ANT_SEL20"), + MTK_FUNCTION(8, "IOBIST168") + ), + MTK_PIN( + 169, "GPIO169", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO169"), + MTK_FUNCTION(1, "MIPI2_D_SCLK"), + MTK_FUNCTION(3, "BPI_BUS10"), + MTK_FUNCTION(6, "MD_GPS_L1_BLANK"), + MTK_FUNCTION(8, "IOBIST169") + ), + MTK_PIN( + 170, "GPIO170", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO170"), + MTK_FUNCTION(1, "MIPI2_D_SDATA"), + MTK_FUNCTION(3, "BPI_BUS11"), + MTK_FUNCTION(6, "MD_GPS_L5_BLANK"), + MTK_FUNCTION(8, "IOBIST170") + ), + MTK_PIN( + 171, "GPIO171", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO171"), + MTK_FUNCTION(1, "MIPI_M_SCLK"), + MTK_FUNCTION(8, "IOBIST171") + ), + MTK_PIN( + 172, "GPIO172", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO172"), + MTK_FUNCTION(1, "MIPI_M_SDATA"), + MTK_FUNCTION(8, "IOBIST172") + ), + MTK_PIN( + 173, "GPIO173", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO173"), + MTK_FUNCTION(1, "AUD_CLK_MOSI"), + MTK_FUNCTION(3, "AUD_CLK_MOSI"), + MTK_FUNCTION(8, "IOBIST173") + ), + MTK_PIN( + 174, "GPIO174", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO174"), + MTK_FUNCTION(1, "AUD_SYNC_MOSI"), + MTK_FUNCTION(8, "IOBIST174") + ), + MTK_PIN( + 175, "GPIO175", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO175"), + MTK_FUNCTION(1, "AUD_DAT_MOSI0"), + MTK_FUNCTION(3, "AUD_DAT_MOSI0"), + MTK_FUNCTION(8, "IOBIST175") + ), + MTK_PIN( + 176, "GPIO176", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO176"), + MTK_FUNCTION(1, "AUD_DAT_MOSI1"), + MTK_FUNCTION(3, "AUD_DAT_MOSI1"), + MTK_FUNCTION(8, "IOBIST176") + ), + MTK_PIN( + 177, "GPIO177", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO177"), + MTK_FUNCTION(1, "AUD_NLE_MOSI0"), + MTK_FUNCTION(2, "AUD_SYNC_MISO"), + MTK_FUNCTION(8, "IOBIST177") + ), + MTK_PIN( + 178, "GPIO178", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO178"), + MTK_FUNCTION(1, "AUD_NLE_MOSI1"), + MTK_FUNCTION(2, "AUD_CLK_MISO"), + MTK_FUNCTION(3, "AUD_CLK_MISO"), + MTK_FUNCTION(8, "IOBIST178") + ), + MTK_PIN( + 179, "GPIO179", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO179"), + MTK_FUNCTION(1, "AUD_DAT_MISO0"), + MTK_FUNCTION(2, "VOW_DAT_MISO"), + MTK_FUNCTION(3, "AUD_DAT_MISO0"), + MTK_FUNCTION(8, "IOBIST179") + ), + MTK_PIN( + 180, "GPIO180", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO180"), + MTK_FUNCTION(1, "AUD_DAT_MISO1"), + MTK_FUNCTION(2, "VOW_CLK_MISO"), + MTK_FUNCTION(3, "AUD_DAT_MISO1"), + MTK_FUNCTION(8, "IOBIST180") + ), + MTK_PIN( + 181, "GPIO181", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO181"), + MTK_FUNCTION(1, "SCP_VREQ_VAO"), + MTK_FUNCTION(8, "IOBIST181") + ), + MTK_PIN( + 182, "GPIO182", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO182"), + MTK_FUNCTION(1, "CONN_TOP_CLK"), + MTK_FUNCTION(8, "IOBIST182") + ), + MTK_PIN( + 183, "GPIO183", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO183"), + MTK_FUNCTION(1, "CONN_TOP_DATA"), + MTK_FUNCTION(8, "IOBIST183") + ), + MTK_PIN( + 184, "GPIO184", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO184"), + MTK_FUNCTION(1, "CONN_BT_CLK"), + MTK_FUNCTION(8, "IOBIST184") + ), + MTK_PIN( + 185, "GPIO185", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO185"), + MTK_FUNCTION(1, "CONN_BT_DATA"), + MTK_FUNCTION(8, "IOBIST185") + ), + MTK_PIN( + 186, "GPIO186", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO186"), + MTK_FUNCTION(1, "CONN_HRST_B"), + MTK_FUNCTION(8, "IOBIST186") + ), + MTK_PIN( + 187, "GPIO187", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO187"), + MTK_FUNCTION(1, "CONN_WB_PTA"), + MTK_FUNCTION(8, "IOBIST187") + ), + MTK_PIN( + 188, "GPIO188", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO188"), + MTK_FUNCTION(1, "CONN_WF_CTRL0"), + MTK_FUNCTION(8, "IOBIST188") + ), + MTK_PIN( + 189, "GPIO189", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO189"), + MTK_FUNCTION(1, "CONN_WF_CTRL1"), + MTK_FUNCTION(8, "IOBIST189") + ), + MTK_PIN( + 190, "GPIO190", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO190"), + MTK_FUNCTION(1, "CONN_WF_CTRL2"), + MTK_FUNCTION(8, "IOBIST190") + ), + MTK_PIN( + 191, "GPIO191", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO191"), + MTK_FUNCTION(1, "CONN_TOP_CLK_2"), + MTK_FUNCTION(8, "IOBIST191") + ), + MTK_PIN( + 192, "GPIO192", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO192"), + MTK_FUNCTION(1, "CONN_TOP_DATA_2"), + MTK_FUNCTION(8, "IOBIST192") + ), + MTK_PIN( + 193, "GPIO193", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO193"), + MTK_FUNCTION(1, "CONN_HRST_B_2"), + MTK_FUNCTION(8, "IOBIST193") + ), + MTK_PIN( + 194, "GPIO194", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO194"), + MTK_FUNCTION(1, "GPS_L1_ELNA_EN"), + MTK_FUNCTION(2, "MD_GPS_L1_BLANK"), + MTK_FUNCTION(8, "IOBIST194") + ), + MTK_PIN( + 195, "GPIO195", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO195"), + MTK_FUNCTION(1, "GPS_L5_ELNA_EN"), + MTK_FUNCTION(2, "MD_GPS_L5_BLANK"), + MTK_FUNCTION(3, "ANT_SEL21"), + MTK_FUNCTION(5, "SPMI_P_TRIG_FLAG"), + MTK_FUNCTION(8, "IOBIST195") + ), + MTK_PIN( + 196, "GPIO196", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO196"), + MTK_FUNCTION(1, "PAD_RESET_DRAM_0"), + MTK_FUNCTION(8, "IOBIST196") + ), + MTK_PIN_VEINT(197), + MTK_PIN_VEINT(198), + MTK_PIN_VEINT(199), + MTK_PIN_VEINT(200), + MTK_PIN_VEINT(201), + MTK_PIN_VEINT(202), + MTK_PIN_VEINT(203), + MTK_PIN_VEINT(204), + MTK_PIN_VEINT(205), + MTK_PIN_VEINT(206), + MTK_PIN_VEINT(207), + MTK_PIN_VEINT(208), + MTK_PIN_VEINT(209), + MTK_PIN_VEINT(210), + MTK_PIN_VEINT(211), + MTK_PIN_VEINT(212), + MTK_PIN_VEINT(213), + MTK_PIN_VEINT(214), + MTK_PIN_VEINT(215), + MTK_PIN_VEINT(216), +}; + +static struct mtk_eint_pin eint_pins_mt6858[] = { + MTK_EINT_PIN(0, 2, 0, 1), + MTK_EINT_PIN(1, 2, 1, 1), + MTK_EINT_PIN(2, 2, 2, 1), + MTK_EINT_PIN(3, 2, 3, 1), + MTK_EINT_PIN(4, 2, 4, 1), + MTK_EINT_PIN(5, 2, 5, 1), + MTK_EINT_PIN(6, 2, 6, 1), + MTK_EINT_PIN(7, 2, 7, 1), + MTK_EINT_PIN(8, 0, 0, 1), + MTK_EINT_PIN(9, 0, 1, 1), + MTK_EINT_PIN(10, 0, 2, 1), + MTK_EINT_PIN(11, 0, 3, 1), + MTK_EINT_PIN(12, 0, 4, 1), + MTK_EINT_PIN(13, 1, 0, 1), + MTK_EINT_PIN(14, 1, 1, 1), + MTK_EINT_PIN(15, 1, 2, 1), + MTK_EINT_PIN(16, 1, 3, 1), + MTK_EINT_PIN(17, 1, 4, 1), + MTK_EINT_PIN(18, 1, 5, 1), + MTK_EINT_PIN(19, 1, 6, 1), + MTK_EINT_PIN(20, 1, 7, 1), + MTK_EINT_PIN(21, 0, 5, 1), + MTK_EINT_PIN(22, 0, 6, 1), + MTK_EINT_PIN(23, 2, 8, 1), + MTK_EINT_PIN(24, 0, 7, 1), + MTK_EINT_PIN(25, 2, 18, 0), + MTK_EINT_PIN(26, 0, 8, 1), + MTK_EINT_PIN(27, 2, 9, 1), + MTK_EINT_PIN(28, 2, 10, 1), + MTK_EINT_PIN(29, 2, 11, 1), + MTK_EINT_PIN(30, 2, 12, 1), + MTK_EINT_PIN(31, 2, 13, 1), + MTK_EINT_PIN(32, 2, 14, 1), + MTK_EINT_PIN(33, 2, 15, 1), + MTK_EINT_PIN(34, 2, 16, 1), + MTK_EINT_PIN(35, 0, 9, 1), + MTK_EINT_PIN(36, 2, 17, 1), + MTK_EINT_PIN(37, 2, 19, 0), + MTK_EINT_PIN(38, 2, 20, 0), + MTK_EINT_PIN(39, 2, 21, 0), + MTK_EINT_PIN(40, 0, 10, 0), + MTK_EINT_PIN(41, 0, 11, 0), + MTK_EINT_PIN(42, 0, 12, 0), + MTK_EINT_PIN(43, 0, 13, 0), + MTK_EINT_PIN(44, 0, 14, 0), + MTK_EINT_PIN(45, 0, 15, 0), + MTK_EINT_PIN(46, 0, 16, 0), + MTK_EINT_PIN(47, 0, 17, 0), + MTK_EINT_PIN(48, 0, 18, 0), + MTK_EINT_PIN(49, 0, 19, 0), + MTK_EINT_PIN(50, 0, 20, 0), + MTK_EINT_PIN(51, 0, 21, 0), + MTK_EINT_PIN(52, 0, 22, 0), + MTK_EINT_PIN(53, 0, 23, 0), + MTK_EINT_PIN(54, 0, 24, 0), + MTK_EINT_PIN(55, 0, 25, 0), + MTK_EINT_PIN(56, 0, 26, 0), + MTK_EINT_PIN(57, 0, 27, 0), + MTK_EINT_PIN(58, 0, 28, 0), + MTK_EINT_PIN(59, 0, 29, 0), + MTK_EINT_PIN(60, 0, 30, 0), + MTK_EINT_PIN(61, 0, 31, 0), + MTK_EINT_PIN(62, 2, 22, 0), + MTK_EINT_PIN(63, 2, 23, 0), + MTK_EINT_PIN(64, 2, 24, 0), + MTK_EINT_PIN(65, 2, 25, 0), + MTK_EINT_PIN(66, 0, 32, 0), + MTK_EINT_PIN(67, 0, 33, 0), + MTK_EINT_PIN(68, 0, 34, 0), + MTK_EINT_PIN(69, 0, 35, 0), + MTK_EINT_PIN(70, 0, 36, 0), + MTK_EINT_PIN(71, 0, 37, 0), + MTK_EINT_PIN(72, 0, 38, 0), + MTK_EINT_PIN(73, 0, 39, 0), + MTK_EINT_PIN(74, 0, 40, 0), + MTK_EINT_PIN(75, 0, 41, 0), + MTK_EINT_PIN(76, 0, 42, 0), + MTK_EINT_PIN(77, 0, 43, 0), + MTK_EINT_PIN(78, 0, 44, 0), + MTK_EINT_PIN(79, 0, 45, 0), + MTK_EINT_PIN(80, 0, 46, 0), + MTK_EINT_PIN(81, 0, 47, 0), + MTK_EINT_PIN(82, 2, 26, 0), + MTK_EINT_PIN(83, 2, 27, 0), + MTK_EINT_PIN(84, 2, 28, 0), + MTK_EINT_PIN(85, 2, 29, 0), + MTK_EINT_PIN(86, 2, 30, 0), + MTK_EINT_PIN(87, 2, 31, 0), + MTK_EINT_PIN(88, 0, 48, 0), + MTK_EINT_PIN(89, 0, 49, 0), + MTK_EINT_PIN(90, 0, 50, 0), + MTK_EINT_PIN(91, 0, 51, 0), + MTK_EINT_PIN(92, 0, 52, 0), + MTK_EINT_PIN(93, 0, 53, 0), + MTK_EINT_PIN(94, 0, 54, 0), + MTK_EINT_PIN(95, 0, 55, 0), + MTK_EINT_PIN(96, 0, 56, 0), + MTK_EINT_PIN(97, 0, 57, 0), + MTK_EINT_PIN(98, 0, 58, 0), + MTK_EINT_PIN(99, 2, 32, 0), + MTK_EINT_PIN(100, 2, 33, 0), + MTK_EINT_PIN(101, 2, 34, 0), + MTK_EINT_PIN(102, 2, 35, 0), + MTK_EINT_PIN(103, 2, 36, 0), + MTK_EINT_PIN(104, 2, 37, 0), + MTK_EINT_PIN(105, 2, 38, 0), + MTK_EINT_PIN(106, 0, 59, 0), + MTK_EINT_PIN(107, 0, 60, 0), + MTK_EINT_PIN(108, 0, 61, 0), + MTK_EINT_PIN(109, 0, 62, 0), + MTK_EINT_PIN(110, 0, 63, 0), + MTK_EINT_PIN(111, 0, 64, 0), + MTK_EINT_PIN(112, 0, 65, 0), + MTK_EINT_PIN(113, 0, 66, 0), + MTK_EINT_PIN(114, 0, 67, 0), + MTK_EINT_PIN(115, 0, 68, 0), + MTK_EINT_PIN(116, 0, 69, 0), + MTK_EINT_PIN(117, 0, 70, 0), + MTK_EINT_PIN(118, 0, 71, 0), + MTK_EINT_PIN(119, 0, 72, 0), + MTK_EINT_PIN(120, 0, 73, 0), + MTK_EINT_PIN(121, 0, 74, 0), + MTK_EINT_PIN(122, EINT_INVALID_BASE, 0, 0), + MTK_EINT_PIN(123, EINT_INVALID_BASE, 0, 0), + MTK_EINT_PIN(124, EINT_INVALID_BASE, 0, 0), + MTK_EINT_PIN(125, EINT_INVALID_BASE, 0, 0), + MTK_EINT_PIN(126, EINT_INVALID_BASE, 0, 0), + MTK_EINT_PIN(127, EINT_INVALID_BASE, 0, 0), + MTK_EINT_PIN(128, EINT_INVALID_BASE, 0, 0), + MTK_EINT_PIN(129, EINT_INVALID_BASE, 0, 0), + MTK_EINT_PIN(130, EINT_INVALID_BASE, 0, 0), + MTK_EINT_PIN(131, EINT_INVALID_BASE, 0, 0), + MTK_EINT_PIN(132, EINT_INVALID_BASE, 0, 0), + MTK_EINT_PIN(133, EINT_INVALID_BASE, 0, 0), + MTK_EINT_PIN(134, EINT_INVALID_BASE, 0, 0), + MTK_EINT_PIN(135, EINT_INVALID_BASE, 0, 0), + MTK_EINT_PIN(136, EINT_INVALID_BASE, 0, 0), + MTK_EINT_PIN(137, EINT_INVALID_BASE, 0, 0), + MTK_EINT_PIN(138, EINT_INVALID_BASE, 0, 0), + MTK_EINT_PIN(139, EINT_INVALID_BASE, 0, 0), + MTK_EINT_PIN(140, EINT_INVALID_BASE, 0, 0), + MTK_EINT_PIN(141, EINT_INVALID_BASE, 0, 0), + MTK_EINT_PIN(142, EINT_INVALID_BASE, 0, 0), + MTK_EINT_PIN(143, EINT_INVALID_BASE, 0, 0), + MTK_EINT_PIN(144, EINT_INVALID_BASE, 0, 0), + MTK_EINT_PIN(145, EINT_INVALID_BASE, 0, 0), + MTK_EINT_PIN(146, EINT_INVALID_BASE, 0, 0), + MTK_EINT_PIN(147, EINT_INVALID_BASE, 0, 0), + MTK_EINT_PIN(148, EINT_INVALID_BASE, 0, 0), + MTK_EINT_PIN(149, EINT_INVALID_BASE, 0, 0), + MTK_EINT_PIN(150, EINT_INVALID_BASE, 0, 0), + MTK_EINT_PIN(151, EINT_INVALID_BASE, 0, 0), + MTK_EINT_PIN(152, EINT_INVALID_BASE, 0, 0), + MTK_EINT_PIN(153, EINT_INVALID_BASE, 0, 0), + MTK_EINT_PIN(154, EINT_INVALID_BASE, 0, 0), + MTK_EINT_PIN(155, EINT_INVALID_BASE, 0, 0), + MTK_EINT_PIN(156, EINT_INVALID_BASE, 0, 0), + MTK_EINT_PIN(157, EINT_INVALID_BASE, 0, 0), + MTK_EINT_PIN(158, EINT_INVALID_BASE, 0, 0), + MTK_EINT_PIN(159, EINT_INVALID_BASE, 0, 0), + MTK_EINT_PIN(160, EINT_INVALID_BASE, 0, 0), + MTK_EINT_PIN(161, EINT_INVALID_BASE, 0, 0), + MTK_EINT_PIN(162, EINT_INVALID_BASE, 0, 0), + MTK_EINT_PIN(163, EINT_INVALID_BASE, 0, 0), + MTK_EINT_PIN(164, EINT_INVALID_BASE, 0, 0), + MTK_EINT_PIN(165, EINT_INVALID_BASE, 0, 0), + MTK_EINT_PIN(166, EINT_INVALID_BASE, 0, 0), + MTK_EINT_PIN(167, EINT_INVALID_BASE, 0, 0), + MTK_EINT_PIN(168, EINT_INVALID_BASE, 0, 0), + MTK_EINT_PIN(169, EINT_INVALID_BASE, 0, 0), + MTK_EINT_PIN(170, EINT_INVALID_BASE, 0, 0), + MTK_EINT_PIN(171, EINT_INVALID_BASE, 0, 0), + MTK_EINT_PIN(172, EINT_INVALID_BASE, 0, 0), + MTK_EINT_PIN(173, EINT_INVALID_BASE, 0, 0), + MTK_EINT_PIN(174, EINT_INVALID_BASE, 0, 0), + MTK_EINT_PIN(175, EINT_INVALID_BASE, 0, 0), + MTK_EINT_PIN(176, EINT_INVALID_BASE, 0, 0), + MTK_EINT_PIN(177, EINT_INVALID_BASE, 0, 0), + MTK_EINT_PIN(178, EINT_INVALID_BASE, 0, 0), + MTK_EINT_PIN(179, EINT_INVALID_BASE, 0, 0), + MTK_EINT_PIN(180, EINT_INVALID_BASE, 0, 0), + MTK_EINT_PIN(181, EINT_INVALID_BASE, 0, 0), + MTK_EINT_PIN(182, EINT_INVALID_BASE, 0, 0), + MTK_EINT_PIN(183, EINT_INVALID_BASE, 0, 0), + MTK_EINT_PIN(184, EINT_INVALID_BASE, 0, 0), + MTK_EINT_PIN(185, EINT_INVALID_BASE, 0, 0), + MTK_EINT_PIN(186, EINT_INVALID_BASE, 0, 0), + MTK_EINT_PIN(187, EINT_INVALID_BASE, 0, 0), + MTK_EINT_PIN(188, EINT_INVALID_BASE, 0, 0), + MTK_EINT_PIN(189, EINT_INVALID_BASE, 0, 0), + MTK_EINT_PIN(190, EINT_INVALID_BASE, 0, 0), + MTK_EINT_PIN(191, EINT_INVALID_BASE, 0, 0), + MTK_EINT_PIN(192, EINT_INVALID_BASE, 0, 0), + MTK_EINT_PIN(193, EINT_INVALID_BASE, 0, 0), + MTK_EINT_PIN(194, EINT_INVALID_BASE, 0, 0), + MTK_EINT_PIN(195, EINT_INVALID_BASE, 0, 0), + MTK_EINT_PIN(196, EINT_INVALID_BASE, 0, 0), + MTK_EINT_PIN(197, 3, 0, 0), + MTK_EINT_PIN(198, 3, 1, 0), + MTK_EINT_PIN(199, 3, 2, 0), + MTK_EINT_PIN(200, 3, 3, 0), + MTK_EINT_PIN(201, 3, 4, 0), + MTK_EINT_PIN(202, 3, 5, 0), + MTK_EINT_PIN(203, 3, 6, 0), + MTK_EINT_PIN(204, 3, 7, 0), + MTK_EINT_PIN(205, 3, 8, 0), + MTK_EINT_PIN(206, 3, 9, 0), + MTK_EINT_PIN(207, 3, 10, 0), + MTK_EINT_PIN(208, 3, 11, 0), + MTK_EINT_PIN(209, 3, 12, 0), + MTK_EINT_PIN(210, 3, 13, 0), + MTK_EINT_PIN(211, 3, 14, 0), + MTK_EINT_PIN(212, 3, 15, 0), + MTK_EINT_PIN(213, 3, 16, 0), + MTK_EINT_PIN(214, 3, 17, 0), + MTK_EINT_PIN(215, 3, 18, 0), + MTK_EINT_PIN(216, 3, 19, 0), +}; + +#endif /* __PINCTRL_MTK_MT6858_H */ diff --git a/drivers/pinctrl/mediatek/pinctrl-mtmips.c b/drivers/pinctrl/mediatek/pinctrl-mtmips.c index efd77b6c56a1..b2d7a79ff9cc 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mtmips.c +++ b/drivers/pinctrl/mediatek/pinctrl-mtmips.c @@ -349,3 +349,7 @@ int mtmips_pinctrl_init(struct platform_device *pdev, return PTR_ERR_OR_ZERO(dev); } +EXPORT_SYMBOL_NS_GPL(mtmips_pinctrl_init, "MTK_PINCTRL"); + +MODULE_DESCRIPTION("MediaTek MIPS Pinctrl Common Driver"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/pinctrl/mediatek/pinctrl-paris.c b/drivers/pinctrl/mediatek/pinctrl-paris.c index 23f04b24fd65..09098b68f725 100644 --- a/drivers/pinctrl/mediatek/pinctrl-paris.c +++ b/drivers/pinctrl/mediatek/pinctrl-paris.c @@ -957,7 +957,7 @@ static int mtk_build_gpiochip(struct mtk_pinctrl *hw) chip->base = -1; chip->ngpio = hw->soc->npins; - ret = gpiochip_add_data(chip, hw); + ret = devm_gpiochip_add_data(hw->dev, chip, hw); if (ret < 0) return ret; diff --git a/drivers/pinctrl/mediatek/pinctrl-rt2880.c b/drivers/pinctrl/mediatek/pinctrl-rt2880.c index e0366721a515..e7099325c5ef 100644 --- a/drivers/pinctrl/mediatek/pinctrl-rt2880.c +++ b/drivers/pinctrl/mediatek/pinctrl-rt2880.c @@ -59,3 +59,7 @@ static int __init rt2880_pinctrl_init(void) return platform_driver_register(&rt2880_pinctrl_driver); } core_initcall_sync(rt2880_pinctrl_init); + +MODULE_DESCRIPTION("MediaTek RT2880 Pinctrl Driver"); +MODULE_LICENSE("GPL v2"); +MODULE_IMPORT_NS("MTK_PINCTRL"); diff --git a/drivers/pinctrl/mediatek/pinctrl-rt305x.c b/drivers/pinctrl/mediatek/pinctrl-rt305x.c index 77bd4d1f6122..fa6407e86f79 100644 --- a/drivers/pinctrl/mediatek/pinctrl-rt305x.c +++ b/drivers/pinctrl/mediatek/pinctrl-rt305x.c @@ -138,3 +138,7 @@ static int __init rt305x_pinctrl_init(void) return platform_driver_register(&rt305x_pinctrl_driver); } core_initcall_sync(rt305x_pinctrl_init); + +MODULE_DESCRIPTION("MediaTek RT305X Pinctrl Driver"); +MODULE_LICENSE("GPL v2"); +MODULE_IMPORT_NS("MTK_PINCTRL"); diff --git a/drivers/pinctrl/mediatek/pinctrl-rt3883.c b/drivers/pinctrl/mediatek/pinctrl-rt3883.c index eeaf344c3647..838bf811cd0c 100644 --- a/drivers/pinctrl/mediatek/pinctrl-rt3883.c +++ b/drivers/pinctrl/mediatek/pinctrl-rt3883.c @@ -106,3 +106,7 @@ static int __init rt3883_pinctrl_init(void) return platform_driver_register(&rt3883_pinctrl_driver); } core_initcall_sync(rt3883_pinctrl_init); + +MODULE_DESCRIPTION("MediaTek RT3883 Pinctrl Driver"); +MODULE_LICENSE("GPL v2"); +MODULE_IMPORT_NS("MTK_PINCTRL"); diff --git a/drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c b/drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c index a68d55caef25..6150cde7e824 100644 --- a/drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c +++ b/drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c @@ -25,6 +25,7 @@ #define NPCM8XX_GCR_SRCNT 0x068 #define NPCM8XX_GCR_FLOCKR1 0x074 #define NPCM8XX_GCR_DSCNT 0x078 +#define NPCM8XX_GCR_INTCR4 0x0c0 #define NPCM8XX_GCR_I2CSEGSEL 0x0e0 #define NPCM8XX_GCR_MFSEL1 0x260 #define NPCM8XX_GCR_MFSEL2 0x264 @@ -77,6 +78,11 @@ #define NPCM8XX_GPIO_PER_BANK 32 #define NPCM8XX_GPIO_BANK_NUM 8 #define NPCM8XX_GCR_NONE 0 +#define NPCM8XX_INTCR4_R1_RMII_EN BIT(12) +#define NPCM8XX_INTCR4_R2_RMII_EN BIT(13) +#define NPCM8XX_INTCR4_RMII3_EN BIT(14) +#define NPCM8XX_GCR_DSCNT_RG2DS_SHIFT 6 +#define NPCM8XX_GCR_DSCNT_RG2DS_MASK GENMASK(7, 6) #define NPCM8XX_DEBOUNCE_MAX 4 #define NPCM8XX_DEBOUNCE_NSEC 40 @@ -290,17 +296,33 @@ static void npcmgpio_irq_unmask(struct irq_data *d) static unsigned int npcmgpio_irq_startup(struct irq_data *d) { - struct gpio_chip *gc = irq_data_get_irq_chip_data(d); - unsigned int gpio = irqd_to_hwirq(d); - - /* active-high, input, clear interrupt, enable interrupt */ - npcmgpio_direction_input(gc, gpio); npcmgpio_irq_ack(d); npcmgpio_irq_unmask(d); return 0; } +static int npcmgpio_irq_request_resources(struct irq_data *d) +{ + struct gpio_chip *gc = irq_data_get_irq_chip_data(d); + unsigned int gpio = irqd_to_hwirq(d); + int ret; + + ret = npcmgpio_direction_input(gc, gpio); + if (ret) + return ret; + + return gpiochip_reqres_irq(gc, gpio); +} + +static void npcmgpio_irq_release_resources(struct irq_data *d) +{ + struct gpio_chip *gc = irq_data_get_irq_chip_data(d); + unsigned int gpio = irqd_to_hwirq(d); + + gpiochip_relres_irq(gc, gpio); +} + static struct irq_chip npcmgpio_irqchip = { .name = "NPCM8XX-GPIO-IRQ", .irq_ack = npcmgpio_irq_ack, @@ -308,8 +330,9 @@ static struct irq_chip npcmgpio_irqchip = { .irq_mask = npcmgpio_irq_mask, .irq_set_type = npcmgpio_set_irq_type, .irq_startup = npcmgpio_irq_startup, + .irq_request_resources = npcmgpio_irq_request_resources, + .irq_release_resources = npcmgpio_irq_release_resources, .flags = IRQCHIP_MASK_ON_SUSPEND | IRQCHIP_IMMUTABLE, - GPIOCHIP_IRQ_RESOURCE_HELPERS, }; static const int gpi36_pins[] = { 36 }; @@ -537,7 +560,7 @@ static const int wdog2_pins[] = { 219 }; static const int bmcuart0a_pins[] = { 41, 42 }; static const int bmcuart0b_pins[] = { 48, 49 }; -static const int bmcuart1_pins[] = { 43, 44, 62, 63 }; +static const int bmcuart1_pins[] = { 43, 63 }; static const int scipme_pins[] = { 169 }; static const int smi_pins[] = { 170 }; @@ -1282,6 +1305,7 @@ static struct pinfunction npcm8xx_funcs[] = { #define DRIVE_STRENGTH_LO_SHIFT 8 #define DRIVE_STRENGTH_HI_SHIFT 12 #define DRIVE_STRENGTH_MASK GENMASK(15, 8) +#define DSTR_RG2 BIT(16) #define DSTR(lo, hi) (((lo) << DRIVE_STRENGTH_LO_SHIFT) | \ ((hi) << DRIVE_STRENGTH_HI_SHIFT)) @@ -1414,10 +1438,10 @@ static const struct npcm8xx_pincfg pincfg[] = { NPCM8XX_PINCFG(107, i3c5, MFSEL3, 22, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW), NPCM8XX_PINCFG(108, sg1mdio, MFSEL4, 21, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW), NPCM8XX_PINCFG(109, sg1mdio, MFSEL4, 21, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW), - NPCM8XX_PINCFG(110, rg2, MFSEL4, 24, ddr, MFSEL3, 26, rmii3, MFSEL5, 11, none, NONE, 0, none, NONE, 0, SLEW), - NPCM8XX_PINCFG(111, rg2, MFSEL4, 24, ddr, MFSEL3, 26, rmii3, MFSEL5, 11, none, NONE, 0, none, NONE, 0, SLEW), - NPCM8XX_PINCFG(112, rg2, MFSEL4, 24, ddr, MFSEL3, 26, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW), - NPCM8XX_PINCFG(113, rg2, MFSEL4, 24, ddr, MFSEL3, 26, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW), + NPCM8XX_PINCFG(110, rg2, MFSEL4, 24, ddr, MFSEL3, 26, rmii3, MFSEL5, 11, none, NONE, 0, none, NONE, 0, DSTR_RG2 | SLEW), + NPCM8XX_PINCFG(111, rg2, MFSEL4, 24, ddr, MFSEL3, 26, rmii3, MFSEL5, 11, none, NONE, 0, none, NONE, 0, DSTR_RG2 | SLEW), + NPCM8XX_PINCFG(112, rg2, MFSEL4, 24, ddr, MFSEL3, 26, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR_RG2 | SLEW), + NPCM8XX_PINCFG(113, rg2, MFSEL4, 24, ddr, MFSEL3, 26, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR_RG2 | SLEW), NPCM8XX_PINCFG(114, smb0, MFSEL1, 6, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0), NPCM8XX_PINCFG(115, smb0, MFSEL1, 6, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0), NPCM8XX_PINCFG(116, smb1, MFSEL1, 7, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0), @@ -1440,14 +1464,14 @@ static const struct npcm8xx_pincfg pincfg[] = { NPCM8XX_PINCFG(133, smb10, MFSEL4, 13, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0), NPCM8XX_PINCFG(134, smb11, MFSEL4, 14, smb23b, MFSEL6, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0), NPCM8XX_PINCFG(135, smb11, MFSEL4, 14, smb23b, MFSEL6, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0), - NPCM8XX_PINCFG(136, jm1, MFSEL5, 15, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW), - NPCM8XX_PINCFG(137, jm1, MFSEL5, 15, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW), - NPCM8XX_PINCFG(138, jm1, MFSEL5, 15, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW), - NPCM8XX_PINCFG(139, jm1, MFSEL5, 15, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW), - NPCM8XX_PINCFG(140, jm1, MFSEL5, 15, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW), - NPCM8XX_PINCFG(141, smb7b, I2CSEGSEL, 27, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0), - NPCM8XX_PINCFG(142, smb7d, I2CSEGSEL, 29, tp_smb1, MFSEL7, 11, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW), - NPCM8XX_PINCFG(143, smb7d, I2CSEGSEL, 29, tp_smb1, MFSEL7, 11, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0), + NPCM8XX_PINCFG(136, jm1, MFSEL5, 15, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW), + NPCM8XX_PINCFG(137, jm1, MFSEL5, 15, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW), + NPCM8XX_PINCFG(138, jm1, MFSEL5, 15, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW), + NPCM8XX_PINCFG(139, jm1, MFSEL5, 15, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW), + NPCM8XX_PINCFG(140, jm1, MFSEL5, 15, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW), + NPCM8XX_PINCFG(141, smb7b, I2CSEGSEL, 27, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW), + NPCM8XX_PINCFG(142, smb7d, I2CSEGSEL, 29, tp_smb1, MFSEL7, 11, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW), + NPCM8XX_PINCFG(143, smb7d, I2CSEGSEL, 29, tp_smb1, MFSEL7, 11, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW), NPCM8XX_PINCFG(144, pwm4, MFSEL2, 20, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(4, 8)), NPCM8XX_PINCFG(145, pwm5, MFSEL2, 21, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(4, 8)), NPCM8XX_PINCFG(146, pwm6, MFSEL2, 22, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(4, 8)), @@ -1508,8 +1532,8 @@ static const struct npcm8xx_pincfg pincfg[] = { NPCM8XX_PINCFG(201, r1, MFSEL3, 9, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPO), NPCM8XX_PINCFG(202, smb0c, I2CSEGSEL, 1, fm0, MFSEL6, 16, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW), NPCM8XX_PINCFG(203, faninx, MFSEL3, 3, spi1cs0, MFSEL3, 4, fm1, MFSEL6, 17, none, NONE, 0, none, NONE, 0, DSTR(8, 12)), - NPCM8XX_PINCFG(208, rg2, MFSEL4, 24, ddr, MFSEL3, 26, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW), /* DSCNT */ - NPCM8XX_PINCFG(209, rg2, MFSEL4, 24, ddr, MFSEL3, 26, rmii3, MFSEL5, 11, none, NONE, 0, none, NONE, 0, SLEW), /* DSCNT */ + NPCM8XX_PINCFG(208, rg2, MFSEL4, 24, ddr, MFSEL3, 26, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR_RG2 | SLEW), + NPCM8XX_PINCFG(209, rg2, MFSEL4, 24, ddr, MFSEL3, 26, rmii3, MFSEL5, 11, none, NONE, 0, none, NONE, 0, DSTR_RG2 | SLEW), NPCM8XX_PINCFG(210, rg2, MFSEL4, 24, ddr, MFSEL3, 26, rmii3, MFSEL5, 11, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW), NPCM8XX_PINCFG(211, rg2, MFSEL4, 24, ddr, MFSEL3, 26, rmii3, MFSEL5, 11, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW), NPCM8XX_PINCFG(212, rg2, MFSEL4, 24, ddr, MFSEL3, 26, r3rxer, MFSEL6, 30, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW), @@ -1559,7 +1583,7 @@ static const struct pinctrl_pin_desc npcm8xx_pins[] = { PINCTRL_PIN(4, "GPIO4/IOX2_DI/SMB1D_SDA"), PINCTRL_PIN(5, "GPIO5/IOX2_LD/SMB1D_SCL"), PINCTRL_PIN(6, "GPIO6/IOX2_CK/SMB2D_SDA"), - PINCTRL_PIN(7, "GPIO7/IOX2_D0/SMB2D_SCL"), + PINCTRL_PIN(7, "GPIO7/IOX2_DO/SMB2D_SCL"), PINCTRL_PIN(8, "GPIO8/LKGPO1/TP_GPIO0"), PINCTRL_PIN(9, "GPIO9/LKGPO2/TP_GPIO1"), PINCTRL_PIN(10, "GPIO10/IOXH_LD/SMB6D_SCL/SMB16_SCL"), @@ -1795,6 +1819,61 @@ static const struct pinctrl_pin_desc npcm8xx_pins[] = { PINCTRL_PIN(251, "JM2/CP1_GPIO"), }; +static u32 npcm8xx_rmii_output_enable_mask(unsigned int pin) +{ + switch (pin) { + case 178: + case 179: + case 180: + case 181: + case 182: + case 193: + case 201: + return NPCM8XX_INTCR4_R1_RMII_EN; + case 84: + case 85: + case 86: + case 87: + case 88: + case 89: + case 200: + return NPCM8XX_INTCR4_R2_RMII_EN; + case 110: + case 111: + case 209: + case 210: + case 211: + case 214: + case 215: + return NPCM8XX_INTCR4_RMII3_EN; + default: + return 0; + } +} + +static void npcm8xx_set_rmii_output_enable(struct regmap *gcr_regmap, + const unsigned int *pin, + int pin_number, int mode) +{ + u32 mask = 0; + u32 val = 0; + u32 bit; + int i; + + for (i = 0; i < pin_number; i++) { + bit = npcm8xx_rmii_output_enable_mask(pin[i]); + mask |= bit; + + if ((mode == fn_r1 && bit == NPCM8XX_INTCR4_R1_RMII_EN) || + (mode == fn_r2 && bit == NPCM8XX_INTCR4_R2_RMII_EN) || + (mode == fn_rmii3 && bit == NPCM8XX_INTCR4_RMII3_EN)) + val |= bit; + } + + if (mask) + regmap_update_bits(gcr_regmap, NPCM8XX_GCR_INTCR4, mask, val); +} + /* Enable mode in pin group */ static void npcm8xx_setfunc(struct regmap *gcr_regmap, const unsigned int *pin, int pin_number, int mode) @@ -1833,6 +1912,8 @@ static void npcm8xx_setfunc(struct regmap *gcr_regmap, const unsigned int *pin, BIT(cfg->bit4) : 0); } } + + npcm8xx_set_rmii_output_enable(gcr_regmap, pin, pin_number, mode); } static int npcm8xx_get_slew_rate(struct npcm8xx_gpio *bank, @@ -1892,6 +1973,56 @@ static int npcm8xx_set_slew_rate(struct npcm8xx_gpio *bank, return 0; } +static int npcm8xx_get_rg2_drive_strength(struct npcm8xx_pinctrl *npcm) +{ + u32 val; + int ret; + + ret = regmap_read(npcm->gcr_regmap, NPCM8XX_GCR_DSCNT, &val); + if (ret) + return ret; + + switch ((val & NPCM8XX_GCR_DSCNT_RG2DS_MASK) >> + NPCM8XX_GCR_DSCNT_RG2DS_SHIFT) { + case 0: + return 8; + case 1: + return 12; + case 2: + return 16; + case 3: + return 24; + default: + return -EINVAL; + } +} + +static int npcm8xx_set_rg2_drive_strength(struct npcm8xx_pinctrl *npcm, int nval) +{ + u32 val; + + switch (nval) { + case 8: + val = 0; + break; + case 12: + val = 1; + break; + case 16: + val = 2; + break; + case 24: + val = 3; + break; + default: + return -EOPNOTSUPP; + } + + return regmap_update_bits(npcm->gcr_regmap, NPCM8XX_GCR_DSCNT, + NPCM8XX_GCR_DSCNT_RG2DS_MASK, + val << NPCM8XX_GCR_DSCNT_RG2DS_SHIFT); +} + static int npcm8xx_get_drive_strength(struct pinctrl_dev *pctldev, unsigned int pin) { @@ -1900,10 +2031,13 @@ static int npcm8xx_get_drive_strength(struct pinctrl_dev *pctldev, &npcm->gpio_bank[pin / NPCM8XX_GPIO_PER_BANK]; int gpio = pin % bank->chip.gc.ngpio; unsigned long pinmask = BIT(gpio); - int flg, val; - u32 ds = 0; + int flg, ds; + u32 val; flg = pincfg[pin].flag; + if (flg & DSTR_RG2) + return npcm8xx_get_rg2_drive_strength(npcm); + if (!(flg & DRIVE_STRENGTH_MASK)) return -EINVAL; @@ -1922,6 +2056,9 @@ static int npcm8xx_set_drive_strength(struct npcm8xx_pinctrl *npcm, int gpio = BIT(pin % bank->chip.gc.ngpio); int v; + if (pincfg[pin].flag & DSTR_RG2) + return npcm8xx_set_rg2_drive_strength(npcm, nval); + v = pincfg[pin].flag & DRIVE_STRENGTH_MASK; if (DSLO(v) == nval) @@ -2073,7 +2210,8 @@ static const struct pinmux_ops npcm8xx_pinmux_ops = { static int debounce_timing_setting(struct npcm8xx_gpio *bank, u32 gpio, u32 nanosecs) { - void __iomem *DBNCS_offset = bank->base + NPCM8XX_GP_N_DBNCS0 + (gpio / 4); + void __iomem *DBNCS_offset = bank->base + NPCM8XX_GP_N_DBNCS0 + + (gpio / 16) * 4; int gpio_debounce = (gpio % 16) * 2, debounce_select, i; u32 dbncp_val, dbncp_val_mod; @@ -2350,6 +2488,9 @@ static int npcm8xx_gpio_fw(struct npcm8xx_pinctrl *pctrl) if (ret < 0) return dev_err_probe(dev, ret, "Failed to retrieve IRQ for bank %u\n", id); + iowrite32(0, pctrl->gpio_bank[id].base + NPCM8XX_GP_N_EVEN); + iowrite32(0xffffffff, pctrl->gpio_bank[id].base + NPCM8XX_GP_N_EVST); + pctrl->gpio_bank[id].irq = ret; pctrl->gpio_bank[id].irq_chip = npcmgpio_irqchip; pctrl->gpio_bank[id].irqbase = id * NPCM8XX_GPIO_PER_BANK; diff --git a/drivers/pinctrl/nxp/Kconfig b/drivers/pinctrl/nxp/Kconfig index abca7ef97003..fab725f250ab 100644 --- a/drivers/pinctrl/nxp/Kconfig +++ b/drivers/pinctrl/nxp/Kconfig @@ -5,6 +5,8 @@ config PINCTRL_S32CC select GENERIC_PINCTRL_GROUPS select GENERIC_PINMUX_FUNCTIONS select GENERIC_PINCONF + select GPIOLIB + select GPIO_REGMAP select REGMAP_MMIO config PINCTRL_S32G2 diff --git a/drivers/pinctrl/nxp/pinctrl-s32.h b/drivers/pinctrl/nxp/pinctrl-s32.h index 8715befd5f05..028578a090e4 100644 --- a/drivers/pinctrl/nxp/pinctrl-s32.h +++ b/drivers/pinctrl/nxp/pinctrl-s32.h @@ -2,7 +2,7 @@ * * S32 pinmux core definitions * - * Copyright 2016-2020, 2022 NXP + * Copyright 2016-2020, 2022, 2026 NXP * Copyright (C) 2022 SUSE LLC * Copyright 2015-2016 Freescale Semiconductor, Inc. * Copyright (C) 2012 Linaro Ltd. @@ -34,11 +34,42 @@ struct s32_pin_range { unsigned int end; }; +/** + * struct s32_gpio_range - contiguous GPIO pin range within a SIUL2 module + * @gpio_base: first GPIO line offset in the GPIO range + * @pin_base: first pinctrl pin number mapped by this GPIO range + * @gpio_num: number of consecutive GPIO pins in the range + * @sparse: true if the PGPD layout is non-linear (resolved via pad map only); + * pins not found in the pad map are invalid for this range + */ +struct s32_gpio_range { + unsigned int gpio_base; + unsigned int pin_base; + unsigned int gpio_num; + bool sparse; +}; + +/** + * struct s32_gpio_pad_map - mapping between GPIO ranges and PGPD pads + * @gpio_start: first GPIO line offset in the range + * @gpio_end: last GPIO line offset in the range + * @pad: PGPD pad number serving the range + */ +struct s32_gpio_pad_map { + unsigned int gpio_start; + unsigned int gpio_end; + unsigned int pad; +}; + struct s32_pinctrl_soc_data { const struct pinctrl_pin_desc *pins; unsigned int npins; const struct s32_pin_range *mem_pin_ranges; unsigned int mem_regions; + const struct s32_gpio_range *gpio_ranges; + unsigned int num_gpio_ranges; + const struct s32_gpio_pad_map *gpio_pad_maps; + unsigned int num_gpio_pad_maps; }; struct s32_pinctrl_soc_info { @@ -53,6 +84,8 @@ struct s32_pinctrl_soc_info { #define S32_PINCTRL_PIN(pin) PINCTRL_PIN(pin, #pin) #define S32_PIN_RANGE(_start, _end) { .start = _start, .end = _end } +#define S32_GPIO_RANGE(gpio, pin, num) \ + { .gpio_base = gpio, .pin_base = pin, .gpio_num = num } int s32_pinctrl_probe(struct platform_device *pdev, const struct s32_pinctrl_soc_data *soc_data); diff --git a/drivers/pinctrl/nxp/pinctrl-s32cc.c b/drivers/pinctrl/nxp/pinctrl-s32cc.c index 56be6e8d624e..0025add68495 100644 --- a/drivers/pinctrl/nxp/pinctrl-s32cc.c +++ b/drivers/pinctrl/nxp/pinctrl-s32cc.c @@ -2,7 +2,7 @@ /* * Core driver for the S32 CC (Common Chassis) pin controller * - * Copyright 2017-2022,2024-2025 NXP + * Copyright 2017-2022,2024-2026 NXP * Copyright (C) 2022 SUSE LLC * Copyright 2015-2016 Freescale Semiconductor, Inc. */ @@ -10,6 +10,7 @@ #include #include #include +#include #include #include #include @@ -39,6 +40,40 @@ #define S32_MSCR_ODE BIT(20) #define S32_MSCR_OBE BIT(21) +#define S32_GPIO_OP_SHIFT 16 +#define S32_GPIO_OP_MASK GENMASK(19, 16) + +#define S32_GPIO_OP_DIR 0 /* MSCR direction */ +#define S32_GPIO_OP_DAT BIT(S32_GPIO_OP_SHIFT) /* PGPDI read */ +#define S32_GPIO_OP_SET BIT(S32_GPIO_OP_SHIFT + 1) /* PGPDO write */ + +/* + * [15:12] = GPIO bank / gpio range index + * [11:0] = real register offset or pin id + */ +#define S32_GPIO_BANK_SHIFT 12 +#define S32_GPIO_BANK_MASK GENMASK(15, 12) +#define S32_GPIO_REG_MASK GENMASK(11, 0) + +#define S32_GPIO_ENCODE(bank, off) \ + ((((bank) << S32_GPIO_BANK_SHIFT) & S32_GPIO_BANK_MASK) | \ + ((off) & S32_GPIO_REG_MASK)) + +#define S32_GPIO_DECODE_BANK(reg) \ + (((reg) & S32_GPIO_BANK_MASK) >> S32_GPIO_BANK_SHIFT) + +#define S32_GPIO_DECODE_OFF(reg) \ + ((reg) & S32_GPIO_REG_MASK) + +/* + * PGPDOs are 16bit registers that come in big endian + * order if they are grouped in pairs of two. + * + * For example, the order is PGPDO1, PGPDO0, PGPDO3, PGPDO2... + */ +#define S32_PGPD(N) (((N) ^ 1) * 2) +#define S32_PGPD_SIZE 16 + enum s32_write_type { S32_PINCONF_UPDATE_ONLY, S32_PINCONF_OVERWRITE, @@ -60,6 +95,12 @@ static u32 get_pin_func(u32 pinmux) return pinmux & GENMASK(3, 0); } +/* + * struct s32_pinctrl_mem_region - memory region for a set of SIUL2 registers + * @map: regmap used for this range + * @pin_range: the pins controlled by these registers + * @name: name of the current range + */ struct s32_pinctrl_mem_region { struct regmap *map; const struct s32_pin_range *pin_range; @@ -67,7 +108,19 @@ struct s32_pinctrl_mem_region { }; /* - * Holds pin configuration for GPIO's. + * struct s32_gpio_regmaps - GPIO register maps for a SIUL2 instance + * @pgpdo: regmap for Parallel GPIO Pad Data Out registers + * @pgpdi: regmap for Parallel GPIO Pad Data In registers + * @range: GPIO range info + */ +struct s32_gpio_regmaps { + struct regmap *pgpdo; + struct regmap *pgpdi; + const struct s32_gpio_range *range; +}; + +/* + * struct gpio_pin_config - holds pin configuration for GPIO's * @pin_id: Pin ID for this GPIO * @config: Pin settings * @list: Linked list entry for each gpio pin @@ -79,26 +132,40 @@ struct gpio_pin_config { }; /* - * Pad config save/restore for power suspend/resume. + * struct s32_pinctrl_context - pad config save/restore for suspend/resume + * @pads: saved values for the pads */ struct s32_pinctrl_context { unsigned int *pads; }; /* + * struct s32_pinctrl - private driver data * @dev: a pointer back to containing device * @pctl: a pointer to the pinctrl device structure * @regions: reserved memory regions with start/end pin * @info: structure containing information about the pin - * @gpio_configs: Saved configurations for GPIO pins - * @gpiop_configs_lock: lock for the `gpio_configs` list - * @s32_pinctrl_context: Configuration saved over system sleep + * @gpio_regmaps: PGPDO/PGPDI regmaps for each SIUL2 module + * @num_gpio_regmaps: number of GPIO regmap entries + * @gpio_regmap: regmap bridging gpio-regmap to SIUL2 registers + * @gpio_rgm: gpio-regmap instance registered for this controller + * @ngpio: total number of GPIO line offsets + * @gpio_names: GPIO line names array passed to gpio-regmap + * @gpio_configs: saved configurations for GPIO pins + * @gpio_configs_lock: lock for the `gpio_configs` list + * @saved_context: configuration saved over system sleep */ struct s32_pinctrl { struct device *dev; struct pinctrl_dev *pctl; struct s32_pinctrl_mem_region *regions; struct s32_pinctrl_soc_info *info; + struct s32_gpio_regmaps *gpio_regmaps; + unsigned int num_gpio_regmaps; + struct regmap *gpio_regmap; + struct gpio_regmap *gpio_rgm; + unsigned int ngpio; + const char *const *gpio_names; struct list_head gpio_configs; spinlock_t gpio_configs_lock; #ifdef CONFIG_PM_SLEEP @@ -123,13 +190,13 @@ s32_get_region(struct pinctrl_dev *pctldev, unsigned int pin) return NULL; } -static inline int s32_check_pin(struct pinctrl_dev *pctldev, - unsigned int pin) +static int s32_check_pin(struct pinctrl_dev *pctldev, + unsigned int pin) { return s32_get_region(pctldev, pin) ? 0 : -EINVAL; } -static inline int s32_regmap_read(struct pinctrl_dev *pctldev, +static int s32_regmap_read(struct pinctrl_dev *pctldev, unsigned int pin, unsigned int *val) { struct s32_pinctrl_mem_region *region; @@ -145,7 +212,7 @@ static inline int s32_regmap_read(struct pinctrl_dev *pctldev, return regmap_read(region->map, offset, val); } -static inline int s32_regmap_write(struct pinctrl_dev *pctldev, +static int s32_regmap_write(struct pinctrl_dev *pctldev, unsigned int pin, unsigned int val) { @@ -163,7 +230,7 @@ static inline int s32_regmap_write(struct pinctrl_dev *pctldev, } -static inline int s32_regmap_update(struct pinctrl_dev *pctldev, unsigned int pin, +static int s32_regmap_update(struct pinctrl_dev *pctldev, unsigned int pin, unsigned int mask, unsigned int val) { struct s32_pinctrl_mem_region *region; @@ -348,6 +415,63 @@ static int s32_pmx_get_funcs_count(struct pinctrl_dev *pctldev) return info->nfunctions; } +static int s32_pmx_gpio_request_enable(struct pinctrl_dev *pctldev, + struct pinctrl_gpio_range *range, + unsigned int pin) +{ + struct s32_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); + struct gpio_pin_config *gpio_pin __free(kfree) = NULL; + unsigned int config; + int ret; + + ret = s32_regmap_read(pctldev, pin, &config); + if (ret) + return ret; + + gpio_pin = kmalloc_obj(*gpio_pin, GFP_KERNEL); + if (!gpio_pin) + return -ENOMEM; + + gpio_pin->pin_id = pin; + gpio_pin->config = config; + + /* GPIO pin means SSS = 0 */ + ret = s32_regmap_update(pctldev, pin, + S32_MSCR_SSS_MASK | S32_MSCR_IBE, + S32_MSCR_IBE); + if (ret) + return ret; + + scoped_guard(spinlock_irqsave, &ipctl->gpio_configs_lock) + list_add(&no_free_ptr(gpio_pin)->list, &ipctl->gpio_configs); + + return 0; +} + +static void s32_pmx_gpio_disable_free(struct pinctrl_dev *pctldev, + struct pinctrl_gpio_range *range, + unsigned int pin) +{ + struct s32_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); + struct gpio_pin_config *gpio_pin, *found = NULL; + unsigned long flags; + + spin_lock_irqsave(&ipctl->gpio_configs_lock, flags); + list_for_each_entry(gpio_pin, &ipctl->gpio_configs, list) { + if (gpio_pin->pin_id == pin) { + list_del(&gpio_pin->list); + found = gpio_pin; + break; + } + } + spin_unlock_irqrestore(&ipctl->gpio_configs_lock, flags); + + if (found) { + s32_regmap_write(pctldev, found->pin_id, found->config); + kfree(found); + } +} + static const char *s32_pmx_get_func_name(struct pinctrl_dev *pctldev, unsigned int selector) { @@ -371,67 +495,6 @@ static int s32_pmx_get_groups(struct pinctrl_dev *pctldev, return 0; } -static int s32_pmx_gpio_request_enable(struct pinctrl_dev *pctldev, - struct pinctrl_gpio_range *range, - unsigned int offset) -{ - struct s32_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); - struct gpio_pin_config *gpio_pin; - unsigned int config; - unsigned long flags; - int ret; - - ret = s32_regmap_read(pctldev, offset, &config); - if (ret) - return ret; - - /* Save current configuration */ - gpio_pin = kmalloc_obj(*gpio_pin); - if (!gpio_pin) - return -ENOMEM; - - gpio_pin->pin_id = offset; - gpio_pin->config = config; - INIT_LIST_HEAD(&gpio_pin->list); - - spin_lock_irqsave(&ipctl->gpio_configs_lock, flags); - list_add(&gpio_pin->list, &ipctl->gpio_configs); - spin_unlock_irqrestore(&ipctl->gpio_configs_lock, flags); - - /* GPIO pin means SSS = 0 */ - config &= ~S32_MSCR_SSS_MASK; - - return s32_regmap_write(pctldev, offset, config); -} - -static void s32_pmx_gpio_disable_free(struct pinctrl_dev *pctldev, - struct pinctrl_gpio_range *range, - unsigned int offset) -{ - struct s32_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); - struct gpio_pin_config *gpio_pin, *tmp; - unsigned long flags; - int ret; - - spin_lock_irqsave(&ipctl->gpio_configs_lock, flags); - - list_for_each_entry_safe(gpio_pin, tmp, &ipctl->gpio_configs, list) { - if (gpio_pin->pin_id == offset) { - ret = s32_regmap_write(pctldev, gpio_pin->pin_id, - gpio_pin->config); - if (ret != 0) - goto unlock; - - list_del(&gpio_pin->list); - kfree(gpio_pin); - break; - } - } - -unlock: - spin_unlock_irqrestore(&ipctl->gpio_configs_lock, flags); -} - static int s32_pmx_gpio_set_direction(struct pinctrl_dev *pctldev, struct pinctrl_gpio_range *range, unsigned int offset, @@ -476,8 +539,8 @@ static int s32_get_slew_regval(int arg) return -EINVAL; } -static inline void s32_pin_set_pull(enum pin_config_param param, - unsigned int *mask, unsigned int *config) +static void s32_pin_set_pull(enum pin_config_param param, + unsigned int *mask, unsigned int *config) { switch (param) { case PIN_CONFIG_BIAS_DISABLE: @@ -641,9 +704,9 @@ static void s32_pinconf_dbg_show(struct pinctrl_dev *pctldev, ret = s32_regmap_read(pctldev, pin_id, &config); if (ret) - return; - - seq_printf(s, "0x%x", config); + seq_printf(s, "error %d", ret); + else + seq_printf(s, "0x%x", config); } static void s32_pinconf_group_dbg_show(struct pinctrl_dev *pctldev, @@ -661,8 +724,11 @@ static void s32_pinconf_group_dbg_show(struct pinctrl_dev *pctldev, for (i = 0; i < grp->data.npins; i++) { name = pin_get_name(pctldev, grp->data.pins[i]); ret = s32_regmap_read(pctldev, grp->data.pins[i], &config); - if (ret) - return; + if (ret) { + seq_printf(s, "%s: error %d\n", name, ret); + continue; + } + seq_printf(s, "%s: 0x%x\n", name, config); } } @@ -675,6 +741,477 @@ static const struct pinconf_ops s32_pinconf_ops = { .pin_config_group_dbg_show = s32_pinconf_group_dbg_show, }; +static void s32_gpio_free_saved_configs(void *data) +{ + struct s32_pinctrl *ipctl = data; + struct gpio_pin_config *gpio_pin, *tmp; + unsigned long flags; + + spin_lock_irqsave(&ipctl->gpio_configs_lock, flags); + list_for_each_entry_safe(gpio_pin, tmp, &ipctl->gpio_configs, list) { + list_del(&gpio_pin->list); + kfree(gpio_pin); + } + spin_unlock_irqrestore(&ipctl->gpio_configs_lock, flags); +} + +static unsigned int s32_pin2pad(unsigned int pin) +{ + return pin / S32_PGPD_SIZE; +} + +static u16 s32_pin2mask(unsigned int pin) +{ + /* + * From Reference manual : + * PGPDOx[PPDOy] = GPDO(x × 16) + (15 - y)[PDO_(x × 16) + (15 - y)] + */ + return BIT(S32_PGPD_SIZE - 1 - pin % S32_PGPD_SIZE); +} + +static int s32_gpio_get_range(struct s32_pinctrl *ipctl, + unsigned int gpio, + unsigned int *pin, + unsigned int *bank) +{ + const struct s32_pinctrl_soc_data *soc_data = ipctl->info->soc_data; + const struct s32_gpio_range *range; + int i; + + for (i = 0; i < soc_data->num_gpio_ranges; i++) { + range = &soc_data->gpio_ranges[i]; + + if (gpio < range->gpio_base || + gpio >= range->gpio_base + range->gpio_num) + continue; + + if (pin) + *pin = range->pin_base + gpio - range->gpio_base; + + if (bank) + *bank = i; + + return 0; + } + + return -EINVAL; +} + +static int s32_gpio_pad_map_xlate(struct s32_pinctrl *ipctl, + unsigned int gpio, + unsigned int *reg_offset, + u16 *mask) +{ + const struct s32_pinctrl_soc_data *soc_data = ipctl->info->soc_data; + const struct s32_gpio_pad_map *map; + unsigned int bit; + int i; + + if (!soc_data->gpio_pad_maps || !soc_data->num_gpio_pad_maps) + return -EINVAL; + + for (i = 0; i < soc_data->num_gpio_pad_maps; i++) { + map = &soc_data->gpio_pad_maps[i]; + + if (gpio < map->gpio_start || gpio > map->gpio_end) + continue; + + bit = gpio - map->gpio_start; + *mask = BIT(S32_PGPD_SIZE - 1 - bit); + *reg_offset = S32_PGPD(map->pad); + + return 0; + } + + return -EINVAL; +} + +static bool s32_gpio_pin_is_sparse(struct s32_pinctrl *ipctl, unsigned int pin) +{ + const struct s32_pinctrl_soc_data *soc_data = ipctl->info->soc_data; + const struct s32_gpio_range *range; + int i; + + for (i = 0; i < soc_data->num_gpio_ranges; i++) { + range = &soc_data->gpio_ranges[i]; + if (pin >= range->pin_base && + pin < range->pin_base + range->gpio_num) + return range->sparse; + } + + return false; +} + +static int s32_gpio_xlate_pgpd(struct s32_pinctrl *ipctl, + unsigned int pin, + unsigned int *reg_offset, + u16 *mask) +{ + int ret; + + /* + * Try the pad map first. For sparse ranges (SIUL2_1), only pins + * listed in the pad map are valid, return the error directly without + * falling back to the linear layout. + * For linear ranges (SIUL2_0), fall back to the linear pad-to-PGPD + * formula if no pad map entry matches. + */ + ret = s32_gpio_pad_map_xlate(ipctl, pin, reg_offset, mask); + if (ret != -EINVAL) + return ret; + + if (s32_gpio_pin_is_sparse(ipctl, pin)) + return -EINVAL; + + /* Linear layout fallback for non-sparse ranges. */ + *mask = s32_pin2mask(pin); + *reg_offset = S32_PGPD(s32_pin2pad(pin)); + + return 0; +} + +static int s32_gpio_reg_mask_xlate(struct gpio_regmap *gpio, + unsigned int base, unsigned int offset, + unsigned int *reg, unsigned int *mask) +{ + struct s32_pinctrl *ipctl = gpio_regmap_get_drvdata(gpio); + unsigned int pgpd_reg, pin, bank; + u16 pgpd_mask; + int ret; + + ret = s32_gpio_get_range(ipctl, offset, &pin, &bank); + if (ret) + return ret; + + switch (base) { + case S32_GPIO_OP_DIR: + /* + * Direction is controlled through MSCR OBE. + * Encode the real pin id in the virtual register. + */ + *reg = S32_GPIO_OP_DIR | pin; + *mask = S32_MSCR_OBE; + return 0; + + case S32_GPIO_OP_DAT: + case S32_GPIO_OP_SET: + ret = s32_gpio_xlate_pgpd(ipctl, pin, &pgpd_reg, &pgpd_mask); + if (ret) + return ret; + /* + * Encode both the GPIO bank and the real PGPD register offset. + */ + *reg = base | S32_GPIO_ENCODE(bank, pgpd_reg); + *mask = pgpd_mask; + return 0; + default: + return -EINVAL; + } +} + +static int s32_gpio_reg_read(void *context, unsigned int reg, + unsigned int *val) +{ + struct s32_pinctrl *ipctl = context; + unsigned int op = reg & S32_GPIO_OP_MASK; + unsigned int vreg = reg & ~S32_GPIO_OP_MASK; + unsigned int bank; + unsigned int offset; + struct regmap *map; + + switch (op) { + case S32_GPIO_OP_DIR: + /* + * Lower bits contain the real MSCR pin id. + */ + offset = S32_GPIO_DECODE_OFF(vreg); + + return s32_regmap_read(ipctl->pctl, offset, val); + + case S32_GPIO_OP_DAT: + bank = S32_GPIO_DECODE_BANK(vreg); + offset = S32_GPIO_DECODE_OFF(vreg); + + if (bank >= ipctl->num_gpio_regmaps) + return -EINVAL; + + map = ipctl->gpio_regmaps[bank].pgpdi; + if (!map) + return -ENODEV; + + return regmap_read(map, offset, val); + + case S32_GPIO_OP_SET: + /* + * gpio-regmap uses update_bits() for set, so it needs to read + * the output register before writing the updated value. + */ + bank = S32_GPIO_DECODE_BANK(vreg); + offset = S32_GPIO_DECODE_OFF(vreg); + + if (bank >= ipctl->num_gpio_regmaps) + return -EINVAL; + + map = ipctl->gpio_regmaps[bank].pgpdo; + if (!map) + return -ENODEV; + + return regmap_read(map, offset, val); + + default: + return -EINVAL; + } +} + +static int s32_gpio_reg_write(void *context, unsigned int reg, + unsigned int val) +{ + struct s32_pinctrl *ipctl = context; + unsigned int op = reg & S32_GPIO_OP_MASK; + unsigned int vreg = reg & ~S32_GPIO_OP_MASK; + unsigned int bank, offset, config; + struct regmap *map; + + switch (op) { + case S32_GPIO_OP_DIR: + /* + * gpio-regmap sets S32_MSCR_OBE for output and clears it for + * input. Keep IBE enabled for GPIOs in both cases. + */ + offset = S32_GPIO_DECODE_OFF(vreg); + + config = S32_MSCR_IBE; + if (val & S32_MSCR_OBE) + config |= S32_MSCR_OBE; + + return s32_regmap_update(ipctl->pctl, offset, + S32_MSCR_OBE | S32_MSCR_IBE, + config); + + case S32_GPIO_OP_SET: + bank = S32_GPIO_DECODE_BANK(vreg); + offset = S32_GPIO_DECODE_OFF(vreg); + + if (bank >= ipctl->num_gpio_regmaps) + return -EINVAL; + + map = ipctl->gpio_regmaps[bank].pgpdo; + if (!map) + return -ENODEV; + + return regmap_write(map, offset, val); + + default: + return -EINVAL; + } +} + +static const struct regmap_bus s32_gpio_regmap_bus = { + .reg_read = s32_gpio_reg_read, + .reg_write = s32_gpio_reg_write, +}; + +static const struct regmap_config s32_gpio_regmap_config = { + .name = "s32-gpio", + .reg_bits = 32, + .val_bits = 32, + .reg_stride = 1, + .max_register = S32_GPIO_OP_SET | S32_GPIO_BANK_MASK | S32_GPIO_REG_MASK, + .cache_type = REGCACHE_NONE, + .fast_io = true, +}; + +static int s32_gpio_get_ngpio(const struct s32_pinctrl_soc_data *soc_data, + unsigned int *ngpio) +{ + const struct s32_gpio_range *range; + unsigned int end, max = 0; + int i; + + if (!soc_data->gpio_ranges || !soc_data->num_gpio_ranges) + return -EINVAL; + + for (i = 0; i < soc_data->num_gpio_ranges; i++) { + range = &soc_data->gpio_ranges[i]; + + if (!range->gpio_num) + return -EINVAL; + + end = range->gpio_base + range->gpio_num; + + /* + * gpio_ranges must be ordered by gpio_base and must not overlap. + * The GPIO line space size is derived from the highest range end. + */ + if (i > 0 && range->gpio_base < max) + return -EINVAL; + + if (end > max) + max = end; + } + + *ngpio = max; + + return 0; +} + +static int s32_init_gpio_regmap(struct platform_device *pdev, + struct s32_pinctrl *ipctl) +{ + ipctl->gpio_regmap = + devm_regmap_init(&pdev->dev, &s32_gpio_regmap_bus, + ipctl, &s32_gpio_regmap_config); + if (IS_ERR(ipctl->gpio_regmap)) + return dev_err_probe(&pdev->dev, + PTR_ERR(ipctl->gpio_regmap), + "Failed to init GPIO regmap\n"); + + return 0; +} + +static int s32_init_valid_mask(struct gpio_chip *chip, unsigned long *mask, + unsigned int ngpios) +{ + struct gpio_regmap *gpio = gpiochip_get_data(chip); + struct s32_pinctrl *ipctl = gpio_regmap_get_drvdata(gpio); + unsigned int gpio_num, pin, reg_offset; + u16 pgpd_mask; + int ret; + + bitmap_zero(mask, ngpios); + + for (gpio_num = 0; gpio_num < ngpios; gpio_num++) { + ret = s32_gpio_get_range(ipctl, gpio_num, &pin, NULL); + if (ret) + continue; + + ret = s32_gpio_xlate_pgpd(ipctl, pin, ®_offset, &pgpd_mask); + if (ret) + continue; + + bitmap_set(mask, gpio_num, 1); + } + + return 0; +} + +static int s32_gpio_populate_names(struct s32_pinctrl *ipctl) +{ + char **names; + unsigned int gpio; + unsigned int pin; + char port; + int ret; + + names = devm_kcalloc(ipctl->dev, ipctl->ngpio, sizeof(*names), + GFP_KERNEL); + if (!names) + return -ENOMEM; + + for (gpio = 0; gpio < ipctl->ngpio; gpio++) { + ret = s32_gpio_get_range(ipctl, gpio, &pin, NULL); + if (ret) + continue; + + port = 'A' + pin / 16; + + names[gpio] = devm_kasprintf(ipctl->dev, GFP_KERNEL, + "P%c_%02u", port, pin & 0xf); + if (!names[gpio]) + return -ENOMEM; + } + + ipctl->gpio_names = (const char *const *)names; + + return 0; +} + +static int s32_pinctrl_init_gpio_regmaps(struct platform_device *pdev, + struct s32_pinctrl *ipctl) +{ + const struct s32_pinctrl_soc_data *soc_data = ipctl->info->soc_data; + static const struct regmap_config pgpd_config = { + .reg_bits = 32, + .val_bits = 16, + .reg_stride = 2, + }; + struct regmap_config cfg; + struct resource *res; + void __iomem *base; + unsigned int pgpdo_idx, pgpdi_idx; + unsigned int i; + + if (!soc_data->gpio_ranges || !soc_data->num_gpio_ranges) + return 0; + + ipctl->num_gpio_regmaps = soc_data->num_gpio_ranges; + ipctl->gpio_regmaps = devm_kcalloc(&pdev->dev, ipctl->num_gpio_regmaps, + sizeof(*ipctl->gpio_regmaps), + GFP_KERNEL); + if (!ipctl->gpio_regmaps) + return -ENOMEM; + + for (i = 0; i < ipctl->num_gpio_regmaps; i++) { + ipctl->gpio_regmaps[i].range = &soc_data->gpio_ranges[i]; + + /* + * GPIO resources are placed after the pinctrl regions + */ + pgpdo_idx = soc_data->mem_regions + i * 2; + pgpdi_idx = soc_data->mem_regions + i * 2 + 1; + + /* PGPDO */ + res = platform_get_resource(pdev, IORESOURCE_MEM, pgpdo_idx); + if (!res) + return dev_err_probe(&pdev->dev, -ENOENT, + "Missing PGPDO resource %u\n", i); + + base = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(base)) + return PTR_ERR(base); + + cfg = pgpd_config; + cfg.name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "pgpdo%u", i); + if (!cfg.name) + return -ENOMEM; + + cfg.max_register = resource_size(res) - cfg.reg_stride; + + ipctl->gpio_regmaps[i].pgpdo = + devm_regmap_init_mmio(&pdev->dev, base, &cfg); + if (IS_ERR(ipctl->gpio_regmaps[i].pgpdo)) + return dev_err_probe(&pdev->dev, + PTR_ERR(ipctl->gpio_regmaps[i].pgpdo), + "Failed to init PGPDO regmap %u\n", i); + + /* PGPDI */ + res = platform_get_resource(pdev, IORESOURCE_MEM, pgpdi_idx); + if (!res) + return dev_err_probe(&pdev->dev, -ENOENT, + "Missing PGPDI resource %u\n", i); + + base = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(base)) + return PTR_ERR(base); + + cfg = pgpd_config; + cfg.name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "pgpdi%u", i); + if (!cfg.name) + return -ENOMEM; + + cfg.max_register = resource_size(res) - cfg.reg_stride; + + ipctl->gpio_regmaps[i].pgpdi = + devm_regmap_init_mmio(&pdev->dev, base, &cfg); + if (IS_ERR(ipctl->gpio_regmaps[i].pgpdi)) + return dev_err_probe(&pdev->dev, + PTR_ERR(ipctl->gpio_regmaps[i].pgpdi), + "Failed to init PGPDI regmap %u\n", i); + } + + return 0; +} + #ifdef CONFIG_PM_SLEEP static bool s32_pinctrl_should_save(struct s32_pinctrl *ipctl, unsigned int pin) @@ -701,8 +1238,7 @@ int s32_pinctrl_suspend(struct device *dev) const struct pinctrl_pin_desc *pin; const struct s32_pinctrl_soc_info *info = ipctl->info; struct s32_pinctrl_context *saved_context = &ipctl->saved_context; - int i; - int ret; + int i, ret; unsigned int config; for (i = 0; i < info->soc_data->npins; i++) { @@ -713,7 +1249,7 @@ int s32_pinctrl_suspend(struct device *dev) ret = s32_regmap_read(ipctl->pctl, pin->number, &config); if (ret) - return -EINVAL; + return ret; saved_context->pads[i] = config; } @@ -728,7 +1264,7 @@ int s32_pinctrl_resume(struct device *dev) const struct s32_pinctrl_soc_info *info = ipctl->info; const struct pinctrl_pin_desc *pin; struct s32_pinctrl_context *saved_context = &ipctl->saved_context; - int ret, i; + int i, ret; for (i = 0; i < info->soc_data->npins; i++) { pin = &info->soc_data->pins[i]; @@ -737,7 +1273,7 @@ int s32_pinctrl_resume(struct device *dev) continue; ret = s32_regmap_write(ipctl->pctl, pin->number, - saved_context->pads[i]); + saved_context->pads[i]); if (ret) return ret; } @@ -920,9 +1456,11 @@ int s32_pinctrl_probe(struct platform_device *pdev, #ifdef CONFIG_PM_SLEEP struct s32_pinctrl_context *saved_context; #endif + struct gpio_regmap_config gpio_cfg = {}; struct pinctrl_desc *s32_pinctrl_desc; struct s32_pinctrl_soc_info *info; struct s32_pinctrl *ipctl; + unsigned int ngpio; int ret; if (!soc_data || !soc_data->pins || !soc_data->npins) @@ -948,6 +1486,11 @@ int s32_pinctrl_probe(struct platform_device *pdev, INIT_LIST_HEAD(&ipctl->gpio_configs); spin_lock_init(&ipctl->gpio_configs_lock); + ret = devm_add_action_or_reset(&pdev->dev, + s32_gpio_free_saved_configs, ipctl); + if (ret) + return ret; + s32_pinctrl_desc = devm_kzalloc(&pdev->dev, sizeof(*s32_pinctrl_desc), GFP_KERNEL); if (!s32_pinctrl_desc) @@ -966,11 +1509,16 @@ int s32_pinctrl_probe(struct platform_device *pdev, return dev_err_probe(&pdev->dev, ret, "Fail to probe dt properties\n"); - ipctl->pctl = devm_pinctrl_register(&pdev->dev, s32_pinctrl_desc, - ipctl); - if (IS_ERR(ipctl->pctl)) - return dev_err_probe(&pdev->dev, PTR_ERR(ipctl->pctl), - "could not register s32 pinctrl driver\n"); + ret = s32_pinctrl_init_gpio_regmaps(pdev, ipctl); + if (ret) + return dev_err_probe(&pdev->dev, ret, + "Failed to init GPIO regmaps\n"); + + ret = devm_pinctrl_register_and_init(&pdev->dev, s32_pinctrl_desc, + ipctl, &ipctl->pctl); + if (ret) + return dev_err_probe(&pdev->dev, ret, + "Could not register s32 pinctrl driver\n"); #ifdef CONFIG_PM_SLEEP saved_context = &ipctl->saved_context; @@ -982,7 +1530,47 @@ int s32_pinctrl_probe(struct platform_device *pdev, return -ENOMEM; #endif - dev_info(&pdev->dev, "initialized s32 pinctrl driver\n"); + ret = pinctrl_enable(ipctl->pctl); + if (ret) + return dev_err_probe(&pdev->dev, ret, + "Failed to enable pinctrl\n"); + + /* Setup GPIO if GPIO ranges are defined */ + if (!soc_data->gpio_ranges || !soc_data->num_gpio_ranges) + return 0; + + ret = s32_gpio_get_ngpio(soc_data, &ngpio); + if (ret) + return dev_err_probe(&pdev->dev, ret, "Invalid GPIO ranges\n"); + + ipctl->ngpio = ngpio; + + ret = s32_gpio_populate_names(ipctl); + if (ret) + return ret; + + ret = s32_init_gpio_regmap(pdev, ipctl); + if (ret) + return ret; + + gpio_cfg.parent = &pdev->dev; + gpio_cfg.fwnode = dev_fwnode(&pdev->dev); + gpio_cfg.label = dev_name(&pdev->dev); + gpio_cfg.regmap = ipctl->gpio_regmap; + gpio_cfg.ngpio = ngpio; + gpio_cfg.names = ipctl->gpio_names; + gpio_cfg.reg_dir_out_base = GPIO_REGMAP_ADDR(S32_GPIO_OP_DIR); + gpio_cfg.reg_dat_base = GPIO_REGMAP_ADDR(S32_GPIO_OP_DAT); + gpio_cfg.reg_set_base = GPIO_REGMAP_ADDR(S32_GPIO_OP_SET); + gpio_cfg.reg_mask_xlate = s32_gpio_reg_mask_xlate; + gpio_cfg.init_valid_mask = s32_init_valid_mask; + gpio_cfg.drvdata = ipctl; + + ipctl->gpio_rgm = devm_gpio_regmap_register(&pdev->dev, &gpio_cfg); + if (IS_ERR(ipctl->gpio_rgm)) + return dev_err_probe(&pdev->dev, + PTR_ERR(ipctl->gpio_rgm), + "Unable to add gpio_regmap chip\n"); return 0; } diff --git a/drivers/pinctrl/nxp/pinctrl-s32g2.c b/drivers/pinctrl/nxp/pinctrl-s32g2.c index c49d28793b69..f9546c67a269 100644 --- a/drivers/pinctrl/nxp/pinctrl-s32g2.c +++ b/drivers/pinctrl/nxp/pinctrl-s32g2.c @@ -3,7 +3,7 @@ * NXP S32G pinctrl driver * * Copyright 2015-2016 Freescale Semiconductor, Inc. - * Copyright 2017-2018, 2020-2022 NXP + * Copyright 2017-2018, 2020-2022, 2025-2026 NXP * Copyright (C) 2022 SUSE LLC */ @@ -773,17 +773,48 @@ static const struct s32_pin_range s32_pin_ranges_siul2[] = { S32_PIN_RANGE(942, 1007), }; -static const struct s32_pinctrl_soc_data s32_pinctrl_data = { +static const struct s32_gpio_range s32_gpio_ranges_siul2[] = { + S32_GPIO_RANGE(0, 0, 102), + /* SIUL2_1: sparse layout, PGPD mapping required for all pins */ + { .gpio_base = 112, .pin_base = 112, .gpio_num = 79, .sparse = true }, +}; + +/* + * SIUL2_1 GPIO ranges mapped to sparse PGPD pads. + * + * SIUL2_1 does not expose GPIO data registers as a linear pad + * sequence. Each entry describes a contiguous GPIO offset range + * and the PGPD pad servicing that range. + */ +static const struct s32_gpio_pad_map s32g_gpio_pad_maps[] = { + { 112, 122, 7 }, /* PH_00 .. PH_10 -> PGPD7 */ + { 144, 159, 9 }, /* PJ_00 .. PJ_15 -> PGPD9 */ + { 160, 175, 10 }, /* PK_00 .. PK_15 -> PGPD10 */ + { 176, 190, 11 }, /* PL_00 .. PL_14 -> PGPD11 */ +}; + +/* Legacy data for old DT bindings without GPIO support */ +static const struct s32_pinctrl_soc_data legacy_s32g_pinctrl_data = { .pins = s32_pinctrl_pads_siul2, .npins = ARRAY_SIZE(s32_pinctrl_pads_siul2), .mem_pin_ranges = s32_pin_ranges_siul2, .mem_regions = ARRAY_SIZE(s32_pin_ranges_siul2), }; +static const struct s32_pinctrl_soc_data s32g_pinctrl_data = { + .pins = s32_pinctrl_pads_siul2, + .npins = ARRAY_SIZE(s32_pinctrl_pads_siul2), + .mem_pin_ranges = s32_pin_ranges_siul2, + .mem_regions = ARRAY_SIZE(s32_pin_ranges_siul2), + .gpio_ranges = s32_gpio_ranges_siul2, + .num_gpio_ranges = ARRAY_SIZE(s32_gpio_ranges_siul2), + .gpio_pad_maps = s32g_gpio_pad_maps, + .num_gpio_pad_maps = ARRAY_SIZE(s32g_gpio_pad_maps), +}; + static const struct of_device_id s32_pinctrl_of_match[] = { { .compatible = "nxp,s32g2-siul2-pinctrl", - .data = &s32_pinctrl_data, }, { /* sentinel */ } }; @@ -792,8 +823,16 @@ MODULE_DEVICE_TABLE(of, s32_pinctrl_of_match); static int s32g_pinctrl_probe(struct platform_device *pdev) { const struct s32_pinctrl_soc_data *soc_data; + struct device_node *np = pdev->dev.of_node; - soc_data = of_device_get_match_data(&pdev->dev); + /* + * Legacy DTs only describe the pinctrl resources. + * New DT changes extend the same node with GPIO resources. + */ + if (of_property_present(np, "gpio-controller")) + soc_data = &s32g_pinctrl_data; + else + soc_data = &legacy_s32g_pinctrl_data; return s32_pinctrl_probe(pdev, soc_data); } diff --git a/drivers/pinctrl/pinctrl-aw9523.c b/drivers/pinctrl/pinctrl-aw9523.c index bc94003512cf..a13b1cdb78ea 100644 --- a/drivers/pinctrl/pinctrl-aw9523.c +++ b/drivers/pinctrl/pinctrl-aw9523.c @@ -817,7 +817,7 @@ static int aw9523_init_irq(struct aw9523 *awi, int irq) ret = devm_request_threaded_irq(dev, irq, NULL, aw9523_irq_thread_func, IRQF_ONESHOT, dev_name(dev), awi); if (ret) - return dev_err_probe(dev, ret, "Failed to request irq %d\n", irq); + return ret; girq = &awi->gpio.irq; gpio_irq_chip_set_chip(girq, &aw9523_irq_chip); diff --git a/drivers/pinctrl/pinctrl-generic-mux.c b/drivers/pinctrl/pinctrl-generic-mux.c index da5a5ec01583..202b72351efb 100644 --- a/drivers/pinctrl/pinctrl-generic-mux.c +++ b/drivers/pinctrl/pinctrl-generic-mux.c @@ -93,7 +93,7 @@ static int mux_pinmux_set_mux(struct pinctrl_dev *pctldev, function = pinmux_generic_get_function(pctldev, func_selector); func = function->data; - ret = mux_state_select(func->mux_state); + ret = mux_state_try_select(func->mux_state); if (ret) return ret; diff --git a/drivers/pinctrl/pinctrl-mcp23s08.c b/drivers/pinctrl/pinctrl-mcp23s08.c index a4f0ba728c6e..cc668f84bf8b 100644 --- a/drivers/pinctrl/pinctrl-mcp23s08.c +++ b/drivers/pinctrl/pinctrl-mcp23s08.c @@ -559,11 +559,8 @@ static int mcp23s08_irq_setup(struct mcp23s08 *mcp) err = devm_request_threaded_irq(chip->parent, mcp->irq, NULL, mcp23s08_irq, irqflags, dev_name(chip->parent), mcp); - if (err != 0) { - dev_err(chip->parent, "unable to request IRQ#%d: %d\n", - mcp->irq, err); + if (err) return err; - } return 0; } diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c index 7e0fcd45fd26..e90e13c5d7f2 100644 --- a/drivers/pinctrl/pinctrl-rockchip.c +++ b/drivers/pinctrl/pinctrl-rockchip.c @@ -483,7 +483,7 @@ static struct rockchip_mux_recalced_data rv1103b_mux_recalced_data[] = { }, }; -static struct rockchip_mux_recalced_data rv1108_mux_recalced_data[] = { +static const struct rockchip_mux_recalced_data rv1108_mux_recalced_data[] = { { .num = 1, .pin = 0, @@ -547,7 +547,7 @@ static struct rockchip_mux_recalced_data rv1108_mux_recalced_data[] = { }, }; -static struct rockchip_mux_recalced_data rv1126_mux_recalced_data[] = { +static const struct rockchip_mux_recalced_data rv1126_mux_recalced_data[] = { { .num = 0, .pin = 20, @@ -578,7 +578,7 @@ static struct rockchip_mux_recalced_data rv1126_mux_recalced_data[] = { }, }; -static struct rockchip_mux_recalced_data rk3128_mux_recalced_data[] = { +static const struct rockchip_mux_recalced_data rk3128_mux_recalced_data[] = { { .num = 2, .pin = 20, @@ -612,7 +612,7 @@ static struct rockchip_mux_recalced_data rk3128_mux_recalced_data[] = { }, }; -static struct rockchip_mux_recalced_data rk3308_mux_recalced_data[] = { +static const struct rockchip_mux_recalced_data rk3308_mux_recalced_data[] = { { /* gpio1b6_sel */ .num = 1, @@ -721,7 +721,116 @@ static struct rockchip_mux_recalced_data rk3308_mux_recalced_data[] = { }, }; -static struct rockchip_mux_recalced_data rk3328_mux_recalced_data[] = { +static const struct rockchip_mux_recalced_data rk3308b_mux_recalced_data[] = { + { + /* gpio1b6_sel */ + .num = 1, + .pin = 14, + .reg = 0x28, + .bit = 12, + .mask = 0xf + }, { + /* gpio1b7_sel */ + .num = 1, + .pin = 15, + .reg = 0x2c, + .bit = 0, + .mask = 0x3 + }, { + /* gpio1c2_sel */ + .num = 1, + .pin = 18, + .reg = 0x30, + .bit = 4, + .mask = 0xf + }, { + /* gpio1c3_sel */ + .num = 1, + .pin = 19, + .reg = 0x30, + .bit = 8, + .mask = 0xf + }, { + /* gpio1c4_sel */ + .num = 1, + .pin = 20, + .reg = 0x30, + .bit = 12, + .mask = 0xf + }, { + /* gpio1c5_sel */ + .num = 1, + .pin = 21, + .reg = 0x34, + .bit = 0, + .mask = 0xf + }, { + /* gpio1c6_sel */ + .num = 1, + .pin = 22, + .reg = 0x34, + .bit = 4, + .mask = 0xf + }, { + /* gpio1c7_sel */ + .num = 1, + .pin = 23, + .reg = 0x34, + .bit = 8, + .mask = 0xf + }, { + /* gpio2a2_sel_plus */ + .num = 2, + .pin = 2, + .reg = 0x608, + .bit = 0, + .mask = 0x7 + }, { + /* gpio2a3_sel_plus */ + .num = 2, + .pin = 3, + .reg = 0x608, + .bit = 4, + .mask = 0x7 + }, { + /* gpio2c0_sel_plus */ + .num = 2, + .pin = 16, + .reg = 0x610, + .bit = 8, + .mask = 0x7 + }, { + /* gpio3b2_sel_plus */ + .num = 3, + .pin = 10, + .reg = 0x610, + .bit = 0, + .mask = 0x7 + }, { + /* gpio3b3_sel_plus */ + .num = 3, + .pin = 11, + .reg = 0x610, + .bit = 4, + .mask = 0x7 + }, { + /* gpio3b4_sel */ + .num = 3, + .pin = 12, + .reg = 0x68, + .bit = 8, + .mask = 0xf + }, { + /* gpio3b5_sel */ + .num = 3, + .pin = 13, + .reg = 0x68, + .bit = 12, + .mask = 0xf + }, +}; + +static const struct rockchip_mux_recalced_data rk3328_mux_recalced_data[] = { { /* gpio2_b7_sel */ .num = 2, @@ -793,7 +902,7 @@ static void rockchip_get_recalced_mux(struct rockchip_pin_bank *bank, int pin, { struct rockchip_pinctrl *info = bank->drvdata; struct rockchip_pin_ctrl *ctrl = info->ctrl; - struct rockchip_mux_recalced_data *data; + const struct rockchip_mux_recalced_data *data; int i; for (i = 0; i < ctrl->niomux_recalced; i++) { @@ -811,7 +920,7 @@ static void rockchip_get_recalced_mux(struct rockchip_pin_bank *bank, int pin, *bit = data->bit; } -static struct rockchip_mux_route_data px30_mux_route_data[] = { +static const struct rockchip_mux_route_data px30_mux_route_data[] = { RK_MUXROUTE_SAME(2, RK_PB4, 1, 0x184, BIT(16 + 7)), /* cif-d0m0 */ RK_MUXROUTE_SAME(3, RK_PA1, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-d0m1 */ RK_MUXROUTE_SAME(2, RK_PB6, 1, 0x184, BIT(16 + 7)), /* cif-d1m0 */ @@ -862,7 +971,7 @@ static struct rockchip_mux_route_data px30_mux_route_data[] = { RK_MUXROUTE_SAME(1, RK_PB5, 2, 0x184, BIT(16 + 9) | BIT(9)), /* uart3-rtsm1 */ }; -static struct rockchip_mux_route_data rv1126_mux_route_data[] = { +static const struct rockchip_mux_route_data rv1126_mux_route_data[] = { RK_MUXROUTE_GRF(3, RK_PD2, 1, 0x10260, WRITE_MASK_VAL(0, 0, 0)), /* I2S0_MCLK_M0 */ RK_MUXROUTE_GRF(3, RK_PB0, 3, 0x10260, WRITE_MASK_VAL(0, 0, 1)), /* I2S0_MCLK_M1 */ @@ -959,7 +1068,7 @@ static struct rockchip_mux_route_data rv1126_mux_route_data[] = { RK_MUXROUTE_PMU(1, RK_PD0, 5, 0x0118, WRITE_MASK_VAL(2, 2, 1)), /* UART1_TX_M1 */ }; -static struct rockchip_mux_route_data rk3128_mux_route_data[] = { +static const struct rockchip_mux_route_data rk3128_mux_route_data[] = { RK_MUXROUTE_SAME(1, RK_PB2, 1, 0x144, BIT(16 + 3) | BIT(16 + 4)), /* spi-0 */ RK_MUXROUTE_SAME(1, RK_PD3, 3, 0x144, BIT(16 + 3) | BIT(16 + 4) | BIT(3)), /* spi-1 */ RK_MUXROUTE_SAME(0, RK_PB5, 2, 0x144, BIT(16 + 3) | BIT(16 + 4) | BIT(4)), /* spi-2 */ @@ -969,12 +1078,12 @@ static struct rockchip_mux_route_data rk3128_mux_route_data[] = { RK_MUXROUTE_SAME(2, RK_PA4, 2, 0x144, BIT(16 + 6) | BIT(6)), /* emmc-1 */ }; -static struct rockchip_mux_route_data rk3188_mux_route_data[] = { +static const struct rockchip_mux_route_data rk3188_mux_route_data[] = { RK_MUXROUTE_SAME(0, RK_PD0, 1, 0xa0, BIT(16 + 11)), /* non-iomuxed emmc/flash pins on flash-dqs */ RK_MUXROUTE_SAME(0, RK_PD0, 2, 0xa0, BIT(16 + 11) | BIT(11)), /* non-iomuxed emmc/flash pins on emmc-clk */ }; -static struct rockchip_mux_route_data rk3228_mux_route_data[] = { +static const struct rockchip_mux_route_data rk3228_mux_route_data[] = { RK_MUXROUTE_SAME(0, RK_PD2, 1, 0x50, BIT(16)), /* pwm0-0 */ RK_MUXROUTE_SAME(3, RK_PC5, 1, 0x50, BIT(16) | BIT(0)), /* pwm0-1 */ RK_MUXROUTE_SAME(0, RK_PD3, 1, 0x50, BIT(16 + 1)), /* pwm1-0 */ @@ -995,12 +1104,12 @@ static struct rockchip_mux_route_data rk3228_mux_route_data[] = { RK_MUXROUTE_SAME(3, RK_PB5, 1, 0x50, BIT(16 + 11) | BIT(11)), /* uart1-1_rx */ }; -static struct rockchip_mux_route_data rk3288_mux_route_data[] = { +static const struct rockchip_mux_route_data rk3288_mux_route_data[] = { RK_MUXROUTE_SAME(7, RK_PC0, 2, 0x264, BIT(16 + 12) | BIT(12)), /* edphdmi_cecinoutt1 */ RK_MUXROUTE_SAME(7, RK_PC7, 4, 0x264, BIT(16 + 12)), /* edphdmi_cecinout */ }; -static struct rockchip_mux_route_data rk3308_mux_route_data[] = { +static const struct rockchip_mux_route_data rk3308_mux_route_data[] = { RK_MUXROUTE_SAME(0, RK_PC3, 1, 0x314, BIT(16 + 0) | BIT(0)), /* rtc_clk */ RK_MUXROUTE_SAME(1, RK_PC6, 2, 0x314, BIT(16 + 2) | BIT(16 + 3)), /* uart2_rxm0 */ RK_MUXROUTE_SAME(4, RK_PD2, 2, 0x314, BIT(16 + 2) | BIT(16 + 3) | BIT(2)), /* uart2_rxm1 */ @@ -1016,7 +1125,36 @@ static struct rockchip_mux_route_data rk3308_mux_route_data[] = { RK_MUXROUTE_SAME(2, RK_PA4, 3, 0x600, BIT(16 + 2) | BIT(2)), /* pdm-clkm-m2 */ }; -static struct rockchip_mux_route_data rk3328_mux_route_data[] = { +static const struct rockchip_mux_route_data rk3308b_mux_route_data[] = { + RK_MUXROUTE_SAME(0, RK_PC3, 1, 0x314, BIT(16 + 0) | BIT(0)), /* rtc_clk */ + RK_MUXROUTE_SAME(1, RK_PC6, 2, 0x314, BIT(16 + 2) | BIT(16 + 3)), /* uart2_rxm0 */ + RK_MUXROUTE_SAME(4, RK_PD2, 2, 0x314, BIT(16 + 2) | BIT(16 + 3) | BIT(2)), /* uart2_rxm1 */ + RK_MUXROUTE_SAME(0, RK_PB7, 2, 0x608, BIT(16 + 8) | BIT(16 + 9)), /* i2c3_sdam0 */ + RK_MUXROUTE_SAME(3, RK_PB4, 2, 0x608, BIT(16 + 8) | BIT(16 + 9) | BIT(8)), /* i2c3_sdam1 */ + RK_MUXROUTE_SAME(2, RK_PA0, 3, 0x608, BIT(16 + 8) | BIT(16 + 9) | BIT(9)), /* i2c3_sdam2 */ + RK_MUXROUTE_SAME(1, RK_PA3, 2, 0x308, BIT(16 + 3)), /* i2s-8ch-1-sclktxm0 */ + RK_MUXROUTE_SAME(1, RK_PA4, 2, 0x308, BIT(16 + 3)), /* i2s-8ch-1-sclkrxm0 */ + RK_MUXROUTE_SAME(1, RK_PB5, 2, 0x308, BIT(16 + 3) | BIT(3)), /* i2s-8ch-1-sclktxm1 */ + RK_MUXROUTE_SAME(1, RK_PB6, 2, 0x308, BIT(16 + 3) | BIT(3)), /* i2s-8ch-1-sclkrxm1 */ + RK_MUXROUTE_SAME(1, RK_PA4, 3, 0x308, BIT(16 + 12) | BIT(16 + 13)), /* pdm-clkm0 */ + RK_MUXROUTE_SAME(1, RK_PB6, 4, 0x308, BIT(16 + 12) | BIT(16 + 13) | BIT(12)), /* pdm-clkm1 */ + RK_MUXROUTE_SAME(2, RK_PA6, 2, 0x308, BIT(16 + 12) | BIT(16 + 13) | BIT(13)), /* pdm-clkm2 */ + RK_MUXROUTE_SAME(2, RK_PA4, 3, 0x600, BIT(16 + 2) | BIT(2)), /* pdm-clkm-m2 */ + RK_MUXROUTE_SAME(3, RK_PB2, 3, 0x314, BIT(16 + 9)), /* spi1_miso */ + RK_MUXROUTE_SAME(2, RK_PA4, 2, 0x314, BIT(16 + 9) | BIT(9)), /* spi1_miso_m1 */ + RK_MUXROUTE_SAME(0, RK_PB3, 3, 0x314, BIT(16 + 10) | BIT(16 + 11)), /* owire_m0 */ + RK_MUXROUTE_SAME(1, RK_PC6, 7, 0x314, BIT(16 + 10) | BIT(16 + 11) | BIT(10)), /* owire_m1 */ + RK_MUXROUTE_SAME(2, RK_PA2, 5, 0x314, BIT(16 + 10) | BIT(16 + 11) | BIT(11)), /* owire_m2 */ + RK_MUXROUTE_SAME(0, RK_PB3, 2, 0x314, BIT(16 + 12) | BIT(16 + 13)), /* can_rxd_m0 */ + RK_MUXROUTE_SAME(1, RK_PC6, 5, 0x314, BIT(16 + 12) | BIT(16 + 13) | BIT(12)), /* can_rxd_m1 */ + RK_MUXROUTE_SAME(2, RK_PA2, 4, 0x314, BIT(16 + 12) | BIT(16 + 13) | BIT(13)), /* can_rxd_m2 */ + RK_MUXROUTE_SAME(1, RK_PC4, 3, 0x314, BIT(16 + 14)), /* mac_rxd0_m0 */ + RK_MUXROUTE_SAME(4, RK_PA2, 2, 0x314, BIT(16 + 14) | BIT(14)), /* mac_rxd0_m1 */ + RK_MUXROUTE_SAME(3, RK_PB4, 4, 0x314, BIT(16 + 15)), /* uart3_rx */ + RK_MUXROUTE_SAME(0, RK_PC1, 3, 0x314, BIT(16 + 15) | BIT(15)), /* uart3_rx_m1 */ +}; + +static const struct rockchip_mux_route_data rk3328_mux_route_data[] = { RK_MUXROUTE_SAME(1, RK_PA1, 2, 0x50, BIT(16) | BIT(16 + 1)), /* uart2dbg_rxm0 */ RK_MUXROUTE_SAME(2, RK_PA1, 1, 0x50, BIT(16) | BIT(16 + 1) | BIT(0)), /* uart2dbg_rxm1 */ RK_MUXROUTE_SAME(1, RK_PB3, 2, 0x50, BIT(16 + 2) | BIT(2)), /* gmac-m1_rxd0 */ @@ -1031,7 +1169,7 @@ static struct rockchip_mux_route_data rk3328_mux_route_data[] = { RK_MUXROUTE_SAME(2, RK_PC0, 4, 0x50, BIT(16 + 9) | BIT(9)), /* cif_data5m1 */ }; -static struct rockchip_mux_route_data rk3399_mux_route_data[] = { +static const struct rockchip_mux_route_data rk3399_mux_route_data[] = { RK_MUXROUTE_SAME(4, RK_PB0, 2, 0xe21c, BIT(16 + 10) | BIT(16 + 11)), /* uart2dbga_rx */ RK_MUXROUTE_SAME(4, RK_PC0, 2, 0xe21c, BIT(16 + 10) | BIT(16 + 11) | BIT(10)), /* uart2dbgb_rx */ RK_MUXROUTE_SAME(4, RK_PC3, 1, 0xe21c, BIT(16 + 10) | BIT(16 + 11) | BIT(11)), /* uart2dbgc_rx */ @@ -1039,7 +1177,7 @@ static struct rockchip_mux_route_data rk3399_mux_route_data[] = { RK_MUXROUTE_SAME(4, RK_PD0, 1, 0xe21c, BIT(16 + 14) | BIT(14)), /* pcie_clkreqnb */ }; -static struct rockchip_mux_route_data rk3568_mux_route_data[] = { +static const struct rockchip_mux_route_data rk3568_mux_route_data[] = { RK_MUXROUTE_PMU(0, RK_PB7, 1, 0x0110, WRITE_MASK_VAL(1, 0, 0)), /* PWM0 IO mux M0 */ RK_MUXROUTE_PMU(0, RK_PC7, 2, 0x0110, WRITE_MASK_VAL(1, 0, 1)), /* PWM0 IO mux M1 */ RK_MUXROUTE_PMU(0, RK_PC0, 1, 0x0110, WRITE_MASK_VAL(3, 2, 0)), /* PWM1 IO mux M0 */ @@ -1140,7 +1278,7 @@ static bool rockchip_get_mux_route(struct rockchip_pin_bank *bank, int pin, { struct rockchip_pinctrl *info = bank->drvdata; struct rockchip_pin_ctrl *ctrl = info->ctrl; - struct rockchip_mux_route_data *data; + const struct rockchip_mux_route_data *data; int i; for (i = 0; i < ctrl->niomux_routes; i++) { @@ -3486,6 +3624,7 @@ static int rockchip_get_pull(struct rockchip_pin_bank *bank, int pin_num) case RK3188: case RK3288: case RK3308: + case RK3308B: case RK3328: case RK3368: case RK3399: @@ -3552,6 +3691,7 @@ static int rockchip_set_pull(struct rockchip_pin_bank *bank, case RK3188: case RK3288: case RK3308: + case RK3308B: case RK3328: case RK3368: case RK3399: @@ -3848,6 +3988,7 @@ static bool rockchip_pinconf_pull_valid(struct rockchip_pin_ctrl *ctrl, case RK3188: case RK3288: case RK3308: + case RK3308B: case RK3328: case RK3368: case RK3399: @@ -4370,7 +4511,18 @@ static struct rockchip_pin_ctrl *rockchip_pinctrl_get_soc_data( bank_pins += 8; } + } + return ctrl; +} + +static void iomux_recalced_routes_init(struct rockchip_pinctrl *info) +{ + struct rockchip_pin_ctrl *ctrl = info->ctrl; + struct rockchip_pin_bank *bank = ctrl->pin_banks; + int i, j; + + for (i = 0; i < ctrl->nr_banks; ++i, ++bank) { /* calculate the per-bank recalced_mask */ for (j = 0; j < ctrl->niomux_recalced; j++) { int pin = 0; @@ -4391,8 +4543,6 @@ static struct rockchip_pin_ctrl *rockchip_pinctrl_get_soc_data( } } } - - return ctrl; } #define RK3288_GRF_GPIO6C_IOMUX 0x64 @@ -4443,6 +4593,76 @@ static int __maybe_unused rockchip_pinctrl_resume(struct device *dev) static SIMPLE_DEV_PM_OPS(rockchip_pinctrl_dev_pm_ops, rockchip_pinctrl_suspend, rockchip_pinctrl_resume); +#define RK3308B_GRF_SOC_CON13 0x608 +#define RK3308B_GRF_SOC_CON15 0x610 + +/* RK3308B_GRF_SOC_CON13 */ +#define RK3308B_GRF_I2C3_IOFUNC_SRC_CTRL (BIT(16 + 10) | BIT(10)) +#define RK3308B_GRF_GPIO2A3_SEL_SRC_CTRL (BIT(16 + 7) | BIT(7)) +#define RK3308B_GRF_GPIO2A2_SEL_SRC_CTRL (BIT(16 + 3) | BIT(3)) + +/* RK3308B_GRF_SOC_CON15 */ +#define RK3308B_GRF_GPIO2C0_SEL_SRC_CTRL (BIT(16 + 11) | BIT(11)) +#define RK3308B_GRF_GPIO3B3_SEL_SRC_CTRL (BIT(16 + 7) | BIT(7)) +#define RK3308B_GRF_GPIO3B2_SEL_SRC_CTRL (BIT(16 + 3) | BIT(3)) + +/* + * RK3308B has 3-bit gpio##_sel_plus iomuxes over some 2-bit old ones. + * Enable them by setting the gpio##_sel_src_ctrl registers. + */ +static int rk3308b_soc_sel_src_init(struct rockchip_pinctrl *info) +{ + int ret; + + ret = regmap_write(info->regmap_base, RK3308B_GRF_SOC_CON13, + RK3308B_GRF_I2C3_IOFUNC_SRC_CTRL | + RK3308B_GRF_GPIO2A3_SEL_SRC_CTRL | + RK3308B_GRF_GPIO2A2_SEL_SRC_CTRL); + if (ret) + return ret; + + return regmap_write(info->regmap_base, RK3308B_GRF_SOC_CON15, + RK3308B_GRF_GPIO2C0_SEL_SRC_CTRL | + RK3308B_GRF_GPIO3B3_SEL_SRC_CTRL | + RK3308B_GRF_GPIO3B2_SEL_SRC_CTRL); +} + +#define RK3308_GRF_CHIP_ID 0x800 + +static int rk3308_soc_data_init(struct rockchip_pinctrl *info) +{ + struct rockchip_pin_ctrl *ctrl = info->ctrl; + unsigned int chip_id; + int ret; + + ret = regmap_read(info->regmap_base, RK3308_GRF_CHIP_ID, &chip_id); + if (ret) + return ret; + + switch (chip_id) { + case 0xcea: + /* Original RK3308, no changes needed */ + break; + case 0x3308: + case 0x3308c: + ctrl->type = RK3308B; + ctrl->iomux_recalced = rk3308b_mux_recalced_data; + ctrl->niomux_recalced = ARRAY_SIZE(rk3308b_mux_recalced_data); + ctrl->iomux_routes = rk3308b_mux_route_data; + ctrl->niomux_routes = ARRAY_SIZE(rk3308b_mux_route_data); + + ret = rk3308b_soc_sel_src_init(info); + if (ret) + return ret; + break; + default: + return dev_err_probe(info->dev, -EINVAL, + "Unknown RK3308 chip_id: 0x%x\n", chip_id); + } + + return 0; +} + static int rockchip_pinctrl_probe(struct platform_device *pdev) { struct rockchip_pinctrl *info; @@ -4505,6 +4725,14 @@ static int rockchip_pinctrl_probe(struct platform_device *pdev) /* try to find the optional reference to the ioc1 syscon */ info->regmap_ioc1 = syscon_regmap_lookup_by_phandle_optional(np, "rockchip,ioc1"); + if (ctrl->type == RK3308) { + ret = rk3308_soc_data_init(info); + if (ret) + return ret; + } + + iomux_recalced_routes_init(info); + ret = rockchip_pinctrl_register(pdev, info); if (ret) return ret; diff --git a/drivers/pinctrl/pinctrl-rockchip.h b/drivers/pinctrl/pinctrl-rockchip.h index bb0e803e3b8a..914582c87dd8 100644 --- a/drivers/pinctrl/pinctrl-rockchip.h +++ b/drivers/pinctrl/pinctrl-rockchip.h @@ -194,6 +194,7 @@ enum rockchip_pinctrl_type { RK3188, RK3288, RK3308, + RK3308B, RK3328, RK3368, RK3399, @@ -400,9 +401,9 @@ struct rockchip_pin_ctrl { int pmu_mux_offset; int grf_drv_offset; int pmu_drv_offset; - struct rockchip_mux_recalced_data *iomux_recalced; + const struct rockchip_mux_recalced_data *iomux_recalced; u32 niomux_recalced; - struct rockchip_mux_route_data *iomux_routes; + const struct rockchip_mux_route_data *iomux_routes; u32 niomux_routes; int (*pull_calc_reg)(struct rockchip_pin_bank *bank, diff --git a/drivers/pinctrl/pinctrl-rp1.c b/drivers/pinctrl/pinctrl-rp1.c index fc4ed68ea5ac..dd0e85c2ca33 100644 --- a/drivers/pinctrl/pinctrl-rp1.c +++ b/drivers/pinctrl/pinctrl-rp1.c @@ -1085,7 +1085,7 @@ static void rp1_pctl_pin_dbg_show(struct pinctrl_dev *pctldev, seq_printf(s, "function %s (%s) in %s; irq %d (%s)", rp1_func_names[fsel].name, rp1_func_names[func].name, - value ? "hi" : "lo", + str_hi_lo(value), irq, irq_type_names[pin->irq_type]); } diff --git a/drivers/pinctrl/pinctrl-stmfx.c b/drivers/pinctrl/pinctrl-stmfx.c index 03ee13844b50..935cace7f645 100644 --- a/drivers/pinctrl/pinctrl-stmfx.c +++ b/drivers/pinctrl/pinctrl-stmfx.c @@ -727,10 +727,8 @@ static int stmfx_pinctrl_probe(struct platform_device *pdev) stmfx_pinctrl_irq_thread_fn, IRQF_ONESHOT, dev_name(pctl->dev), pctl); - if (ret) { - dev_err(pctl->dev, "cannot request irq%d\n", irq); + if (ret) return ret; - } dev_info(pctl->dev, "%ld GPIOs available\n", hweight_long(pctl->gpio_valid_mask)); diff --git a/drivers/pinctrl/pinctrl-sx150x.c b/drivers/pinctrl/pinctrl-sx150x.c index b59d913513d5..89fdfa96843f 100644 --- a/drivers/pinctrl/pinctrl-sx150x.c +++ b/drivers/pinctrl/pinctrl-sx150x.c @@ -850,6 +850,7 @@ static const struct i2c_device_id sx150x_id[] = { { .name = "sx1509q", .driver_data = (kernel_ulong_t)&sx1509q_device_data }, { } }; +MODULE_DEVICE_TABLE(i2c, sx150x_id); static const struct of_device_id sx150x_of_match[] = { { .compatible = "semtech,sx1501q", .data = &sx1501q_device_data }, diff --git a/drivers/pinctrl/pinctrl-tb10x.c b/drivers/pinctrl/pinctrl-tb10x.c index 3f581404a9b9..b7cbd69dd877 100644 --- a/drivers/pinctrl/pinctrl-tb10x.c +++ b/drivers/pinctrl/pinctrl-tb10x.c @@ -479,7 +479,7 @@ struct tb10x_port { */ struct tb10x_pinctrl { struct pinctrl_dev *pctl; - void *base; + void __iomem *base; const struct tb10x_pinfuncgrp *pingroups; unsigned int pinfuncgrpcnt; unsigned int pinfuncnt; diff --git a/drivers/pinctrl/renesas/gpio.c b/drivers/pinctrl/renesas/gpio.c index 2293af642849..b49a3e14da91 100644 --- a/drivers/pinctrl/renesas/gpio.c +++ b/drivers/pinctrl/renesas/gpio.c @@ -271,13 +271,41 @@ static int gpio_function_request(struct gpio_chip *gc, unsigned offset) return ret; } +static void sh_pfc_fwnode_put(void *data) +{ + fwnode_handle_put(data); +} + static int gpio_function_setup(struct sh_pfc_chip *chip) { struct sh_pfc *pfc = chip->pfc; struct gpio_chip *gc = &chip->gpio_chip; + struct fwnode_handle *fwnode = dev_fwnode(pfc->dev); gc->request = gpio_function_request; + if (is_software_node(fwnode)) { + fwnode = fwnode_get_named_child_node(fwnode, "functions"); + if (fwnode) { + int ret; + + ret = devm_add_action_or_reset(pfc->dev, + sh_pfc_fwnode_put, + fwnode); + if (ret) + return ret; + + gc->fwnode = fwnode; + } + } + + /* + * If we did not find 'functions' node, explicitly mask the parent's + * fwnode to prevent gpiolib from reusing it for function GPIOs. + */ + if (!gc->fwnode) + gc->fwnode = ERR_PTR(-ENODEV); + gc->label = pfc->info->name; gc->owner = THIS_MODULE; gc->base = pfc->nr_gpio_pins; diff --git a/drivers/pinctrl/renesas/pinctrl-rza2.c b/drivers/pinctrl/renesas/pinctrl-rza2.c index 8618f32ed26a..4cab641c3350 100644 --- a/drivers/pinctrl/renesas/pinctrl-rza2.c +++ b/drivers/pinctrl/renesas/pinctrl-rza2.c @@ -44,12 +44,12 @@ struct rza2_pinctrl_priv { struct device *dev; void __iomem *base; - struct pinctrl_pin_desc *pins; struct pinctrl_desc desc; struct pinctrl_dev *pctl; struct pinctrl_gpio_range gpio_range; - int npins; + unsigned int npins; struct mutex mutex; /* serialize adding groups and functions */ + struct pinctrl_pin_desc pins[] __counted_by(npins); }; #define RZA2_PDR(port) (0x0000 + (port) * 2) /* Direction 16-bit */ @@ -289,21 +289,15 @@ static int rza2_gpio_register(struct rza2_pinctrl_priv *priv) static int rza2_pinctrl_register(struct rza2_pinctrl_priv *priv) { - struct pinctrl_pin_desc *pins; unsigned int i; int ret; - pins = devm_kcalloc(priv->dev, priv->npins, sizeof(*pins), GFP_KERNEL); - if (!pins) - return -ENOMEM; - - priv->pins = pins; - priv->desc.pins = pins; + priv->desc.pins = priv->pins; priv->desc.npins = priv->npins; for (i = 0; i < priv->npins; i++) { - pins[i].number = i; - pins[i].name = rza2_gpio_names[i]; + priv->pins[i].number = i; + priv->pins[i].name = rza2_gpio_names[i]; } ret = devm_pinctrl_register_and_init(priv->dev, &priv->desc, priv, @@ -482,12 +476,17 @@ static const struct pinmux_ops rza2_pinmux_ops = { static int rza2_pinctrl_probe(struct platform_device *pdev) { struct rza2_pinctrl_priv *priv; + unsigned int npins; int ret; - priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); + npins = (uintptr_t)of_device_get_match_data(&pdev->dev) * + RZA2_PINS_PER_PORT; + + priv = devm_kzalloc(&pdev->dev, struct_size(priv, pins, npins), GFP_KERNEL); if (!priv) return -ENOMEM; + priv->npins = npins; priv->dev = &pdev->dev; priv->base = devm_platform_ioremap_resource(pdev, 0); @@ -498,9 +497,6 @@ static int rza2_pinctrl_probe(struct platform_device *pdev) platform_set_drvdata(pdev, priv); - priv->npins = (int)(uintptr_t)of_device_get_match_data(&pdev->dev) * - RZA2_PINS_PER_PORT; - priv->desc.name = DRIVER_NAME; priv->desc.pctlops = &rza2_pinctrl_ops; priv->desc.pmxops = &rza2_pinmux_ops;