debugcc: move post_div_val into struct debug_mux

It looks like post_div_val is a property of debug_mux rather than the
clock itself. It is equal for all the clocks being set. So, set it on a
mux-by-mux bases.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>

debugcc.c

@@ -80,7 +80,7 @@ static unsigned int measure_ticks(struct debug_mux *gcc, unsigned int ticks)
 	return val;
 }
 
-static void mux_enable(struct debug_mux *mux, int selector, int div)
+static void mux_enable(struct debug_mux *mux, int selector)
 {
 	uint32_t val;
 
@@ -92,7 +92,7 @@ static void mux_enable(struct debug_mux *mux, int selector, int div)
 	if (mux->div_mask) {
 		val = readl(mux->base + mux->div_reg);
 		val &= ~mux->div_mask;
-		val |= (div - 1) << mux->div_shift;
+		val |= (mux->div_val - 1) << mux->div_shift;
 		writel(val, mux->base + mux->div_reg);
 	}
 
@@ -137,9 +137,9 @@ static void measure(const struct measure_clk *clk)
 	}
 
 	if (clk->leaf)
-		mux_enable(clk->leaf, clk->leaf_mux, clk->leaf_div);
+		mux_enable(clk->leaf, clk->leaf_mux);
 
-	mux_enable(clk->primary, clk->mux, clk->post_div);
+	mux_enable(clk->primary, clk->mux);
 
 	writel(1, gcc->base + gcc->xo_div4_reg);
 
@@ -161,10 +161,11 @@ static void measure(const struct measure_clk *clk)
 	if (clk->leaf)
 		mux_disable(clk->leaf);
 
-	if (clk->leaf)
-		raw_count_full *= clk->leaf_div;
+	if (clk->leaf && clk->leaf->div_val)
+		raw_count_full *= clk->leaf->div_val;
 
-	raw_count_full *= clk->post_div;
+	if (clk->primary->div_val)
+		raw_count_full *= clk->primary->div_val;
 
 	if (clk->fixed_div)
 		raw_count_full *= clk->fixed_div;

debugcc.h

@@ -48,6 +48,7 @@ struct debug_mux {
 	unsigned int div_reg;
 	unsigned int div_shift;
 	unsigned int div_mask;
+	unsigned int div_val;
 
 	unsigned int xo_div4_reg;
 	unsigned int debug_ctl_reg;
@@ -61,11 +62,9 @@ struct measure_clk {
 	char *name;
 	struct debug_mux *primary;
 	int mux;
-	int post_div;
 
 	struct debug_mux *leaf;
 	int leaf_mux;
-	int leaf_div;
 
 	unsigned int fixed_div;
 };

qcs404.c

@@ -64,6 +64,7 @@ static struct debug_mux gcc = {
 	.div_reg = GCC_DEBUG_CLK_CTL,
 	.div_shift = 12,
 	.div_mask = 0xf << 12,
+	.div_val = 4,
 
 	.xo_div4_reg = GCC_XO_DIV4_CBCR,
 	.debug_ctl_reg = GCC_CLOCK_FREQ_MEASURE_CTL,
@@ -87,108 +88,108 @@ static struct debug_mux turing = {
 };
 
 static struct measure_clk qcs404_clocks[] = {
-	{ "snoc_clk", &gcc, 0, 4 },
-	{ "gcc_sys_noc_usb3_clk", &gcc, 1, 4 },
-	{ "pnoc_clk", &gcc, 8, 4 },
-	{ "gcc_pcnoc_usb2_clk", &gcc, 9, 4 },
-	{ "gcc_pcnoc_usb3_clk", &gcc, 10, 4 },
-	{ "gcc_gp1_clk", &gcc, 16, 4 },
-	{ "gcc_gp2_clk", &gcc, 17, 4 },
-	{ "gcc_gp3_clk", &gcc, 18, 4 },
-	{ "gcc_bimc_gfx_clk", &gcc, 45, 4 },
-	{ "aon_clk_src", &gcc, 50, 1, &turing, 1, 4 },
-	{ "turing_wrapper_aon_clk", &gcc, 50, 1, &turing, 2, 4 },
-	{ "turing_wrapper_cnoc_sway_aon_clk", &gcc, 50, 1, &turing, 3, 4 },
-	{ "turing_wrapper_qos_ahbs_aon_clk", &gcc, 50, 1, &turing, 4, 4 },
-	{ "q6ss_ahbm_aon_clk", &gcc, 50, 1, &turing, 5, 4 },
-	{ "q6ss_ahbs_aon_clk", &gcc, 50, 1, &turing, 6, 4},
-	{ "turing_wrapper_bus_timeout_aon_clk", &gcc, 50, 1, &turing, 7, 4 },
-	{ "turing_wrapper_rscc_aon_clk", &gcc, 50, 1, &turing, 8, 4 },
-	{ "q6ss_alt_reset_aon_clk", &gcc, 50, 1, &turing, 10, 4 },
-	{ "qos_fixed_lat_counter_clk_src", &gcc, 50, 1, &turing, 11, 4 },
-	{ "turing_wrapper_qos_dmonitor_fixed_lat_counter_clk", &gcc, 50, 1, &turing, 12, 4 },
-	{ "turing_wrapper_qos_danger_fixed_lat_counter_clk", &gcc, 50, 1, &turing, 13, 4 },
-	{ "q6_xo_clk_src", &gcc, 50, 1, &turing, 14, 4 },
-	{ "qos_xo_clk_src", &gcc, 50, 1, &turing, 15, 4 },
-	{ "turing_wrapper_qos_xo_lat_counter_clk", &gcc, 50, 1, &turing, 16, 4 },
-	{ "bcr_slp_clk_src", &gcc, 50, 1, &turing, 19, 4 },
-	{ "q6ss_bcr_slp_clk", &gcc, 50, 1, &turing, 20, 4 },
-	{ "turing_wrapper_cnoc_ahbs_clk", &gcc, 50, 1, &turing, 28, 4 },
-	{ "q6ss_q6_axim_clk", &gcc, 50, 1, &turing, 29, 4 },
-	{ "q6ss_sleep_clk_src", &gcc, 50, 1, &turing, 33, 4 },
-	{ "qdsp6ss_xo_clk", &gcc, 50, 1, &turing, 36, 4 },
-	{ "qdsp6ss_sleep_clk", &gcc, 50, 1, &turing, 37, 4 },
-	{ "q6ss_dbg_in_clk", &gcc, 50, 1, &turing, 39, 4 },
-	{ "gcc_usb_hs_system_clk", &gcc, 96, 4 },
-	{ "gcc_usb_hs_inactivity_timers_clk", &gcc, 98, 4 },
-	{ "gcc_usb2a_phy_sleep_clk", &gcc, 99, 4 },
-	{ "gcc_usb_hs_phy_cfg_ahb_clk", &gcc, 100, 4 },
-	{ "gcc_usb20_mock_utmi_clk", &gcc, 101, 4 },
-	{ "gcc_sdcc1_apps_clk", &gcc, 104, 4 },
-	{ "gcc_sdcc1_ahb_clk", &gcc, 105, 4 },
-	{ "gcc_sdcc1_ice_core_clk", &gcc, 106, 4 },
-	{ "gcc_sdcc2_apps_clk", &gcc, 112, 4 },
-	{ "gcc_sdcc2_ahb_clk", &gcc, 113, 4 },
-	{ "gcc_usb30_master_clk", &gcc, 120, 4 },
-	{ "gcc_usb30_sleep_clk", &gcc, 121, 4 },
-	{ "gcc_usb30_mock_utmi_clk", &gcc, 122, 4 },
-	{ "gcc_usb3_phy_pipe_clk", &gcc, 123, 4 },
-	{ "gcc_usb3_phy_aux_clk", &gcc, 124, 4 },
-	{ "gcc_eth_axi_clk", &gcc, 128, 4 },
-	{ "gcc_eth_rgmii_clk", &gcc, 129, 4 },
-	{ "gcc_eth_slave_ahb_clk", &gcc, 130, 4 },
-	{ "gcc_eth_ptp_clk", &gcc, 131, 4 },
-	{ "gcc_blsp1_ahb_clk", &gcc, 136, 4 },
-	{ "gcc_blsp1_qup1_spi_apps_clk", &gcc, 138, 4 },
-	{ "wcnss_m_clk", &gcc, 138, 4 },
-	{ "gcc_blsp1_qup1_i2c_apps_clk", &gcc, 139, 4 },
-	{ "gcc_blsp1_uart1_apps_clk", &gcc, 140, 4 },
-	{ "gcc_blsp1_qup2_spi_apps_clk", &gcc, 142, 4 },
-	{ "gcc_blsp1_qup2_i2c_apps_clk", &gcc, 143, 4 },
-	{ "gcc_blsp1_uart2_apps_clk", &gcc, 144, 4 },
-	{ "gcc_blsp1_qup3_spi_apps_clk", &gcc, 146, 4 },
-	{ "gcc_blsp1_qup3_i2c_apps_clk", &gcc, 147, 4 },
-	{ "gcc_blsp1_qup4_spi_apps_clk", &gcc, 148, 4 },
-	{ "gcc_blsp1_qup4_i2c_apps_clk", &gcc, 149, 4 },
-	{ "gcc_blsp1_uart3_apps_clk", &gcc, 150, 4 },
-	{ "gcc_blsp1_qup0_spi_apps_clk", &gcc, 152, 4 },
-	{ "gcc_blsp1_qup0_i2c_apps_clk", &gcc, 153, 4 },
-	{ "gcc_blsp1_uart0_apps_clk", &gcc, 154, 4 },
-	{ "gcc_blsp2_ahb_clk", &gcc, 160, 4 },
-	{ "gcc_blsp2_qup0_i2c_apps_clk", &gcc, 162, 4 },
-	{ "gcc_blsp2_qup0_spi_apps_clk", &gcc, 163, 4 },
-	{ "gcc_blsp2_uart0_apps_clk", &gcc, 164, 4 },
-	{ "gcc_pcie_0_slv_axi_clk", &gcc, 168, 4 },
-	{ "gcc_pcie_0_mstr_axi_clk", &gcc, 169, 4 },
-	{ "gcc_pcie_0_cfg_ahb_clk", &gcc, 170, 4 },
-	{ "gcc_pcie_0_aux_clk", &gcc, 171, 4 },
-	{ "gcc_pcie_0_pipe_clk", &gcc, 172, 4 },
-	{ "pcie0_pipe_clk", &gcc, 173, 1 },
-	{ "qpic_clk", &gcc, 192, 4 },
-	{ "gcc_pdm_ahb_clk", &gcc, 208, 4 },
-	{ "gcc_pdm2_clk", &gcc, 210, 4 },
-	{ "gcc_pwm0_xo512_clk", &gcc, 211, 4 },
-	{ "gcc_pwm1_xo512_clk", &gcc, 212, 4 },
-	{ "gcc_pwm2_xo512_clk", &gcc, 213, 4 },
-	{ "gcc_prng_ahb_clk", &gcc, 216, 4 },
-	{ "gcc_geni_ir_s_clk", &gcc, 238, 4 },
-	{ "gcc_boot_rom_ahb_clk", &gcc, 248, 4 },
-	{ "ce1_clk", &gcc, 312, 4 },
-	{ "bimc_clk", &gcc, 346, 4 },
-	{ "bimc_fsm_ddr_clk", &gcc, 350, 1 },
-	{ "gcc_apss_ahb_clk", &gcc, 360, 4 },
-	{ "gcc_dcc_clk", &gcc, 441, 4 },
-	{ "gcc_oxili_gfx3d_clk", &gcc, 490, 4 },
-	{ "gcc_oxili_ahb_clk", &gcc, 491, 4 },
-	{ "gcc_mdss_hdmi_pclk_clk", &gcc, 497, 4 },
-	{ "gcc_mdss_hdmi_app_clk", &gcc, 498, 4 },
-	{ "gcc_mdss_ahb_clk", &gcc, 502, 4 },
-	{ "gcc_mdss_axi_clk", &gcc, 503, 4 },
-	{ "gcc_mdss_pclk0_clk", &gcc, 504, 4 },
-	{ "gcc_mdss_mdp_clk", &gcc, 505, 4 },
-	{ "gcc_mdss_vsync_clk", &gcc, 507, 4 },
-	{ "gcc_mdss_byte0_clk", &gcc, 508, 4 },
-	{ "gcc_mdss_esc0_clk", &gcc, 509, 4 },
+	{ "snoc_clk", &gcc, 0 },
+	{ "gcc_sys_noc_usb3_clk", &gcc, 1 },
+	{ "pnoc_clk", &gcc, 8 },
+	{ "gcc_pcnoc_usb2_clk", &gcc, 9 },
+	{ "gcc_pcnoc_usb3_clk", &gcc, 10 },
+	{ "gcc_gp1_clk", &gcc, 16 },
+	{ "gcc_gp2_clk", &gcc, 17 },
+	{ "gcc_gp3_clk", &gcc, 18 },
+	{ "gcc_bimc_gfx_clk", &gcc, 45 },
+	{ "aon_clk_src", &gcc, 50, &turing, 1},
+	{ "turing_wrapper_aon_clk", &gcc, 50, &turing, 2},
+	{ "turing_wrapper_cnoc_sway_aon_clk", &gcc, 50, &turing, 3},
+	{ "turing_wrapper_qos_ahbs_aon_clk", &gcc, 50, &turing, 4},
+	{ "q6ss_ahbm_aon_clk", &gcc, 50, &turing, 5},
+	{ "q6ss_ahbs_aon_clk", &gcc, 50, &turing, 6},
+	{ "turing_wrapper_bus_timeout_aon_clk", &gcc, 50, &turing, 7},
+	{ "turing_wrapper_rscc_aon_clk", &gcc, 50, &turing, 8},
+	{ "q6ss_alt_reset_aon_clk", &gcc, 50, &turing, 10},
+	{ "qos_fixed_lat_counter_clk_src", &gcc, 50, &turing, 11},
+	{ "turing_wrapper_qos_dmonitor_fixed_lat_counter_clk", &gcc, 50, &turing, 12},
+	{ "turing_wrapper_qos_danger_fixed_lat_counter_clk", &gcc, 50, &turing, 13},
+	{ "q6_xo_clk_src", &gcc, 50, &turing, 14},
+	{ "qos_xo_clk_src", &gcc, 50, &turing, 15},
+	{ "turing_wrapper_qos_xo_lat_counter_clk", &gcc, 50, &turing, 16},
+	{ "bcr_slp_clk_src", &gcc, 50, &turing, 19},
+	{ "q6ss_bcr_slp_clk", &gcc, 50, &turing, 20},
+	{ "turing_wrapper_cnoc_ahbs_clk", &gcc, 50, &turing, 28},
+	{ "q6ss_q6_axim_clk", &gcc, 50, &turing, 29},
+	{ "q6ss_sleep_clk_src", &gcc, 50, &turing, 33},
+	{ "qdsp6ss_xo_clk", &gcc, 50, &turing, 36},
+	{ "qdsp6ss_sleep_clk", &gcc, 50, &turing, 37},
+	{ "q6ss_dbg_in_clk", &gcc, 50, &turing, 39},
+	{ "gcc_usb_hs_system_clk", &gcc, 96 },
+	{ "gcc_usb_hs_inactivity_timers_clk", &gcc, 98 },
+	{ "gcc_usb2a_phy_sleep_clk", &gcc, 99 },
+	{ "gcc_usb_hs_phy_cfg_ahb_clk", &gcc, 100 },
+	{ "gcc_usb20_mock_utmi_clk", &gcc, 101 },
+	{ "gcc_sdcc1_apps_clk", &gcc, 104 },
+	{ "gcc_sdcc1_ahb_clk", &gcc, 105 },
+	{ "gcc_sdcc1_ice_core_clk", &gcc, 106 },
+	{ "gcc_sdcc2_apps_clk", &gcc, 112 },
+	{ "gcc_sdcc2_ahb_clk", &gcc, 113 },
+	{ "gcc_usb30_master_clk", &gcc, 120 },
+	{ "gcc_usb30_sleep_clk", &gcc, 121 },
+	{ "gcc_usb30_mock_utmi_clk", &gcc, 122 },
+	{ "gcc_usb3_phy_pipe_clk", &gcc, 123 },
+	{ "gcc_usb3_phy_aux_clk", &gcc, 124 },
+	{ "gcc_eth_axi_clk", &gcc, 128 },
+	{ "gcc_eth_rgmii_clk", &gcc, 129 },
+	{ "gcc_eth_slave_ahb_clk", &gcc, 130 },
+	{ "gcc_eth_ptp_clk", &gcc, 131 },
+	{ "gcc_blsp1_ahb_clk", &gcc, 136 },
+	{ "gcc_blsp1_qup1_spi_apps_clk", &gcc, 138 },
+	{ "wcnss_m_clk", &gcc, 138 },
+	{ "gcc_blsp1_qup1_i2c_apps_clk", &gcc, 139 },
+	{ "gcc_blsp1_uart1_apps_clk", &gcc, 140 },
+	{ "gcc_blsp1_qup2_spi_apps_clk", &gcc, 142 },
+	{ "gcc_blsp1_qup2_i2c_apps_clk", &gcc, 143 },
+	{ "gcc_blsp1_uart2_apps_clk", &gcc, 144 },
+	{ "gcc_blsp1_qup3_spi_apps_clk", &gcc, 146 },
+	{ "gcc_blsp1_qup3_i2c_apps_clk", &gcc, 147 },
+	{ "gcc_blsp1_qup4_spi_apps_clk", &gcc, 148 },
+	{ "gcc_blsp1_qup4_i2c_apps_clk", &gcc, 149 },
+	{ "gcc_blsp1_uart3_apps_clk", &gcc, 150 },
+	{ "gcc_blsp1_qup0_spi_apps_clk", &gcc, 152 },
+	{ "gcc_blsp1_qup0_i2c_apps_clk", &gcc, 153 },
+	{ "gcc_blsp1_uart0_apps_clk", &gcc, 154 },
+	{ "gcc_blsp2_ahb_clk", &gcc, 160 },
+	{ "gcc_blsp2_qup0_i2c_apps_clk", &gcc, 162 },
+	{ "gcc_blsp2_qup0_spi_apps_clk", &gcc, 163 },
+	{ "gcc_blsp2_uart0_apps_clk", &gcc, 164 },
+	{ "gcc_pcie_0_slv_axi_clk", &gcc, 168 },
+	{ "gcc_pcie_0_mstr_axi_clk", &gcc, 169 },
+	{ "gcc_pcie_0_cfg_ahb_clk", &gcc, 170 },
+	{ "gcc_pcie_0_aux_clk", &gcc, 171 },
+	{ "gcc_pcie_0_pipe_clk", &gcc, 172 },
+	//{ "pcie0_pipe_clk", &gcc, 173, 1 },
+	{ "qpic_clk", &gcc, 192 },
+	{ "gcc_pdm_ahb_clk", &gcc, 208 },
+	{ "gcc_pdm2_clk", &gcc, 210 },
+	{ "gcc_pwm0_xo512_clk", &gcc, 211 },
+	{ "gcc_pwm1_xo512_clk", &gcc, 212 },
+	{ "gcc_pwm2_xo512_clk", &gcc, 213 },
+	{ "gcc_prng_ahb_clk", &gcc, 216 },
+	{ "gcc_geni_ir_s_clk", &gcc, 238 },
+	{ "gcc_boot_rom_ahb_clk", &gcc, 248 },
+	{ "ce1_clk", &gcc, 312 },
+	{ "bimc_clk", &gcc, 346 },
+	//{ "bimc_fsm_ddr_clk", &gcc, 350, 1 },
+	{ "gcc_apss_ahb_clk", &gcc, 360 },
+	{ "gcc_dcc_clk", &gcc, 441 },
+	{ "gcc_oxili_gfx3d_clk", &gcc, 490 },
+	{ "gcc_oxili_ahb_clk", &gcc, 491 },
+	{ "gcc_mdss_hdmi_pclk_clk", &gcc, 497 },
+	{ "gcc_mdss_hdmi_app_clk", &gcc, 498 },
+	{ "gcc_mdss_ahb_clk", &gcc, 502 },
+	{ "gcc_mdss_axi_clk", &gcc, 503 },
+	{ "gcc_mdss_pclk0_clk", &gcc, 504 },
+	{ "gcc_mdss_mdp_clk", &gcc, 505 },
+	{ "gcc_mdss_vsync_clk", &gcc, 507 },
+	{ "gcc_mdss_byte0_clk", &gcc, 508 },
+	{ "gcc_mdss_esc0_clk", &gcc, 509 },
 	{}
 };