diff --git a/debugcc.c b/debugcc.c index c829dfe..f6b6a6c 100644 --- a/debugcc.c +++ b/debugcc.c @@ -80,7 +80,7 @@ static unsigned int measure_ticks(struct debug_mux *gcc, unsigned int ticks) return val; } -static void mux_enable(struct debug_mux *mux, int selector, int div) +static void mux_enable(struct debug_mux *mux, int selector) { uint32_t val; @@ -92,7 +92,7 @@ static void mux_enable(struct debug_mux *mux, int selector, int div) if (mux->div_mask) { val = readl(mux->base + mux->div_reg); val &= ~mux->div_mask; - val |= (div - 1) << mux->div_shift; + val |= (mux->div_val - 1) << mux->div_shift; writel(val, mux->base + mux->div_reg); } @@ -137,9 +137,9 @@ static void measure(const struct measure_clk *clk) } if (clk->leaf) - mux_enable(clk->leaf, clk->leaf_mux, clk->leaf_div); + mux_enable(clk->leaf, clk->leaf_mux); - mux_enable(clk->primary, clk->mux, clk->post_div); + mux_enable(clk->primary, clk->mux); writel(1, gcc->base + gcc->xo_div4_reg); @@ -161,10 +161,11 @@ static void measure(const struct measure_clk *clk) if (clk->leaf) mux_disable(clk->leaf); - if (clk->leaf) - raw_count_full *= clk->leaf_div; + if (clk->leaf && clk->leaf->div_val) + raw_count_full *= clk->leaf->div_val; - raw_count_full *= clk->post_div; + if (clk->primary->div_val) + raw_count_full *= clk->primary->div_val; if (clk->fixed_div) raw_count_full *= clk->fixed_div; diff --git a/debugcc.h b/debugcc.h index 8167f22..15f87f9 100644 --- a/debugcc.h +++ b/debugcc.h @@ -48,6 +48,7 @@ struct debug_mux { unsigned int div_reg; unsigned int div_shift; unsigned int div_mask; + unsigned int div_val; unsigned int xo_div4_reg; unsigned int debug_ctl_reg; @@ -61,11 +62,9 @@ struct measure_clk { char *name; struct debug_mux *primary; int mux; - int post_div; struct debug_mux *leaf; int leaf_mux; - int leaf_div; unsigned int fixed_div; }; diff --git a/qcs404.c b/qcs404.c index 535346a..553ee05 100644 --- a/qcs404.c +++ b/qcs404.c @@ -64,6 +64,7 @@ static struct debug_mux gcc = { .div_reg = GCC_DEBUG_CLK_CTL, .div_shift = 12, .div_mask = 0xf << 12, + .div_val = 4, .xo_div4_reg = GCC_XO_DIV4_CBCR, .debug_ctl_reg = GCC_CLOCK_FREQ_MEASURE_CTL, @@ -87,108 +88,108 @@ static struct debug_mux turing = { }; static struct measure_clk qcs404_clocks[] = { - { "snoc_clk", &gcc, 0, 4 }, - { "gcc_sys_noc_usb3_clk", &gcc, 1, 4 }, - { "pnoc_clk", &gcc, 8, 4 }, - { "gcc_pcnoc_usb2_clk", &gcc, 9, 4 }, - { "gcc_pcnoc_usb3_clk", &gcc, 10, 4 }, - { "gcc_gp1_clk", &gcc, 16, 4 }, - { "gcc_gp2_clk", &gcc, 17, 4 }, - { "gcc_gp3_clk", &gcc, 18, 4 }, - { "gcc_bimc_gfx_clk", &gcc, 45, 4 }, - { "aon_clk_src", &gcc, 50, 1, &turing, 1, 4 }, - { "turing_wrapper_aon_clk", &gcc, 50, 1, &turing, 2, 4 }, - { "turing_wrapper_cnoc_sway_aon_clk", &gcc, 50, 1, &turing, 3, 4 }, - { "turing_wrapper_qos_ahbs_aon_clk", &gcc, 50, 1, &turing, 4, 4 }, - { "q6ss_ahbm_aon_clk", &gcc, 50, 1, &turing, 5, 4 }, - { "q6ss_ahbs_aon_clk", &gcc, 50, 1, &turing, 6, 4}, - { "turing_wrapper_bus_timeout_aon_clk", &gcc, 50, 1, &turing, 7, 4 }, - { "turing_wrapper_rscc_aon_clk", &gcc, 50, 1, &turing, 8, 4 }, - { "q6ss_alt_reset_aon_clk", &gcc, 50, 1, &turing, 10, 4 }, - { "qos_fixed_lat_counter_clk_src", &gcc, 50, 1, &turing, 11, 4 }, - { "turing_wrapper_qos_dmonitor_fixed_lat_counter_clk", &gcc, 50, 1, &turing, 12, 4 }, - { "turing_wrapper_qos_danger_fixed_lat_counter_clk", &gcc, 50, 1, &turing, 13, 4 }, - { "q6_xo_clk_src", &gcc, 50, 1, &turing, 14, 4 }, - { "qos_xo_clk_src", &gcc, 50, 1, &turing, 15, 4 }, - { "turing_wrapper_qos_xo_lat_counter_clk", &gcc, 50, 1, &turing, 16, 4 }, - { "bcr_slp_clk_src", &gcc, 50, 1, &turing, 19, 4 }, - { "q6ss_bcr_slp_clk", &gcc, 50, 1, &turing, 20, 4 }, - { "turing_wrapper_cnoc_ahbs_clk", &gcc, 50, 1, &turing, 28, 4 }, - { "q6ss_q6_axim_clk", &gcc, 50, 1, &turing, 29, 4 }, - { "q6ss_sleep_clk_src", &gcc, 50, 1, &turing, 33, 4 }, - { "qdsp6ss_xo_clk", &gcc, 50, 1, &turing, 36, 4 }, - { "qdsp6ss_sleep_clk", &gcc, 50, 1, &turing, 37, 4 }, - { "q6ss_dbg_in_clk", &gcc, 50, 1, &turing, 39, 4 }, - { "gcc_usb_hs_system_clk", &gcc, 96, 4 }, - { "gcc_usb_hs_inactivity_timers_clk", &gcc, 98, 4 }, - { "gcc_usb2a_phy_sleep_clk", &gcc, 99, 4 }, - { "gcc_usb_hs_phy_cfg_ahb_clk", &gcc, 100, 4 }, - { "gcc_usb20_mock_utmi_clk", &gcc, 101, 4 }, - { "gcc_sdcc1_apps_clk", &gcc, 104, 4 }, - { "gcc_sdcc1_ahb_clk", &gcc, 105, 4 }, - { "gcc_sdcc1_ice_core_clk", &gcc, 106, 4 }, - { "gcc_sdcc2_apps_clk", &gcc, 112, 4 }, - { "gcc_sdcc2_ahb_clk", &gcc, 113, 4 }, - { "gcc_usb30_master_clk", &gcc, 120, 4 }, - { "gcc_usb30_sleep_clk", &gcc, 121, 4 }, - { "gcc_usb30_mock_utmi_clk", &gcc, 122, 4 }, - { "gcc_usb3_phy_pipe_clk", &gcc, 123, 4 }, - { "gcc_usb3_phy_aux_clk", &gcc, 124, 4 }, - { "gcc_eth_axi_clk", &gcc, 128, 4 }, - { "gcc_eth_rgmii_clk", &gcc, 129, 4 }, - { "gcc_eth_slave_ahb_clk", &gcc, 130, 4 }, - { "gcc_eth_ptp_clk", &gcc, 131, 4 }, - { "gcc_blsp1_ahb_clk", &gcc, 136, 4 }, - { "gcc_blsp1_qup1_spi_apps_clk", &gcc, 138, 4 }, - { "wcnss_m_clk", &gcc, 138, 4 }, - { "gcc_blsp1_qup1_i2c_apps_clk", &gcc, 139, 4 }, - { "gcc_blsp1_uart1_apps_clk", &gcc, 140, 4 }, - { "gcc_blsp1_qup2_spi_apps_clk", &gcc, 142, 4 }, - { "gcc_blsp1_qup2_i2c_apps_clk", &gcc, 143, 4 }, - { "gcc_blsp1_uart2_apps_clk", &gcc, 144, 4 }, - { "gcc_blsp1_qup3_spi_apps_clk", &gcc, 146, 4 }, - { "gcc_blsp1_qup3_i2c_apps_clk", &gcc, 147, 4 }, - { "gcc_blsp1_qup4_spi_apps_clk", &gcc, 148, 4 }, - { "gcc_blsp1_qup4_i2c_apps_clk", &gcc, 149, 4 }, - { "gcc_blsp1_uart3_apps_clk", &gcc, 150, 4 }, - { "gcc_blsp1_qup0_spi_apps_clk", &gcc, 152, 4 }, - { "gcc_blsp1_qup0_i2c_apps_clk", &gcc, 153, 4 }, - { "gcc_blsp1_uart0_apps_clk", &gcc, 154, 4 }, - { "gcc_blsp2_ahb_clk", &gcc, 160, 4 }, - { "gcc_blsp2_qup0_i2c_apps_clk", &gcc, 162, 4 }, - { "gcc_blsp2_qup0_spi_apps_clk", &gcc, 163, 4 }, - { "gcc_blsp2_uart0_apps_clk", &gcc, 164, 4 }, - { "gcc_pcie_0_slv_axi_clk", &gcc, 168, 4 }, - { "gcc_pcie_0_mstr_axi_clk", &gcc, 169, 4 }, - { "gcc_pcie_0_cfg_ahb_clk", &gcc, 170, 4 }, - { "gcc_pcie_0_aux_clk", &gcc, 171, 4 }, - { "gcc_pcie_0_pipe_clk", &gcc, 172, 4 }, - { "pcie0_pipe_clk", &gcc, 173, 1 }, - { "qpic_clk", &gcc, 192, 4 }, - { "gcc_pdm_ahb_clk", &gcc, 208, 4 }, - { "gcc_pdm2_clk", &gcc, 210, 4 }, - { "gcc_pwm0_xo512_clk", &gcc, 211, 4 }, - { "gcc_pwm1_xo512_clk", &gcc, 212, 4 }, - { "gcc_pwm2_xo512_clk", &gcc, 213, 4 }, - { "gcc_prng_ahb_clk", &gcc, 216, 4 }, - { "gcc_geni_ir_s_clk", &gcc, 238, 4 }, - { "gcc_boot_rom_ahb_clk", &gcc, 248, 4 }, - { "ce1_clk", &gcc, 312, 4 }, - { "bimc_clk", &gcc, 346, 4 }, - { "bimc_fsm_ddr_clk", &gcc, 350, 1 }, - { "gcc_apss_ahb_clk", &gcc, 360, 4 }, - { "gcc_dcc_clk", &gcc, 441, 4 }, - { "gcc_oxili_gfx3d_clk", &gcc, 490, 4 }, - { "gcc_oxili_ahb_clk", &gcc, 491, 4 }, - { "gcc_mdss_hdmi_pclk_clk", &gcc, 497, 4 }, - { "gcc_mdss_hdmi_app_clk", &gcc, 498, 4 }, - { "gcc_mdss_ahb_clk", &gcc, 502, 4 }, - { "gcc_mdss_axi_clk", &gcc, 503, 4 }, - { "gcc_mdss_pclk0_clk", &gcc, 504, 4 }, - { "gcc_mdss_mdp_clk", &gcc, 505, 4 }, - { "gcc_mdss_vsync_clk", &gcc, 507, 4 }, - { "gcc_mdss_byte0_clk", &gcc, 508, 4 }, - { "gcc_mdss_esc0_clk", &gcc, 509, 4 }, + { "snoc_clk", &gcc, 0 }, + { "gcc_sys_noc_usb3_clk", &gcc, 1 }, + { "pnoc_clk", &gcc, 8 }, + { "gcc_pcnoc_usb2_clk", &gcc, 9 }, + { "gcc_pcnoc_usb3_clk", &gcc, 10 }, + { "gcc_gp1_clk", &gcc, 16 }, + { "gcc_gp2_clk", &gcc, 17 }, + { "gcc_gp3_clk", &gcc, 18 }, + { "gcc_bimc_gfx_clk", &gcc, 45 }, + { "aon_clk_src", &gcc, 50, &turing, 1}, + { "turing_wrapper_aon_clk", &gcc, 50, &turing, 2}, + { "turing_wrapper_cnoc_sway_aon_clk", &gcc, 50, &turing, 3}, + { "turing_wrapper_qos_ahbs_aon_clk", &gcc, 50, &turing, 4}, + { "q6ss_ahbm_aon_clk", &gcc, 50, &turing, 5}, + { "q6ss_ahbs_aon_clk", &gcc, 50, &turing, 6}, + { "turing_wrapper_bus_timeout_aon_clk", &gcc, 50, &turing, 7}, + { "turing_wrapper_rscc_aon_clk", &gcc, 50, &turing, 8}, + { "q6ss_alt_reset_aon_clk", &gcc, 50, &turing, 10}, + { "qos_fixed_lat_counter_clk_src", &gcc, 50, &turing, 11}, + { "turing_wrapper_qos_dmonitor_fixed_lat_counter_clk", &gcc, 50, &turing, 12}, + { "turing_wrapper_qos_danger_fixed_lat_counter_clk", &gcc, 50, &turing, 13}, + { "q6_xo_clk_src", &gcc, 50, &turing, 14}, + { "qos_xo_clk_src", &gcc, 50, &turing, 15}, + { "turing_wrapper_qos_xo_lat_counter_clk", &gcc, 50, &turing, 16}, + { "bcr_slp_clk_src", &gcc, 50, &turing, 19}, + { "q6ss_bcr_slp_clk", &gcc, 50, &turing, 20}, + { "turing_wrapper_cnoc_ahbs_clk", &gcc, 50, &turing, 28}, + { "q6ss_q6_axim_clk", &gcc, 50, &turing, 29}, + { "q6ss_sleep_clk_src", &gcc, 50, &turing, 33}, + { "qdsp6ss_xo_clk", &gcc, 50, &turing, 36}, + { "qdsp6ss_sleep_clk", &gcc, 50, &turing, 37}, + { "q6ss_dbg_in_clk", &gcc, 50, &turing, 39}, + { "gcc_usb_hs_system_clk", &gcc, 96 }, + { "gcc_usb_hs_inactivity_timers_clk", &gcc, 98 }, + { "gcc_usb2a_phy_sleep_clk", &gcc, 99 }, + { "gcc_usb_hs_phy_cfg_ahb_clk", &gcc, 100 }, + { "gcc_usb20_mock_utmi_clk", &gcc, 101 }, + { "gcc_sdcc1_apps_clk", &gcc, 104 }, + { "gcc_sdcc1_ahb_clk", &gcc, 105 }, + { "gcc_sdcc1_ice_core_clk", &gcc, 106 }, + { "gcc_sdcc2_apps_clk", &gcc, 112 }, + { "gcc_sdcc2_ahb_clk", &gcc, 113 }, + { "gcc_usb30_master_clk", &gcc, 120 }, + { "gcc_usb30_sleep_clk", &gcc, 121 }, + { "gcc_usb30_mock_utmi_clk", &gcc, 122 }, + { "gcc_usb3_phy_pipe_clk", &gcc, 123 }, + { "gcc_usb3_phy_aux_clk", &gcc, 124 }, + { "gcc_eth_axi_clk", &gcc, 128 }, + { "gcc_eth_rgmii_clk", &gcc, 129 }, + { "gcc_eth_slave_ahb_clk", &gcc, 130 }, + { "gcc_eth_ptp_clk", &gcc, 131 }, + { "gcc_blsp1_ahb_clk", &gcc, 136 }, + { "gcc_blsp1_qup1_spi_apps_clk", &gcc, 138 }, + { "wcnss_m_clk", &gcc, 138 }, + { "gcc_blsp1_qup1_i2c_apps_clk", &gcc, 139 }, + { "gcc_blsp1_uart1_apps_clk", &gcc, 140 }, + { "gcc_blsp1_qup2_spi_apps_clk", &gcc, 142 }, + { "gcc_blsp1_qup2_i2c_apps_clk", &gcc, 143 }, + { "gcc_blsp1_uart2_apps_clk", &gcc, 144 }, + { "gcc_blsp1_qup3_spi_apps_clk", &gcc, 146 }, + { "gcc_blsp1_qup3_i2c_apps_clk", &gcc, 147 }, + { "gcc_blsp1_qup4_spi_apps_clk", &gcc, 148 }, + { "gcc_blsp1_qup4_i2c_apps_clk", &gcc, 149 }, + { "gcc_blsp1_uart3_apps_clk", &gcc, 150 }, + { "gcc_blsp1_qup0_spi_apps_clk", &gcc, 152 }, + { "gcc_blsp1_qup0_i2c_apps_clk", &gcc, 153 }, + { "gcc_blsp1_uart0_apps_clk", &gcc, 154 }, + { "gcc_blsp2_ahb_clk", &gcc, 160 }, + { "gcc_blsp2_qup0_i2c_apps_clk", &gcc, 162 }, + { "gcc_blsp2_qup0_spi_apps_clk", &gcc, 163 }, + { "gcc_blsp2_uart0_apps_clk", &gcc, 164 }, + { "gcc_pcie_0_slv_axi_clk", &gcc, 168 }, + { "gcc_pcie_0_mstr_axi_clk", &gcc, 169 }, + { "gcc_pcie_0_cfg_ahb_clk", &gcc, 170 }, + { "gcc_pcie_0_aux_clk", &gcc, 171 }, + { "gcc_pcie_0_pipe_clk", &gcc, 172 }, + //{ "pcie0_pipe_clk", &gcc, 173, 1 }, + { "qpic_clk", &gcc, 192 }, + { "gcc_pdm_ahb_clk", &gcc, 208 }, + { "gcc_pdm2_clk", &gcc, 210 }, + { "gcc_pwm0_xo512_clk", &gcc, 211 }, + { "gcc_pwm1_xo512_clk", &gcc, 212 }, + { "gcc_pwm2_xo512_clk", &gcc, 213 }, + { "gcc_prng_ahb_clk", &gcc, 216 }, + { "gcc_geni_ir_s_clk", &gcc, 238 }, + { "gcc_boot_rom_ahb_clk", &gcc, 248 }, + { "ce1_clk", &gcc, 312 }, + { "bimc_clk", &gcc, 346 }, + //{ "bimc_fsm_ddr_clk", &gcc, 350, 1 }, + { "gcc_apss_ahb_clk", &gcc, 360 }, + { "gcc_dcc_clk", &gcc, 441 }, + { "gcc_oxili_gfx3d_clk", &gcc, 490 }, + { "gcc_oxili_ahb_clk", &gcc, 491 }, + { "gcc_mdss_hdmi_pclk_clk", &gcc, 497 }, + { "gcc_mdss_hdmi_app_clk", &gcc, 498 }, + { "gcc_mdss_ahb_clk", &gcc, 502 }, + { "gcc_mdss_axi_clk", &gcc, 503 }, + { "gcc_mdss_pclk0_clk", &gcc, 504 }, + { "gcc_mdss_mdp_clk", &gcc, 505 }, + { "gcc_mdss_vsync_clk", &gcc, 507 }, + { "gcc_mdss_byte0_clk", &gcc, 508 }, + { "gcc_mdss_esc0_clk", &gcc, 509 }, {} }; diff --git a/sdm845.c b/sdm845.c index f734ffd..8abade1 100644 --- a/sdm845.c +++ b/sdm845.c @@ -61,6 +61,7 @@ static struct debug_mux gcc = { .div_reg = GCC_DEBUG_POST_DIV, .div_mask = 0xf, + .div_val = 4, .xo_div4_reg = GCC_XO_DIV4_CBCR, .debug_ctl_reg = GCC_DEBUG_CTL, @@ -140,252 +141,252 @@ static struct debug_mux video_cc = { }; static struct measure_clk sdm845_clocks[] = { - { "measure_only_snoc_clk", &gcc, 7, 4 }, - { "gcc_sys_noc_cpuss_ahb_clk", &gcc, 12, 4 }, - { "measure_only_cnoc_clk", &gcc, 21, 4 }, - { "gcc_cfg_noc_usb3_prim_axi_clk", &gcc, 29, 4 }, - { "gcc_cfg_noc_usb3_sec_axi_clk", &gcc, 30, 4 }, - { "gcc_aggre_noc_pcie_tbu_clk", &gcc, 45, 4 }, - { "gcc_video_ahb_clk", &gcc, 57, 4 }, - { "gcc_camera_ahb_clk", &gcc, 58, 4 }, - { "gcc_disp_ahb_clk", &gcc, 59, 4 }, - { "gcc_qmip_video_ahb_clk", &gcc, 60, 4 }, - { "gcc_qmip_camera_ahb_clk", &gcc, 61, 4 }, - { "gcc_qmip_disp_ahb_clk", &gcc, 62, 4 }, - { "gcc_video_axi_clk", &gcc, 63, 4 }, - { "gcc_camera_axi_clk", &gcc, 64, 4 }, - { "gcc_disp_axi_clk", &gcc, 65, 4 }, - { "gcc_video_xo_clk", &gcc, 66, 4 }, - { "gcc_camera_xo_clk", &gcc, 67, 4 }, - { "gcc_disp_xo_clk", &gcc, 68, 4 }, - { "cam_cc_mclk0_clk", &gcc, 70, 4, &cam_cc, 1, 1 }, - { "cam_cc_mclk1_clk", &gcc, 70, 4, &cam_cc, 2, 1 }, - { "cam_cc_mclk2_clk", &gcc, 70, 4, &cam_cc, 3, 1 }, - { "cam_cc_mclk3_clk", &gcc, 70, 4, &cam_cc, 4, 1 }, - { "cam_cc_csi0phytimer_clk", &gcc, 70, 4, &cam_cc, 5, 1 }, - { "cam_cc_csiphy0_clk", &gcc, 70, 4, &cam_cc, 6, 1 }, - { "cam_cc_csi1phytimer_clk", &gcc, 70, 4, &cam_cc, 7, 1 }, - { "cam_cc_csiphy1_clk", &gcc, 70, 4, &cam_cc, 8, 1 }, - { "cam_cc_csi2phytimer_clk", &gcc, 70, 4, &cam_cc, 9, 1 }, - { "cam_cc_csiphy2_clk", &gcc, 70, 4, &cam_cc, 10, 1 }, - { "cam_cc_bps_clk", &gcc, 70, 4, &cam_cc, 11, 1 }, - { "cam_cc_bps_axi_clk", &gcc, 70, 4, &cam_cc, 12, 1 }, - { "cam_cc_bps_areg_clk", &gcc, 70, 4, &cam_cc, 13, 1 }, - { "cam_cc_bps_ahb_clk", &gcc, 70, 4, &cam_cc, 14, 1 }, - { "cam_cc_ipe_0_clk", &gcc, 70, 4, &cam_cc, 15, 1 }, - { "cam_cc_ipe_0_axi_clk", &gcc, 70, 4, &cam_cc, 16, 1 }, - { "cam_cc_ipe_0_areg_clk", &gcc, 70, 4, &cam_cc, 17, 1 }, - { "cam_cc_ipe_0_ahb_clk", &gcc, 70, 4, &cam_cc, 18, 1 }, - { "cam_cc_ipe_1_clk", &gcc, 70, 4, &cam_cc, 19, 1 }, - { "cam_cc_ipe_1_axi_clk", &gcc, 70, 4, &cam_cc, 20, 1 }, - { "cam_cc_ipe_1_areg_clk", &gcc, 70, 4, &cam_cc, 21, 1 }, - { "cam_cc_ipe_1_ahb_clk", &gcc, 70, 4, &cam_cc, 22, 1 }, - { "cam_cc_ife_0_clk", &gcc, 70, 4, &cam_cc, 23, 1 }, - { "cam_cc_ife_0_dsp_clk", &gcc, 70, 4, &cam_cc, 24, 1 }, - { "cam_cc_ife_0_csid_clk", &gcc, 70, 4, &cam_cc, 25, 1 }, - { "cam_cc_ife_0_cphy_rx_clk", &gcc, 70, 4, &cam_cc, 26, 1 }, - { "cam_cc_ife_0_axi_clk", &gcc, 70, 4, &cam_cc, 27, 1 }, - { "cam_cc_ife_1_clk", &gcc, 70, 4, &cam_cc, 29, 1 }, - { "cam_cc_ife_1_dsp_clk", &gcc, 70, 4, &cam_cc, 30, 1 }, - { "cam_cc_ife_1_csid_clk", &gcc, 70, 4, &cam_cc, 31, 1 }, - { "cam_cc_ife_1_cphy_rx_clk", &gcc, 70, 4, &cam_cc, 32, 1 }, - { "cam_cc_ife_1_axi_clk", &gcc, 70, 4, &cam_cc, 33, 1 }, - { "cam_cc_ife_lite_clk", &gcc, 70, 4, &cam_cc, 34, 1 }, - { "cam_cc_ife_lite_csid_clk", &gcc, 70, 4, &cam_cc, 35, 1 }, - { "cam_cc_ife_lite_cphy_rx_clk", &gcc, 70, 4, &cam_cc, 36, 1 }, - { "cam_cc_jpeg_clk", &gcc, 70, 4, &cam_cc, 37, 1 }, - { "cam_cc_icp_clk", &gcc, 70, 4, &cam_cc, 38, 1 }, - { "cam_cc_fd_core_clk", &gcc, 70, 4, &cam_cc, 40, 1 }, - { "cam_cc_fd_core_uar_clk", &gcc, 70, 4, &cam_cc, 41, 1 }, - { "cam_cc_cci_clk", &gcc, 70, 4, &cam_cc, 42, 1 }, - { "cam_cc_lrme_clk", &gcc, 70, 4, &cam_cc, 43, 1 }, - { "cam_cc_cpas_ahb_clk", &gcc, 70, 4, &cam_cc, 44, 1 }, - { "cam_cc_camnoc_axi_clk", &gcc, 70, 4, &cam_cc, 45, 1 }, - { "cam_cc_soc_ahb_clk", &gcc, 70, 4, &cam_cc, 46, 1 }, - { "cam_cc_icp_atb_clk", &gcc, 70, 4, &cam_cc, 47, 1 }, - { "cam_cc_icp_cti_clk", &gcc, 70, 4, &cam_cc, 48, 1 }, - { "cam_cc_icp_ts_clk", &gcc, 70, 4, &cam_cc, 49, 1 }, - { "cam_cc_icp_apb_clk", &gcc, 70, 4, &cam_cc, 50, 1 }, - { "cam_cc_sys_tmr_clk", &gcc, 70, 4, &cam_cc, 51, 1 }, - { "cam_cc_camnoc_atb_clk", &gcc, 70, 4, &cam_cc, 52, 1 }, - { "cam_cc_csiphy3_clk", &gcc, 70, 4, &cam_cc, 54, 1 }, - { "disp_cc_mdss_pclk0_clk", &gcc, 71, 4, &disp_cc, 1, 1 }, - { "disp_cc_mdss_pclk1_clk", &gcc, 71, 4, &disp_cc, 2, 1 }, - { "disp_cc_mdss_mdp_clk", &gcc, 71, 4, &disp_cc, 3, 1 }, - { "disp_cc_mdss_rot_clk", &gcc, 71, 4, &disp_cc, 4, 1 }, - { "disp_cc_mdss_mdp_lut_clk", &gcc, 71, 4, &disp_cc, 5, 1 }, - { "disp_cc_mdss_vsync_clk", &gcc, 71, 4, &disp_cc, 6, 1 }, - { "disp_cc_mdss_byte0_clk", &gcc, 71, 4, &disp_cc, 7, 1 }, - { "disp_cc_mdss_byte0_intf_clk", &gcc, 71, 4, &disp_cc, 8, 1 }, - { "disp_cc_mdss_byte1_clk", &gcc, 71, 4, &disp_cc, 9, 1 }, - { "disp_cc_mdss_byte1_intf_clk", &gcc, 71, 4, &disp_cc, 10, 1 }, - { "disp_cc_mdss_esc0_clk", &gcc, 71, 4, &disp_cc, 11, 1 }, - { "disp_cc_mdss_esc1_clk", &gcc, 71, 4, &disp_cc, 12, 1 }, - { "disp_cc_mdss_dp_link_clk", &gcc, 71, 4, &disp_cc, 13, 1 }, - { "disp_cc_mdss_dp_link_intf_clk", &gcc, 71, 4, &disp_cc, 14, 1 }, - { "disp_cc_mdss_dp_crypto_clk", &gcc, 71, 4, &disp_cc, 15, 1 }, - { "disp_cc_mdss_dp_pixel_clk", &gcc, 71, 4, &disp_cc, 16, 1 }, - { "disp_cc_mdss_dp_pixel1_clk", &gcc, 71, 4, &disp_cc, 17, 1 }, - { "disp_cc_mdss_dp_aux_clk", &gcc, 71, 4, &disp_cc, 18, 1 }, - { "disp_cc_mdss_ahb_clk", &gcc, 71, 4, &disp_cc, 19, 1 }, - { "disp_cc_mdss_axi_clk", &gcc, 71, 4, &disp_cc, 20, 1 }, - { "disp_cc_mdss_qdss_at_clk", &gcc, 71, 4, &disp_cc, 21, 1 }, - { "disp_cc_mdss_qdss_tsctr_div8_clk", &gcc, 71, 4, &disp_cc, 22, 1 }, - { "disp_cc_mdss_rscc_ahb_clk", &gcc, 71, 4, &disp_cc, 23, 1 }, - { "disp_cc_mdss_rscc_vsync_clk", &gcc, 71, 4, &disp_cc, 24, 1 }, - { "video_cc_venus_ctl_core_clk", &gcc, 72, 4, &video_cc, 1, 1 }, - { "video_cc_vcodec0_core_clk", &gcc, 72, 4, &video_cc, 2, 1 }, - { "video_cc_vcodec1_core_clk", &gcc, 72, 4, &video_cc, 3, 1 }, - { "video_cc_venus_ctl_axi_clk", &gcc, 72, 4, &video_cc, 4, 1 }, - { "video_cc_vcodec0_axi_clk", &gcc, 72, 4, &video_cc, 5, 1 }, - { "video_cc_vcodec1_axi_clk", &gcc, 72, 4, &video_cc, 6, 1 }, - { "video_cc_qdss_trig_clk", &gcc, 72, 4, &video_cc, 7, 1 }, - { "video_cc_apb_clk", &gcc, 72, 4, &video_cc, 8, 1 }, - { "video_cc_venus_ahb_clk", &gcc, 72, 4, &video_cc, 9, 1 }, - { "video_cc_qdss_tsctr_div8_clk", &gcc, 72, 4, &video_cc, 10, 1 }, - { "video_cc_at_clk", &gcc, 72, 4, &video_cc, 11, 1 }, - { "gcc_disp_gpll0_clk_src", &gcc, 76, 4 }, - { "gcc_disp_gpll0_div_clk_src", &gcc, 77, 4 }, - { "gcc_usb30_prim_master_clk", &gcc, 95, 4 }, - { "gcc_usb30_prim_sleep_clk", &gcc, 96, 4 }, - { "gcc_usb30_prim_mock_utmi_clk", &gcc, 97, 4 }, - { "gcc_usb3_prim_phy_aux_clk", &gcc, 98, 4 }, - { "gcc_usb3_prim_phy_com_aux_clk", &gcc, 99, 4 }, - { "gcc_usb3_prim_phy_pipe_clk", &gcc, 100, 4 }, - { "gcc_usb30_sec_master_clk", &gcc, 101, 4 }, - { "gcc_usb30_sec_sleep_clk", &gcc, 102, 4 }, - { "gcc_usb30_sec_mock_utmi_clk", &gcc, 103, 4 }, - { "gcc_usb3_sec_phy_aux_clk", &gcc, 104, 4 }, - { "gcc_usb3_sec_phy_com_aux_clk", &gcc, 105, 4 }, - { "gcc_usb3_sec_phy_pipe_clk", &gcc, 106, 4 }, - { "gcc_usb_phy_cfg_ahb2phy_clk", &gcc, 111, 4 }, - { "gcc_sdcc2_apps_clk", &gcc, 112, 4 }, - { "gcc_sdcc2_ahb_clk", &gcc, 113, 4 }, - { "gcc_sdcc4_apps_clk", &gcc, 114, 4 }, - { "gcc_sdcc4_ahb_clk", &gcc, 115, 4 }, - { "gcc_qupv3_wrap_0_m_ahb_clk", &gcc, 116, 4 }, - { "gcc_qupv3_wrap_0_s_ahb_clk", &gcc, 117, 4 }, - { "gcc_qupv3_wrap0_core_clk", &gcc, 118, 4 }, - { "gcc_qupv3_wrap0_core_2x_clk", &gcc, 119, 4 }, - { "gcc_qupv3_wrap0_s0_clk", &gcc, 120, 4 }, - { "gcc_qupv3_wrap0_s1_clk", &gcc, 121, 4 }, - { "gcc_qupv3_wrap0_s2_clk", &gcc, 122, 4 }, - { "gcc_qupv3_wrap0_s3_clk", &gcc, 123, 4 }, - { "gcc_qupv3_wrap0_s4_clk", &gcc, 124, 4 }, - { "gcc_qupv3_wrap0_s5_clk", &gcc, 125, 4 }, - { "gcc_qupv3_wrap0_s6_clk", &gcc, 126, 4 }, - { "gcc_qupv3_wrap0_s7_clk", &gcc, 127, 4 }, - { "gcc_qupv3_wrap1_core_2x_clk", &gcc, 128, 4 }, - { "gcc_qupv3_wrap1_core_clk", &gcc, 129, 4 }, - { "gcc_qupv3_wrap_1_m_ahb_clk", &gcc, 130, 4 }, - { "gcc_qupv3_wrap_1_s_ahb_clk", &gcc, 131, 4 }, - { "gcc_qupv3_wrap1_s0_clk", &gcc, 132, 4 }, - { "gcc_qupv3_wrap1_s1_clk", &gcc, 133, 4 }, - { "gcc_qupv3_wrap1_s2_clk", &gcc, 134, 4 }, - { "gcc_qupv3_wrap1_s3_clk", &gcc, 135, 4 }, - { "gcc_qupv3_wrap1_s4_clk", &gcc, 136, 4 }, - { "gcc_qupv3_wrap1_s5_clk", &gcc, 137, 4 }, - { "gcc_qupv3_wrap1_s6_clk", &gcc, 138, 4 }, - { "gcc_qupv3_wrap1_s7_clk", &gcc, 139, 4 }, - { "gcc_pdm_ahb_clk", &gcc, 140, 4 }, - { "gcc_pdm_xo4_clk", &gcc, 141, 4 }, - { "gcc_pdm2_clk", &gcc, 142, 4 }, - { "gcc_prng_ahb_clk", &gcc, 143, 4 }, - { "gcc_tsif_ahb_clk", &gcc, 144, 4 }, - { "gcc_tsif_ref_clk", &gcc, 145, 4 }, - { "gcc_tsif_inactivity_timers_clk", &gcc, 146, 4 }, - { "gcc_boot_rom_ahb_clk", &gcc, 148, 4 }, - { "gcc_ce1_clk", &gcc, 167, 4 }, - { "gcc_ce1_axi_clk", &gcc, 168, 4 }, - { "gcc_ce1_ahb_clk", &gcc, 169, 4 }, - { "gcc_ddrss_gpu_axi_clk", &gcc, 187, 4 }, - { "measure_only_bimc_clk", &gcc, 194, 4 }, - { "gcc_cpuss_ahb_clk", &gcc, 206, 4 }, - { "gcc_cpuss_gnoc_clk", &gcc, 207, 4 }, - { "gcc_cpuss_rbcpr_clk", &gcc, 208, 4 }, - { "gcc_cpuss_dvm_bus_clk", &gcc, 211, 4 }, - { "pwrcl_clk", &gcc, 214, 4, &cpu, 68, 1, 16 }, - { "perfcl_clk", &gcc, 214, 4, &cpu, 69, 1, 16 }, - { "l3_clk", &gcc, 214, 4, &cpu, 70, 1, 16 }, - { "gcc_gp1_clk", &gcc, 222, 4 }, - { "gcc_gp2_clk", &gcc, 223, 4 }, - { "gcc_gp3_clk", &gcc, 224, 4 }, - { "gcc_pcie_0_slv_q2a_axi_clk", &gcc, 225, 4 }, - { "gcc_pcie_0_slv_axi_clk", &gcc, 226, 4 }, - { "gcc_pcie_0_mstr_axi_clk", &gcc, 227, 4 }, - { "gcc_pcie_0_cfg_ahb_clk", &gcc, 228, 4 }, - { "gcc_pcie_0_aux_clk", &gcc, 229, 4 }, - { "gcc_pcie_0_pipe_clk", &gcc, 230, 4 }, - { "gcc_pcie_1_slv_q2a_axi_clk", &gcc, 232, 4 }, - { "gcc_pcie_1_slv_axi_clk", &gcc, 233, 4 }, - { "gcc_pcie_1_mstr_axi_clk", &gcc, 234, 4 }, - { "gcc_pcie_1_cfg_ahb_clk", &gcc, 235, 4 }, - { "gcc_pcie_1_aux_clk", &gcc, 236, 4 }, - { "gcc_pcie_1_pipe_clk", &gcc, 237, 4 }, - { "gcc_pcie_phy_aux_clk", &gcc, 239, 4 }, - { "gcc_ufs_card_axi_clk", &gcc, 240, 4 }, - { "gcc_ufs_card_ahb_clk", &gcc, 241, 4 }, - { "gcc_ufs_card_tx_symbol_0_clk", &gcc, 242, 4 }, - { "gcc_ufs_card_rx_symbol_0_clk", &gcc, 243, 4 }, - { "gcc_ufs_card_unipro_core_clk", &gcc, 246, 4 }, - { "gcc_ufs_card_ice_core_clk", &gcc, 247, 4 }, - { "gcc_ufs_card_phy_aux_clk", &gcc, 248, 4 }, - { "gcc_ufs_card_rx_symbol_1_clk", &gcc, 249, 4 }, - { "gcc_ufs_phy_axi_clk", &gcc, 251, 4 }, - { "gcc_ufs_phy_ahb_clk", &gcc, 252, 4 }, - { "gcc_ufs_phy_tx_symbol_0_clk", &gcc, 253, 4 }, - { "gcc_ufs_phy_rx_symbol_0_clk", &gcc, 254, 4 }, - { "gcc_ufs_phy_unipro_core_clk", &gcc, 257, 4 }, - { "gcc_ufs_phy_ice_core_clk", &gcc, 258, 4 }, - { "gcc_ufs_phy_phy_aux_clk", &gcc, 259, 4 }, - { "gcc_ufs_phy_rx_symbol_1_clk", &gcc, 260, 4 }, - { "gcc_vddcx_vs_clk", &gcc, 268, 4 }, - { "gcc_vddmx_vs_clk", &gcc, 269, 4 }, - { "gcc_vdda_vs_clk", &gcc, 270, 4 }, - { "gcc_vs_ctrl_clk", &gcc, 271, 4 }, - { "gcc_vs_ctrl_ahb_clk", &gcc, 272, 4 }, - { "gcc_mss_vs_clk", &gcc, 273, 4 }, - { "gcc_gpu_vs_clk", &gcc, 274, 4 }, - { "gcc_apc_vs_clk", &gcc, 275, 4 }, - { "gcc_aggre_usb3_prim_axi_clk", &gcc, 283, 4 }, - { "gcc_aggre_usb3_sec_axi_clk", &gcc, 284, 4 }, - { "gcc_aggre_ufs_phy_axi_clk", &gcc, 285, 4 }, - { "gcc_aggre_ufs_card_axi_clk", &gcc, 286, 4 }, - { "measure_only_ipa_2x_clk", &gcc, 296, 4 }, - { "gcc_mss_cfg_ahb_clk", &gcc, 301, 4 }, - { "gcc_mss_mfab_axis_clk", &gcc, 302, 4 }, - { "gcc_mss_axis2_clk", &gcc, 303, 4 }, - { "gcc_mss_gpll0_div_clk_src", &gcc, 307, 4 }, - { "gcc_mss_snoc_axi_clk", &gcc, 308, 4 }, - { "gcc_mss_q6_memnoc_axi_clk", &gcc, 309, 4 }, - { "gcc_gpu_cfg_ahb_clk", &gcc, 322, 4 }, - { "gpu_cc_cxo_clk", &gcc, 324, 4, &gpu_cc, 10, 1 }, - { "gpu_cc_cxo_aon_clk", &gcc, 324, 4, &gpu_cc, 11, 1 }, - { "gpu_cc_gx_gfx3d_clk", &gcc, 324, 4, &gpu_cc, 12, 1 }, - { "gpu_cc_gx_vsense_clk", &gcc, 324, 4, &gpu_cc, 13, 1 }, - { "gpu_cc_gx_qdss_tsctr_clk", &gcc, 324, 4, &gpu_cc, 14, 1 }, - { "gpu_cc_gx_gmu_clk", &gcc, 324, 4, &gpu_cc, 16, 1 }, - { "gpu_cc_crc_ahb_clk", &gcc, 324, 4, &gpu_cc, 18, 1 }, - { "gpu_cc_cx_qdss_at_clk", &gcc, 324, 4, &gpu_cc, 19, 1 }, - { "gpu_cc_cx_qdss_tsctr_clk", &gcc, 324, 4, &gpu_cc, 20, 1 }, - { "gpu_cc_cx_apb_clk", &gcc, 324, 4, &gpu_cc, 21, 1 }, - { "gpu_cc_cx_snoc_dvm_clk", &gcc, 324, 4, &gpu_cc, 22, 1 }, - { "gpu_cc_sleep_clk", &gcc, 324, 4, &gpu_cc, 23, 1 }, - { "gpu_cc_cx_qdss_trig_clk", &gcc, 324, 4, &gpu_cc, 24, 1 }, - { "gpu_cc_cx_gmu_clk", &gcc, 324, 4, &gpu_cc, 25, 1 }, - { "gpu_cc_cx_gfx3d_clk", &gcc, 324, 4, &gpu_cc, 26, 1 }, - { "gpu_cc_cx_gfx3d_slv_clk", &gcc, 324, 4, &gpu_cc, 27, 1 }, - { "gpu_cc_rbcpr_clk", &gcc, 324, 4, &gpu_cc, 28, 1 }, - { "gpu_cc_rbcpr_ahb_clk", &gcc, 324, 4, &gpu_cc, 29, 1 }, - { "gpu_cc_acd_cxo_clk", &gcc, 324, 4, &gpu_cc, 31, 1 }, - { "gcc_gpu_memnoc_gfx_clk", &gcc, 325, 4 }, - { "gcc_gpu_snoc_dvm_gfx_clk", &gcc, 327, 4 }, - { "gcc_gpu_gpll0_clk_src", &gcc, 328, 4 }, - { "gcc_gpu_gpll0_div_clk_src", &gcc, 329, 4 }, - { "gcc_sdcc1_apps_clk", &gcc, 347, 4 }, - { "gcc_sdcc1_ahb_clk", &gcc, 348, 4 }, - { "gcc_sdcc1_ice_core_clk", &gcc, 349, 4 }, - { "gcc_pcie_phy_refgen_clk", &gcc, 352, 4 }, + { "measure_only_snoc_clk", &gcc, 7 }, + { "gcc_sys_noc_cpuss_ahb_clk", &gcc, 12 }, + { "measure_only_cnoc_clk", &gcc, 21 }, + { "gcc_cfg_noc_usb3_prim_axi_clk", &gcc, 29 }, + { "gcc_cfg_noc_usb3_sec_axi_clk", &gcc, 30 }, + { "gcc_aggre_noc_pcie_tbu_clk", &gcc, 45 }, + { "gcc_video_ahb_clk", &gcc, 57 }, + { "gcc_camera_ahb_clk", &gcc, 58 }, + { "gcc_disp_ahb_clk", &gcc, 59 }, + { "gcc_qmip_video_ahb_clk", &gcc, 60 }, + { "gcc_qmip_camera_ahb_clk", &gcc, 61 }, + { "gcc_qmip_disp_ahb_clk", &gcc, 62 }, + { "gcc_video_axi_clk", &gcc, 63 }, + { "gcc_camera_axi_clk", &gcc, 64 }, + { "gcc_disp_axi_clk", &gcc, 65 }, + { "gcc_video_xo_clk", &gcc, 66 }, + { "gcc_camera_xo_clk", &gcc, 67 }, + { "gcc_disp_xo_clk", &gcc, 68 }, + { "cam_cc_mclk0_clk", &gcc, 70, &cam_cc, 1 }, + { "cam_cc_mclk1_clk", &gcc, 70, &cam_cc, 2 }, + { "cam_cc_mclk2_clk", &gcc, 70, &cam_cc, 3 }, + { "cam_cc_mclk3_clk", &gcc, 70, &cam_cc, 4 }, + { "cam_cc_csi0phytimer_clk", &gcc, 70, &cam_cc, 5 }, + { "cam_cc_csiphy0_clk", &gcc, 70, &cam_cc, 6 }, + { "cam_cc_csi1phytimer_clk", &gcc, 70, &cam_cc, 7 }, + { "cam_cc_csiphy1_clk", &gcc, 70, &cam_cc, 8 }, + { "cam_cc_csi2phytimer_clk", &gcc, 70, &cam_cc, 9 }, + { "cam_cc_csiphy2_clk", &gcc, 70, &cam_cc, 10 }, + { "cam_cc_bps_clk", &gcc, 70, &cam_cc, 11 }, + { "cam_cc_bps_axi_clk", &gcc, 70, &cam_cc, 12 }, + { "cam_cc_bps_areg_clk", &gcc, 70, &cam_cc, 13 }, + { "cam_cc_bps_ahb_clk", &gcc, 70, &cam_cc, 14 }, + { "cam_cc_ipe_0_clk", &gcc, 70, &cam_cc, 15 }, + { "cam_cc_ipe_0_axi_clk", &gcc, 70, &cam_cc, 16 }, + { "cam_cc_ipe_0_areg_clk", &gcc, 70, &cam_cc, 17 }, + { "cam_cc_ipe_0_ahb_clk", &gcc, 70, &cam_cc, 18 }, + { "cam_cc_ipe_1_clk", &gcc, 70, &cam_cc, 19 }, + { "cam_cc_ipe_1_axi_clk", &gcc, 70, &cam_cc, 20 }, + { "cam_cc_ipe_1_areg_clk", &gcc, 70, &cam_cc, 21 }, + { "cam_cc_ipe_1_ahb_clk", &gcc, 70, &cam_cc, 22 }, + { "cam_cc_ife_0_clk", &gcc, 70, &cam_cc, 23 }, + { "cam_cc_ife_0_dsp_clk", &gcc, 70, &cam_cc, 24 }, + { "cam_cc_ife_0_csid_clk", &gcc, 70, &cam_cc, 25 }, + { "cam_cc_ife_0_cphy_rx_clk", &gcc, 70, &cam_cc, 26 }, + { "cam_cc_ife_0_axi_clk", &gcc, 70, &cam_cc, 27 }, + { "cam_cc_ife_1_clk", &gcc, 70, &cam_cc, 29 }, + { "cam_cc_ife_1_dsp_clk", &gcc, 70, &cam_cc, 30 }, + { "cam_cc_ife_1_csid_clk", &gcc, 70, &cam_cc, 31 }, + { "cam_cc_ife_1_cphy_rx_clk", &gcc, 70, &cam_cc, 32 }, + { "cam_cc_ife_1_axi_clk", &gcc, 70, &cam_cc, 33 }, + { "cam_cc_ife_lite_clk", &gcc, 70, &cam_cc, 34 }, + { "cam_cc_ife_lite_csid_clk", &gcc, 70, &cam_cc, 35 }, + { "cam_cc_ife_lite_cphy_rx_clk", &gcc, 70, &cam_cc, 36 }, + { "cam_cc_jpeg_clk", &gcc, 70, &cam_cc, 37 }, + { "cam_cc_icp_clk", &gcc, 70, &cam_cc, 38 }, + { "cam_cc_fd_core_clk", &gcc, 70, &cam_cc, 40 }, + { "cam_cc_fd_core_uar_clk", &gcc, 70, &cam_cc, 41 }, + { "cam_cc_cci_clk", &gcc, 70, &cam_cc, 42 }, + { "cam_cc_lrme_clk", &gcc, 70, &cam_cc, 43 }, + { "cam_cc_cpas_ahb_clk", &gcc, 70, &cam_cc, 44 }, + { "cam_cc_camnoc_axi_clk", &gcc, 70, &cam_cc, 45 }, + { "cam_cc_soc_ahb_clk", &gcc, 70, &cam_cc, 46 }, + { "cam_cc_icp_atb_clk", &gcc, 70, &cam_cc, 47 }, + { "cam_cc_icp_cti_clk", &gcc, 70, &cam_cc, 48 }, + { "cam_cc_icp_ts_clk", &gcc, 70, &cam_cc, 49 }, + { "cam_cc_icp_apb_clk", &gcc, 70, &cam_cc, 50 }, + { "cam_cc_sys_tmr_clk", &gcc, 70, &cam_cc, 51 }, + { "cam_cc_camnoc_atb_clk", &gcc, 70, &cam_cc, 52 }, + { "cam_cc_csiphy3_clk", &gcc, 70, &cam_cc, 54 }, + { "disp_cc_mdss_pclk0_clk", &gcc, 71, &disp_cc, 1 }, + { "disp_cc_mdss_pclk1_clk", &gcc, 71, &disp_cc, 2 }, + { "disp_cc_mdss_mdp_clk", &gcc, 71, &disp_cc, 3 }, + { "disp_cc_mdss_rot_clk", &gcc, 71, &disp_cc, 4 }, + { "disp_cc_mdss_mdp_lut_clk", &gcc, 71, &disp_cc, 5 }, + { "disp_cc_mdss_vsync_clk", &gcc, 71, &disp_cc, 6 }, + { "disp_cc_mdss_byte0_clk", &gcc, 71, &disp_cc, 7 }, + { "disp_cc_mdss_byte0_intf_clk", &gcc, 71, &disp_cc, 8 }, + { "disp_cc_mdss_byte1_clk", &gcc, 71, &disp_cc, 9 }, + { "disp_cc_mdss_byte1_intf_clk", &gcc, 71, &disp_cc, 10 }, + { "disp_cc_mdss_esc0_clk", &gcc, 71, &disp_cc, 11 }, + { "disp_cc_mdss_esc1_clk", &gcc, 71, &disp_cc, 12 }, + { "disp_cc_mdss_dp_link_clk", &gcc, 71, &disp_cc, 13 }, + { "disp_cc_mdss_dp_link_intf_clk", &gcc, 71, &disp_cc, 14 }, + { "disp_cc_mdss_dp_crypto_clk", &gcc, 71, &disp_cc, 15 }, + { "disp_cc_mdss_dp_pixel_clk", &gcc, 71, &disp_cc, 16 }, + { "disp_cc_mdss_dp_pixel1_clk", &gcc, 71, &disp_cc, 17 }, + { "disp_cc_mdss_dp_aux_clk", &gcc, 71, &disp_cc, 18 }, + { "disp_cc_mdss_ahb_clk", &gcc, 71, &disp_cc, 19 }, + { "disp_cc_mdss_axi_clk", &gcc, 71, &disp_cc, 20 }, + { "disp_cc_mdss_qdss_at_clk", &gcc, 71, &disp_cc, 21 }, + { "disp_cc_mdss_qdss_tsctr_div8_clk", &gcc, 71, &disp_cc, 22 }, + { "disp_cc_mdss_rscc_ahb_clk", &gcc, 71, &disp_cc, 23 }, + { "disp_cc_mdss_rscc_vsync_clk", &gcc, 71, &disp_cc, 24 }, + { "video_cc_venus_ctl_core_clk", &gcc, 72, &video_cc, 1 }, + { "video_cc_vcodec0_core_clk", &gcc, 72, &video_cc, 2 }, + { "video_cc_vcodec1_core_clk", &gcc, 72, &video_cc, 3 }, + { "video_cc_venus_ctl_axi_clk", &gcc, 72, &video_cc, 4 }, + { "video_cc_vcodec0_axi_clk", &gcc, 72, &video_cc, 5 }, + { "video_cc_vcodec1_axi_clk", &gcc, 72, &video_cc, 6 }, + { "video_cc_qdss_trig_clk", &gcc, 72, &video_cc, 7 }, + { "video_cc_apb_clk", &gcc, 72, &video_cc, 8 }, + { "video_cc_venus_ahb_clk", &gcc, 72, &video_cc, 9 }, + { "video_cc_qdss_tsctr_div8_clk", &gcc, 72, &video_cc, 10 }, + { "video_cc_at_clk", &gcc, 72, &video_cc, 11 }, + { "gcc_disp_gpll0_clk_src", &gcc, 76 }, + { "gcc_disp_gpll0_div_clk_src", &gcc, 77 }, + { "gcc_usb30_prim_master_clk", &gcc, 95 }, + { "gcc_usb30_prim_sleep_clk", &gcc, 96 }, + { "gcc_usb30_prim_mock_utmi_clk", &gcc, 97 }, + { "gcc_usb3_prim_phy_aux_clk", &gcc, 98 }, + { "gcc_usb3_prim_phy_com_aux_clk", &gcc, 99 }, + { "gcc_usb3_prim_phy_pipe_clk", &gcc, 100 }, + { "gcc_usb30_sec_master_clk", &gcc, 101 }, + { "gcc_usb30_sec_sleep_clk", &gcc, 102 }, + { "gcc_usb30_sec_mock_utmi_clk", &gcc, 103 }, + { "gcc_usb3_sec_phy_aux_clk", &gcc, 104 }, + { "gcc_usb3_sec_phy_com_aux_clk", &gcc, 105 }, + { "gcc_usb3_sec_phy_pipe_clk", &gcc, 106 }, + { "gcc_usb_phy_cfg_ahb2phy_clk", &gcc, 111 }, + { "gcc_sdcc2_apps_clk", &gcc, 112 }, + { "gcc_sdcc2_ahb_clk", &gcc, 113 }, + { "gcc_sdcc4_apps_clk", &gcc, 114 }, + { "gcc_sdcc4_ahb_clk", &gcc, 115 }, + { "gcc_qupv3_wrap_0_m_ahb_clk", &gcc, 116 }, + { "gcc_qupv3_wrap_0_s_ahb_clk", &gcc, 117 }, + { "gcc_qupv3_wrap0_core_clk", &gcc, 118 }, + { "gcc_qupv3_wrap0_core_2x_clk", &gcc, 119 }, + { "gcc_qupv3_wrap0_s0_clk", &gcc, 120 }, + { "gcc_qupv3_wrap0_s1_clk", &gcc, 121 }, + { "gcc_qupv3_wrap0_s2_clk", &gcc, 122 }, + { "gcc_qupv3_wrap0_s3_clk", &gcc, 123 }, + { "gcc_qupv3_wrap0_s4_clk", &gcc, 124 }, + { "gcc_qupv3_wrap0_s5_clk", &gcc, 125 }, + { "gcc_qupv3_wrap0_s6_clk", &gcc, 126 }, + { "gcc_qupv3_wrap0_s7_clk", &gcc, 127 }, + { "gcc_qupv3_wrap1_core_2x_clk", &gcc, 128 }, + { "gcc_qupv3_wrap1_core_clk", &gcc, 129 }, + { "gcc_qupv3_wrap_1_m_ahb_clk", &gcc, 130 }, + { "gcc_qupv3_wrap_1_s_ahb_clk", &gcc, 131 }, + { "gcc_qupv3_wrap1_s0_clk", &gcc, 132 }, + { "gcc_qupv3_wrap1_s1_clk", &gcc, 133 }, + { "gcc_qupv3_wrap1_s2_clk", &gcc, 134 }, + { "gcc_qupv3_wrap1_s3_clk", &gcc, 135 }, + { "gcc_qupv3_wrap1_s4_clk", &gcc, 136 }, + { "gcc_qupv3_wrap1_s5_clk", &gcc, 137 }, + { "gcc_qupv3_wrap1_s6_clk", &gcc, 138 }, + { "gcc_qupv3_wrap1_s7_clk", &gcc, 139 }, + { "gcc_pdm_ahb_clk", &gcc, 140 }, + { "gcc_pdm_xo4_clk", &gcc, 141 }, + { "gcc_pdm2_clk", &gcc, 142 }, + { "gcc_prng_ahb_clk", &gcc, 143 }, + { "gcc_tsif_ahb_clk", &gcc, 144 }, + { "gcc_tsif_ref_clk", &gcc, 145 }, + { "gcc_tsif_inactivity_timers_clk", &gcc, 146 }, + { "gcc_boot_rom_ahb_clk", &gcc, 148 }, + { "gcc_ce1_clk", &gcc, 167 }, + { "gcc_ce1_axi_clk", &gcc, 168 }, + { "gcc_ce1_ahb_clk", &gcc, 169 }, + { "gcc_ddrss_gpu_axi_clk", &gcc, 187 }, + { "measure_only_bimc_clk", &gcc, 194 }, + { "gcc_cpuss_ahb_clk", &gcc, 206 }, + { "gcc_cpuss_gnoc_clk", &gcc, 207 }, + { "gcc_cpuss_rbcpr_clk", &gcc, 208 }, + { "gcc_cpuss_dvm_bus_clk", &gcc, 211 }, + { "pwrcl_clk", &gcc, 214, &cpu, 68, 16 }, + { "perfcl_clk", &gcc, 214, &cpu, 69, 16 }, + { "l3_clk", &gcc, 214, &cpu, 70, 16 }, + { "gcc_gp1_clk", &gcc, 222 }, + { "gcc_gp2_clk", &gcc, 223 }, + { "gcc_gp3_clk", &gcc, 224 }, + { "gcc_pcie_0_slv_q2a_axi_clk", &gcc, 225 }, + { "gcc_pcie_0_slv_axi_clk", &gcc, 226 }, + { "gcc_pcie_0_mstr_axi_clk", &gcc, 227 }, + { "gcc_pcie_0_cfg_ahb_clk", &gcc, 228 }, + { "gcc_pcie_0_aux_clk", &gcc, 229 }, + { "gcc_pcie_0_pipe_clk", &gcc, 230 }, + { "gcc_pcie_1_slv_q2a_axi_clk", &gcc, 232 }, + { "gcc_pcie_1_slv_axi_clk", &gcc, 233 }, + { "gcc_pcie_1_mstr_axi_clk", &gcc, 234 }, + { "gcc_pcie_1_cfg_ahb_clk", &gcc, 235 }, + { "gcc_pcie_1_aux_clk", &gcc, 236 }, + { "gcc_pcie_1_pipe_clk", &gcc, 237 }, + { "gcc_pcie_phy_aux_clk", &gcc, 239 }, + { "gcc_ufs_card_axi_clk", &gcc, 240 }, + { "gcc_ufs_card_ahb_clk", &gcc, 241 }, + { "gcc_ufs_card_tx_symbol_0_clk", &gcc, 242 }, + { "gcc_ufs_card_rx_symbol_0_clk", &gcc, 243 }, + { "gcc_ufs_card_unipro_core_clk", &gcc, 246 }, + { "gcc_ufs_card_ice_core_clk", &gcc, 247 }, + { "gcc_ufs_card_phy_aux_clk", &gcc, 248 }, + { "gcc_ufs_card_rx_symbol_1_clk", &gcc, 249 }, + { "gcc_ufs_phy_axi_clk", &gcc, 251 }, + { "gcc_ufs_phy_ahb_clk", &gcc, 252 }, + { "gcc_ufs_phy_tx_symbol_0_clk", &gcc, 253 }, + { "gcc_ufs_phy_rx_symbol_0_clk", &gcc, 254 }, + { "gcc_ufs_phy_unipro_core_clk", &gcc, 257 }, + { "gcc_ufs_phy_ice_core_clk", &gcc, 258 }, + { "gcc_ufs_phy_phy_aux_clk", &gcc, 259 }, + { "gcc_ufs_phy_rx_symbol_1_clk", &gcc, 260 }, + { "gcc_vddcx_vs_clk", &gcc, 268 }, + { "gcc_vddmx_vs_clk", &gcc, 269 }, + { "gcc_vdda_vs_clk", &gcc, 270 }, + { "gcc_vs_ctrl_clk", &gcc, 271 }, + { "gcc_vs_ctrl_ahb_clk", &gcc, 272 }, + { "gcc_mss_vs_clk", &gcc, 273 }, + { "gcc_gpu_vs_clk", &gcc, 274 }, + { "gcc_apc_vs_clk", &gcc, 275 }, + { "gcc_aggre_usb3_prim_axi_clk", &gcc, 283 }, + { "gcc_aggre_usb3_sec_axi_clk", &gcc, 284 }, + { "gcc_aggre_ufs_phy_axi_clk", &gcc, 285 }, + { "gcc_aggre_ufs_card_axi_clk", &gcc, 286 }, + { "measure_only_ipa_2x_clk", &gcc, 296 }, + { "gcc_mss_cfg_ahb_clk", &gcc, 301 }, + { "gcc_mss_mfab_axis_clk", &gcc, 302 }, + { "gcc_mss_axis2_clk", &gcc, 303 }, + { "gcc_mss_gpll0_div_clk_src", &gcc, 307 }, + { "gcc_mss_snoc_axi_clk", &gcc, 308 }, + { "gcc_mss_q6_memnoc_axi_clk", &gcc, 309 }, + { "gcc_gpu_cfg_ahb_clk", &gcc, 322 }, + { "gpu_cc_cxo_clk", &gcc, 324, &gpu_cc, 10 }, + { "gpu_cc_cxo_aon_clk", &gcc, 324, &gpu_cc, 11 }, + { "gpu_cc_gx_gfx3d_clk", &gcc, 324, &gpu_cc, 12 }, + { "gpu_cc_gx_vsense_clk", &gcc, 324, &gpu_cc, 13 }, + { "gpu_cc_gx_qdss_tsctr_clk", &gcc, 324, &gpu_cc, 14 }, + { "gpu_cc_gx_gmu_clk", &gcc, 324, &gpu_cc, 16 }, + { "gpu_cc_crc_ahb_clk", &gcc, 324, &gpu_cc, 18 }, + { "gpu_cc_cx_qdss_at_clk", &gcc, 324, &gpu_cc, 19 }, + { "gpu_cc_cx_qdss_tsctr_clk", &gcc, 324, &gpu_cc, 20 }, + { "gpu_cc_cx_apb_clk", &gcc, 324, &gpu_cc, 21 }, + { "gpu_cc_cx_snoc_dvm_clk", &gcc, 324, &gpu_cc, 22 }, + { "gpu_cc_sleep_clk", &gcc, 324, &gpu_cc, 23 }, + { "gpu_cc_cx_qdss_trig_clk", &gcc, 324, &gpu_cc, 24 }, + { "gpu_cc_cx_gmu_clk", &gcc, 324, &gpu_cc, 25 }, + { "gpu_cc_cx_gfx3d_clk", &gcc, 324, &gpu_cc, 26 }, + { "gpu_cc_cx_gfx3d_slv_clk", &gcc, 324, &gpu_cc, 27 }, + { "gpu_cc_rbcpr_clk", &gcc, 324, &gpu_cc, 28 }, + { "gpu_cc_rbcpr_ahb_clk", &gcc, 324, &gpu_cc, 29 }, + { "gpu_cc_acd_cxo_clk", &gcc, 324, &gpu_cc, 31 }, + { "gcc_gpu_memnoc_gfx_clk", &gcc, 325 }, + { "gcc_gpu_snoc_dvm_gfx_clk", &gcc, 327 }, + { "gcc_gpu_gpll0_clk_src", &gcc, 328 }, + { "gcc_gpu_gpll0_div_clk_src", &gcc, 329 }, + { "gcc_sdcc1_apps_clk", &gcc, 347 }, + { "gcc_sdcc1_ahb_clk", &gcc, 348 }, + { "gcc_sdcc1_ice_core_clk", &gcc, 349 }, + { "gcc_pcie_phy_refgen_clk", &gcc, 352 }, {} }; diff --git a/sm8350.c b/sm8350.c index 6eec49e..58a4165 100644 --- a/sm8350.c +++ b/sm8350.c @@ -61,6 +61,7 @@ static struct debug_mux gcc = { .div_reg = 0x4, .div_mask = 0xf, + .div_val = 2, .xo_div4_reg = 0xc, .debug_ctl_reg = 0x38, @@ -79,6 +80,7 @@ static struct debug_mux cam_cc = { .div_reg = 0xd004, .div_mask = 0x3, + .div_val = 4, }; static struct debug_mux disp_cc = { @@ -93,6 +95,7 @@ static struct debug_mux disp_cc = { .div_reg = 0x5008, .div_mask = 0x3, + .div_val = 4, }; static struct debug_mux gpu_cc = { @@ -107,6 +110,7 @@ static struct debug_mux gpu_cc = { .div_reg = 0x10fc, .div_mask = 0xf, + .div_val = 2, }; static struct debug_mux video_cc = { @@ -121,6 +125,7 @@ static struct debug_mux video_cc = { .div_reg = 0xe9c, .div_mask = 0x7, + .div_val = 3, }; @@ -141,273 +146,273 @@ struct measure_clk { static struct measure_clk sm8350_clocks[] = { /* cam_cc_debug_mux is 0x4D */ - { "cam_cc_bps_ahb_clk", &gcc, 0x4D, 2, &cam_cc, 0x18, 4 }, - { "cam_cc_bps_areg_clk", &gcc, 0x4D, 2, &cam_cc, 0x17, 4 }, - { "cam_cc_bps_axi_clk", &gcc, 0x4D, 2, &cam_cc, 0x16, 4 }, - { "cam_cc_bps_clk", &gcc, 0x4D, 2, &cam_cc, 0x14, 4 }, - { "cam_cc_camnoc_axi_clk", &gcc, 0x4D, 2, &cam_cc, 0x3C, 4 }, - { "cam_cc_camnoc_dcd_xo_clk", &gcc, 0x4D, 2, &cam_cc, 0x3D, 4 }, - { "cam_cc_cci_0_clk", &gcc, 0x4D, 2, &cam_cc, 0x39, 4 }, - { "cam_cc_cci_1_clk", &gcc, 0x4D, 2, &cam_cc, 0x3A, 4 }, - { "cam_cc_core_ahb_clk", &gcc, 0x4D, 2, &cam_cc, 0x40, 4 }, - { "cam_cc_cpas_ahb_clk", &gcc, 0x4D, 2, &cam_cc, 0x3B, 4 }, - { "cam_cc_csi0phytimer_clk", &gcc, 0x4D, 2, &cam_cc, 0x8, 4 }, - { "cam_cc_csi1phytimer_clk", &gcc, 0x4D, 2, &cam_cc, 0xA, 4 }, - { "cam_cc_csi2phytimer_clk", &gcc, 0x4D, 2, &cam_cc, 0xC, 4 }, - { "cam_cc_csi3phytimer_clk", &gcc, 0x4D, 2, &cam_cc, 0xE, 4 }, - { "cam_cc_csi4phytimer_clk", &gcc, 0x4D, 2, &cam_cc, 0x10, 4 }, - { "cam_cc_csi5phytimer_clk", &gcc, 0x4D, 2, &cam_cc, 0x12, 4 }, - { "cam_cc_csiphy0_clk", &gcc, 0x4D, 2, &cam_cc, 0x9, 4 }, - { "cam_cc_csiphy1_clk", &gcc, 0x4D, 2, &cam_cc, 0xB, 4 }, - { "cam_cc_csiphy2_clk", &gcc, 0x4D, 2, &cam_cc, 0xD, 4 }, - { "cam_cc_csiphy3_clk", &gcc, 0x4D, 2, &cam_cc, 0xF, 4 }, - { "cam_cc_csiphy4_clk", &gcc, 0x4D, 2, &cam_cc, 0x11, 4 }, - { "cam_cc_csiphy5_clk", &gcc, 0x4D, 2, &cam_cc, 0x13, 4 }, - { "cam_cc_icp_ahb_clk", &gcc, 0x4D, 2, &cam_cc, 0x36, 4 }, - { "cam_cc_icp_clk", &gcc, 0x4D, 2, &cam_cc, 0x35, 4 }, - { "cam_cc_ife_0_ahb_clk", &gcc, 0x4D, 2, &cam_cc, 0x26, 4 }, - { "cam_cc_ife_0_areg_clk", &gcc, 0x4D, 2, &cam_cc, 0x1F, 4 }, - { "cam_cc_ife_0_axi_clk", &gcc, 0x4D, 2, &cam_cc, 0x25, 4 }, - { "cam_cc_ife_0_clk", &gcc, 0x4D, 2, &cam_cc, 0x1E, 4 }, - { "cam_cc_ife_0_cphy_rx_clk", &gcc, 0x4D, 2, &cam_cc, 0x24, 4 }, - { "cam_cc_ife_0_csid_clk", &gcc, 0x4D, 2, &cam_cc, 0x22, 4 }, - { "cam_cc_ife_0_dsp_clk", &gcc, 0x4D, 2, &cam_cc, 0x21, 4 }, - { "cam_cc_ife_1_ahb_clk", &gcc, 0x4D, 2, &cam_cc, 0x2E, 4 }, - { "cam_cc_ife_1_areg_clk", &gcc, 0x4D, 2, &cam_cc, 0x29, 4 }, - { "cam_cc_ife_1_axi_clk", &gcc, 0x4D, 2, &cam_cc, 0x2D, 4 }, - { "cam_cc_ife_1_clk", &gcc, 0x4D, 2, &cam_cc, 0x27, 4 }, - { "cam_cc_ife_1_cphy_rx_clk", &gcc, 0x4D, 2, &cam_cc, 0x2C, 4 }, - { "cam_cc_ife_1_csid_clk", &gcc, 0x4D, 2, &cam_cc, 0x2B, 4 }, - { "cam_cc_ife_1_dsp_clk", &gcc, 0x4D, 2, &cam_cc, 0x2A, 4 }, - { "cam_cc_ife_2_ahb_clk", &gcc, 0x4D, 2, &cam_cc, 0x54, 4 }, - { "cam_cc_ife_2_areg_clk", &gcc, 0x4D, 2, &cam_cc, 0x37, 4 }, - { "cam_cc_ife_2_axi_clk", &gcc, 0x4D, 2, &cam_cc, 0x53, 4 }, - { "cam_cc_ife_2_clk", &gcc, 0x4D, 2, &cam_cc, 0x7, 4 }, - { "cam_cc_ife_2_cphy_rx_clk", &gcc, 0x4D, 2, &cam_cc, 0x52, 4 }, - { "cam_cc_ife_2_csid_clk", &gcc, 0x4D, 2, &cam_cc, 0x51, 4 }, - { "cam_cc_ife_lite_ahb_clk", &gcc, 0x4D, 2, &cam_cc, 0x32, 4 }, - { "cam_cc_ife_lite_axi_clk", &gcc, 0x4D, 2, &cam_cc, 0x49, 4 }, - { "cam_cc_ife_lite_clk", &gcc, 0x4D, 2, &cam_cc, 0x2F, 4 }, - { "cam_cc_ife_lite_cphy_rx_clk", &gcc, 0x4D, 2, &cam_cc, 0x31, 4 }, - { "cam_cc_ife_lite_csid_clk", &gcc, 0x4D, 2, &cam_cc, 0x30, 4 }, - { "cam_cc_ipe_0_ahb_clk", &gcc, 0x4D, 2, &cam_cc, 0x1D, 4 }, - { "cam_cc_ipe_0_areg_clk", &gcc, 0x4D, 2, &cam_cc, 0x1C, 4 }, - { "cam_cc_ipe_0_axi_clk", &gcc, 0x4D, 2, &cam_cc, 0x1B, 4 }, - { "cam_cc_ipe_0_clk", &gcc, 0x4D, 2, &cam_cc, 0x19, 4 }, - { "cam_cc_jpeg_clk", &gcc, 0x4D, 2, &cam_cc, 0x33, 4 }, - { "cam_cc_mclk0_clk", &gcc, 0x4D, 2, &cam_cc, 0x1, 4 }, - { "cam_cc_mclk1_clk", &gcc, 0x4D, 2, &cam_cc, 0x2, 4 }, - { "cam_cc_mclk2_clk", &gcc, 0x4D, 2, &cam_cc, 0x3, 4 }, - { "cam_cc_mclk3_clk", &gcc, 0x4D, 2, &cam_cc, 0x4, 4 }, - { "cam_cc_mclk4_clk", &gcc, 0x4D, 2, &cam_cc, 0x5, 4 }, - { "cam_cc_mclk5_clk", &gcc, 0x4D, 2, &cam_cc, 0x6, 4 }, - { "cam_cc_sbi_ahb_clk", &gcc, 0x4D, 2, &cam_cc, 0x4E, 4 }, - { "cam_cc_sbi_axi_clk", &gcc, 0x4D, 2, &cam_cc, 0x4D, 4 }, - { "cam_cc_sbi_clk", &gcc, 0x4D, 2, &cam_cc, 0x4A, 4 }, - { "cam_cc_sbi_cphy_rx_0_clk", &gcc, 0x4D, 2, &cam_cc, 0x4C, 4 }, - { "cam_cc_sbi_cphy_rx_1_clk", &gcc, 0x4D, 2, &cam_cc, 0x56, 4 }, - { "cam_cc_sbi_csid_0_clk", &gcc, 0x4D, 2, &cam_cc, 0x4B, 4 }, - { "cam_cc_sbi_csid_1_clk", &gcc, 0x4D, 2, &cam_cc, 0x57, 4 }, - { "cam_cc_sbi_ife_0_clk", &gcc, 0x4D, 2, &cam_cc, 0x4F, 4 }, - { "cam_cc_sbi_ife_1_clk", &gcc, 0x4D, 2, &cam_cc, 0x50, 4 }, - { "cam_cc_sbi_ife_2_clk", &gcc, 0x4D, 2, &cam_cc, 0x55, 4 }, - { "cam_cc_sleep_clk", &gcc, 0x4D, 2, &cam_cc, 0x42, 4 }, + { "cam_cc_bps_ahb_clk", &gcc, 0x4D, &cam_cc, 0x18 }, + { "cam_cc_bps_areg_clk", &gcc, 0x4D, &cam_cc, 0x17 }, + { "cam_cc_bps_axi_clk", &gcc, 0x4D, &cam_cc, 0x16 }, + { "cam_cc_bps_clk", &gcc, 0x4D, &cam_cc, 0x14 }, + { "cam_cc_camnoc_axi_clk", &gcc, 0x4D, &cam_cc, 0x3C }, + { "cam_cc_camnoc_dcd_xo_clk", &gcc, 0x4D, &cam_cc, 0x3D }, + { "cam_cc_cci_0_clk", &gcc, 0x4D, &cam_cc, 0x39 }, + { "cam_cc_cci_1_clk", &gcc, 0x4D, &cam_cc, 0x3A }, + { "cam_cc_core_ahb_clk", &gcc, 0x4D, &cam_cc, 0x40 }, + { "cam_cc_cpas_ahb_clk", &gcc, 0x4D, &cam_cc, 0x3B }, + { "cam_cc_csi0phytimer_clk", &gcc, 0x4D, &cam_cc, 0x8 }, + { "cam_cc_csi1phytimer_clk", &gcc, 0x4D, &cam_cc, 0xA }, + { "cam_cc_csi2phytimer_clk", &gcc, 0x4D, &cam_cc, 0xC }, + { "cam_cc_csi3phytimer_clk", &gcc, 0x4D, &cam_cc, 0xE }, + { "cam_cc_csi4phytimer_clk", &gcc, 0x4D, &cam_cc, 0x10 }, + { "cam_cc_csi5phytimer_clk", &gcc, 0x4D, &cam_cc, 0x12 }, + { "cam_cc_csiphy0_clk", &gcc, 0x4D, &cam_cc, 0x9 }, + { "cam_cc_csiphy1_clk", &gcc, 0x4D, &cam_cc, 0xB }, + { "cam_cc_csiphy2_clk", &gcc, 0x4D, &cam_cc, 0xD }, + { "cam_cc_csiphy3_clk", &gcc, 0x4D, &cam_cc, 0xF }, + { "cam_cc_csiphy4_clk", &gcc, 0x4D, &cam_cc, 0x11 }, + { "cam_cc_csiphy5_clk", &gcc, 0x4D, &cam_cc, 0x13 }, + { "cam_cc_icp_ahb_clk", &gcc, 0x4D, &cam_cc, 0x36 }, + { "cam_cc_icp_clk", &gcc, 0x4D, &cam_cc, 0x35 }, + { "cam_cc_ife_0_ahb_clk", &gcc, 0x4D, &cam_cc, 0x26 }, + { "cam_cc_ife_0_areg_clk", &gcc, 0x4D, &cam_cc, 0x1F }, + { "cam_cc_ife_0_axi_clk", &gcc, 0x4D, &cam_cc, 0x25 }, + { "cam_cc_ife_0_clk", &gcc, 0x4D, &cam_cc, 0x1E }, + { "cam_cc_ife_0_cphy_rx_clk", &gcc, 0x4D, &cam_cc, 0x24 }, + { "cam_cc_ife_0_csid_clk", &gcc, 0x4D, &cam_cc, 0x22 }, + { "cam_cc_ife_0_dsp_clk", &gcc, 0x4D, &cam_cc, 0x21 }, + { "cam_cc_ife_1_ahb_clk", &gcc, 0x4D, &cam_cc, 0x2E }, + { "cam_cc_ife_1_areg_clk", &gcc, 0x4D, &cam_cc, 0x29 }, + { "cam_cc_ife_1_axi_clk", &gcc, 0x4D, &cam_cc, 0x2D }, + { "cam_cc_ife_1_clk", &gcc, 0x4D, &cam_cc, 0x27 }, + { "cam_cc_ife_1_cphy_rx_clk", &gcc, 0x4D, &cam_cc, 0x2C }, + { "cam_cc_ife_1_csid_clk", &gcc, 0x4D, &cam_cc, 0x2B }, + { "cam_cc_ife_1_dsp_clk", &gcc, 0x4D, &cam_cc, 0x2A }, + { "cam_cc_ife_2_ahb_clk", &gcc, 0x4D, &cam_cc, 0x54 }, + { "cam_cc_ife_2_areg_clk", &gcc, 0x4D, &cam_cc, 0x37 }, + { "cam_cc_ife_2_axi_clk", &gcc, 0x4D, &cam_cc, 0x53 }, + { "cam_cc_ife_2_clk", &gcc, 0x4D, &cam_cc, 0x7 }, + { "cam_cc_ife_2_cphy_rx_clk", &gcc, 0x4D, &cam_cc, 0x52 }, + { "cam_cc_ife_2_csid_clk", &gcc, 0x4D, &cam_cc, 0x51 }, + { "cam_cc_ife_lite_ahb_clk", &gcc, 0x4D, &cam_cc, 0x32 }, + { "cam_cc_ife_lite_axi_clk", &gcc, 0x4D, &cam_cc, 0x49 }, + { "cam_cc_ife_lite_clk", &gcc, 0x4D, &cam_cc, 0x2F }, + { "cam_cc_ife_lite_cphy_rx_clk", &gcc, 0x4D, &cam_cc, 0x31 }, + { "cam_cc_ife_lite_csid_clk", &gcc, 0x4D, &cam_cc, 0x30 }, + { "cam_cc_ipe_0_ahb_clk", &gcc, 0x4D, &cam_cc, 0x1D }, + { "cam_cc_ipe_0_areg_clk", &gcc, 0x4D, &cam_cc, 0x1C }, + { "cam_cc_ipe_0_axi_clk", &gcc, 0x4D, &cam_cc, 0x1B }, + { "cam_cc_ipe_0_clk", &gcc, 0x4D, &cam_cc, 0x19 }, + { "cam_cc_jpeg_clk", &gcc, 0x4D, &cam_cc, 0x33 }, + { "cam_cc_mclk0_clk", &gcc, 0x4D, &cam_cc, 0x1 }, + { "cam_cc_mclk1_clk", &gcc, 0x4D, &cam_cc, 0x2 }, + { "cam_cc_mclk2_clk", &gcc, 0x4D, &cam_cc, 0x3 }, + { "cam_cc_mclk3_clk", &gcc, 0x4D, &cam_cc, 0x4 }, + { "cam_cc_mclk4_clk", &gcc, 0x4D, &cam_cc, 0x5 }, + { "cam_cc_mclk5_clk", &gcc, 0x4D, &cam_cc, 0x6 }, + { "cam_cc_sbi_ahb_clk", &gcc, 0x4D, &cam_cc, 0x4E }, + { "cam_cc_sbi_axi_clk", &gcc, 0x4D, &cam_cc, 0x4D }, + { "cam_cc_sbi_clk", &gcc, 0x4D, &cam_cc, 0x4A }, + { "cam_cc_sbi_cphy_rx_0_clk", &gcc, 0x4D, &cam_cc, 0x4C }, + { "cam_cc_sbi_cphy_rx_1_clk", &gcc, 0x4D, &cam_cc, 0x56 }, + { "cam_cc_sbi_csid_0_clk", &gcc, 0x4D, &cam_cc, 0x4B }, + { "cam_cc_sbi_csid_1_clk", &gcc, 0x4D, &cam_cc, 0x57 }, + { "cam_cc_sbi_ife_0_clk", &gcc, 0x4D, &cam_cc, 0x4F }, + { "cam_cc_sbi_ife_1_clk", &gcc, 0x4D, &cam_cc, 0x50 }, + { "cam_cc_sbi_ife_2_clk", &gcc, 0x4D, &cam_cc, 0x55 }, + { "cam_cc_sleep_clk", &gcc, 0x4D, &cam_cc, 0x42 }, /* disp_cc_debug_mux is 0x53 */ - { "disp_cc_mdss_ahb_clk", &gcc, 0x53, 2, &disp_cc, 0x2A, 4 }, - { "disp_cc_mdss_byte0_clk", &gcc, 0x53, 2, &disp_cc, 0x15, 4 }, - { "disp_cc_mdss_byte0_intf_clk", &gcc, 0x53, 2, &disp_cc, 0x16, 4 }, - { "disp_cc_mdss_byte1_clk", &gcc, 0x53, 2, &disp_cc, 0x17, 4 }, - { "disp_cc_mdss_byte1_intf_clk", &gcc, 0x53, 2, &disp_cc, 0x18, 4 }, - { "disp_cc_mdss_dp_aux1_clk", &gcc, 0x53, 2, &disp_cc, 0x25, 4 }, - { "disp_cc_mdss_dp_aux_clk", &gcc, 0x53, 2, &disp_cc, 0x20, 4 }, - { "disp_cc_mdss_dp_link1_clk", &gcc, 0x53, 2, &disp_cc, 0x22, 4 }, - { "disp_cc_mdss_dp_link1_intf_clk", &gcc, 0x53, 2, &disp_cc, 0x23, 4 }, - { "disp_cc_mdss_dp_link_clk", &gcc, 0x53, 2, &disp_cc, 0x1B, 4 }, - { "disp_cc_mdss_dp_link_intf_clk", &gcc, 0x53, 2, &disp_cc, 0x1C, 4 }, - { "disp_cc_mdss_dp_pixel1_clk", &gcc, 0x53, 2, &disp_cc, 0x1F, 4 }, - { "disp_cc_mdss_dp_pixel2_clk", &gcc, 0x53, 2, &disp_cc, 0x21, 4 }, - { "disp_cc_mdss_dp_pixel_clk", &gcc, 0x53, 2, &disp_cc, 0x1E, 4 }, - { "disp_cc_mdss_edp_aux_clk", &gcc, 0x53, 2, &disp_cc, 0x29, 4 }, - { "disp_cc_mdss_edp_link_clk", &gcc, 0x53, 2, &disp_cc, 0x27, 4 }, - { "disp_cc_mdss_edp_link_intf_clk", &gcc, 0x53, 2, &disp_cc, 0x28, 4 }, - { "disp_cc_mdss_edp_pixel_clk", &gcc, 0x53, 2, &disp_cc, 0x26, 4 }, - { "disp_cc_mdss_esc0_clk", &gcc, 0x53, 2, &disp_cc, 0x19, 4 }, - { "disp_cc_mdss_esc1_clk", &gcc, 0x53, 2, &disp_cc, 0x1A, 4 }, - { "disp_cc_mdss_mdp_clk", &gcc, 0x53, 2, &disp_cc, 0x11, 4 }, - { "disp_cc_mdss_mdp_lut_clk", &gcc, 0x53, 2, &disp_cc, 0x13, 4 }, - { "disp_cc_mdss_non_gdsc_ahb_clk", &gcc, 0x53, 2, &disp_cc, 0x2B, 4 }, - { "disp_cc_mdss_pclk0_clk", &gcc, 0x53, 2, &disp_cc, 0xF, 4 }, - { "disp_cc_mdss_pclk1_clk", &gcc, 0x53, 2, &disp_cc, 0x10, 4 }, - { "disp_cc_mdss_rot_clk", &gcc, 0x53, 2, &disp_cc, 0x12, 4 }, - { "disp_cc_mdss_rscc_ahb_clk", &gcc, 0x53, 2, &disp_cc, 0x2D, 4 }, - { "disp_cc_mdss_rscc_vsync_clk", &gcc, 0x53, 2, &disp_cc, 0x2C, 4 }, - { "disp_cc_mdss_vsync_clk", &gcc, 0x53, 2, &disp_cc, 0x14, 4 }, - { "disp_cc_sleep_clk", &gcc, 0x53, 2, &disp_cc, 0x36, 4 }, + { "disp_cc_mdss_ahb_clk", &gcc, 0x53, &disp_cc, 0x2A }, + { "disp_cc_mdss_byte0_clk", &gcc, 0x53, &disp_cc, 0x15 }, + { "disp_cc_mdss_byte0_intf_clk", &gcc, 0x53, &disp_cc, 0x16 }, + { "disp_cc_mdss_byte1_clk", &gcc, 0x53, &disp_cc, 0x17 }, + { "disp_cc_mdss_byte1_intf_clk", &gcc, 0x53, &disp_cc, 0x18 }, + { "disp_cc_mdss_dp_aux1_clk", &gcc, 0x53, &disp_cc, 0x25 }, + { "disp_cc_mdss_dp_aux_clk", &gcc, 0x53, &disp_cc, 0x20 }, + { "disp_cc_mdss_dp_link1_clk", &gcc, 0x53, &disp_cc, 0x22 }, + { "disp_cc_mdss_dp_link1_intf_clk", &gcc, 0x53, &disp_cc, 0x23 }, + { "disp_cc_mdss_dp_link_clk", &gcc, 0x53, &disp_cc, 0x1B }, + { "disp_cc_mdss_dp_link_intf_clk", &gcc, 0x53, &disp_cc, 0x1C }, + { "disp_cc_mdss_dp_pixel1_clk", &gcc, 0x53, &disp_cc, 0x1F }, + { "disp_cc_mdss_dp_pixel2_clk", &gcc, 0x53, &disp_cc, 0x21 }, + { "disp_cc_mdss_dp_pixel_clk", &gcc, 0x53, &disp_cc, 0x1E }, + { "disp_cc_mdss_edp_aux_clk", &gcc, 0x53, &disp_cc, 0x29 }, + { "disp_cc_mdss_edp_link_clk", &gcc, 0x53, &disp_cc, 0x27 }, + { "disp_cc_mdss_edp_link_intf_clk", &gcc, 0x53, &disp_cc, 0x28 }, + { "disp_cc_mdss_edp_pixel_clk", &gcc, 0x53, &disp_cc, 0x26 }, + { "disp_cc_mdss_esc0_clk", &gcc, 0x53, &disp_cc, 0x19 }, + { "disp_cc_mdss_esc1_clk", &gcc, 0x53, &disp_cc, 0x1A }, + { "disp_cc_mdss_mdp_clk", &gcc, 0x53, &disp_cc, 0x11 }, + { "disp_cc_mdss_mdp_lut_clk", &gcc, 0x53, &disp_cc, 0x13 }, + { "disp_cc_mdss_non_gdsc_ahb_clk", &gcc, 0x53, &disp_cc, 0x2B }, + { "disp_cc_mdss_pclk0_clk", &gcc, 0x53, &disp_cc, 0xF }, + { "disp_cc_mdss_pclk1_clk", &gcc, 0x53, &disp_cc, 0x10 }, + { "disp_cc_mdss_rot_clk", &gcc, 0x53, &disp_cc, 0x12 }, + { "disp_cc_mdss_rscc_ahb_clk", &gcc, 0x53, &disp_cc, 0x2D }, + { "disp_cc_mdss_rscc_vsync_clk", &gcc, 0x53, &disp_cc, 0x2C }, + { "disp_cc_mdss_vsync_clk", &gcc, 0x53, &disp_cc, 0x14 }, + { "disp_cc_sleep_clk", &gcc, 0x53, &disp_cc, 0x36 }, // gcc - { "core_bi_pll_test_se", &gcc, 0x5, 2 }, - { "gcc_aggre_noc_pcie_0_axi_clk", &gcc, 0x138, 2 }, - { "gcc_aggre_noc_pcie_1_axi_clk", &gcc, 0x139, 2 }, - { "gcc_aggre_noc_pcie_tbu_clk", &gcc, 0x34, 2 }, - { "gcc_aggre_ufs_card_axi_clk", &gcc, 0x13D, 2 }, - { "gcc_aggre_ufs_phy_axi_clk", &gcc, 0x13C, 2 }, - { "gcc_aggre_usb3_prim_axi_clk", &gcc, 0x13A, 2 }, - { "gcc_aggre_usb3_sec_axi_clk", &gcc, 0x13B, 2 }, - { "gcc_boot_rom_ahb_clk", &gcc, 0xA8, 2 }, - { "gcc_camera_ahb_clk", &gcc, 0x47, 2 }, - { "gcc_camera_hf_axi_clk", &gcc, 0x4A, 2 }, - { "gcc_camera_sf_axi_clk", &gcc, 0x4B, 2 }, - { "gcc_camera_xo_clk", &gcc, 0x4C, 2 }, - { "gcc_cfg_noc_usb3_prim_axi_clk", &gcc, 0x1F, 2 }, - { "gcc_cfg_noc_usb3_sec_axi_clk", &gcc, 0x20, 2 }, - { "gcc_ddrss_gpu_axi_clk", &gcc, 0xC9, 2 }, - { "gcc_ddrss_pcie_sf_tbu_clk", &gcc, 0xCA, 2 }, - { "gcc_disp_ahb_clk", &gcc, 0x4E, 2 }, - { "gcc_disp_hf_axi_clk", &gcc, 0x50, 2 }, - { "gcc_disp_sf_axi_clk", &gcc, 0x51, 2 }, - { "gcc_disp_xo_clk", &gcc, 0x52, 2 }, - { "gcc_gp1_clk", &gcc, 0xF1, 2 }, - { "gcc_gp2_clk", &gcc, 0xF2, 2 }, - { "gcc_gp3_clk", &gcc, 0xF3, 2 }, - { "gcc_gpu_cfg_ahb_clk", &gcc, 0x151, 2 }, - { "gcc_gpu_gpll0_clk_src", &gcc, 0x158, 2 }, - { "gcc_gpu_gpll0_div_clk_src", &gcc, 0x159, 2 }, - { "gcc_gpu_memnoc_gfx_clk", &gcc, 0x154, 2 }, - { "gcc_gpu_snoc_dvm_gfx_clk", &gcc, 0x157, 2 }, - { "gcc_pcie0_phy_rchng_clk", &gcc, 0xFA, 2 }, - { "gcc_pcie1_phy_rchng_clk", &gcc, 0x103, 2 }, - { "gcc_pcie_0_aux_clk", &gcc, 0xF8, 2 }, - { "gcc_pcie_0_cfg_ahb_clk", &gcc, 0xF7, 2 }, - { "gcc_pcie_0_mstr_axi_clk", &gcc, 0xF6, 2 }, - { "gcc_pcie_0_pipe_clk", &gcc, 0xF9, 2 }, - { "gcc_pcie_0_slv_axi_clk", &gcc, 0xF5, 2 }, - { "gcc_pcie_0_slv_q2a_axi_clk", &gcc, 0xF4, 2 }, - { "gcc_pcie_1_aux_clk", &gcc, 0x101, 2 }, - { "gcc_pcie_1_cfg_ahb_clk", &gcc, 0x100, 2 }, - { "gcc_pcie_1_mstr_axi_clk", &gcc, 0xFF, 2 }, - { "gcc_pcie_1_pipe_clk", &gcc, 0x102, 2 }, - { "gcc_pcie_1_slv_axi_clk", &gcc, 0xFE, 2 }, - { "gcc_pcie_1_slv_q2a_axi_clk", &gcc, 0xFD, 2 }, - { "gcc_pdm2_clk", &gcc, 0x9E, 2 }, - { "gcc_pdm_ahb_clk", &gcc, 0x9C, 2 }, - { "gcc_pdm_xo4_clk", &gcc, 0x9D, 2 }, - { "gcc_qmip_camera_nrt_ahb_clk", &gcc, 0x48, 2 }, - { "gcc_qmip_camera_rt_ahb_clk", &gcc, 0x49, 2 }, - { "gcc_qmip_disp_ahb_clk", &gcc, 0x4F, 2 }, - { "gcc_qmip_video_cvp_ahb_clk", &gcc, 0x55, 2 }, - { "gcc_qmip_video_vcodec_ahb_clk", &gcc, 0x56, 2 }, - { "gcc_qupv3_wrap0_core_2x_clk", &gcc, 0x89, 2 }, - { "gcc_qupv3_wrap0_core_clk", &gcc, 0x88, 2 }, - { "gcc_qupv3_wrap0_s0_clk", &gcc, 0x8A, 2 }, - { "gcc_qupv3_wrap0_s1_clk", &gcc, 0x8B, 2 }, - { "gcc_qupv3_wrap0_s2_clk", &gcc, 0x8C, 2 }, - { "gcc_qupv3_wrap0_s3_clk", &gcc, 0x8D, 2 }, - { "gcc_qupv3_wrap0_s4_clk", &gcc, 0x8E, 2 }, - { "gcc_qupv3_wrap0_s5_clk", &gcc, 0x8F, 2 }, - { "gcc_qupv3_wrap0_s6_clk", &gcc, 0x90, 2 }, - { "gcc_qupv3_wrap0_s7_clk", &gcc, 0x91, 2 }, - { "gcc_qupv3_wrap1_core_2x_clk", &gcc, 0x95, 2 }, - { "gcc_qupv3_wrap1_core_clk", &gcc, 0x94, 2 }, - { "gcc_qupv3_wrap1_s0_clk", &gcc, 0x96, 2 }, - { "gcc_qupv3_wrap1_s1_clk", &gcc, 0x97, 2 }, - { "gcc_qupv3_wrap1_s2_clk", &gcc, 0x98, 2 }, - { "gcc_qupv3_wrap1_s3_clk", &gcc, 0x99, 2 }, - { "gcc_qupv3_wrap1_s4_clk", &gcc, 0x9A, 2 }, - { "gcc_qupv3_wrap2_core_2x_clk", &gcc, 0x16E, 2 }, - { "gcc_qupv3_wrap2_core_clk", &gcc, 0x16D, 2 }, - { "gcc_qupv3_wrap2_s0_clk", &gcc, 0x16F, 2 }, - { "gcc_qupv3_wrap2_s1_clk", &gcc, 0x170, 2 }, - { "gcc_qupv3_wrap2_s2_clk", &gcc, 0x171, 2 }, - { "gcc_qupv3_wrap2_s3_clk", &gcc, 0x172, 2 }, - { "gcc_qupv3_wrap2_s4_clk", &gcc, 0x173, 2 }, - { "gcc_qupv3_wrap2_s5_clk", &gcc, 0x174, 2 }, - { "gcc_qupv3_wrap_0_m_ahb_clk", &gcc, 0x86, 2 }, - { "gcc_qupv3_wrap_0_s_ahb_clk", &gcc, 0x87, 2 }, - { "gcc_qupv3_wrap_2_m_ahb_clk", &gcc, 0x16B, 2 }, - { "gcc_qupv3_wrap_2_s_ahb_clk", &gcc, 0x16C, 2 }, - { "gcc_sdcc2_ahb_clk", &gcc, 0x83, 2 }, - { "gcc_sdcc2_apps_clk", &gcc, 0x82, 2 }, - { "gcc_sdcc4_ahb_clk", &gcc, 0x85, 2 }, - { "gcc_sdcc4_apps_clk", &gcc, 0x84, 2 }, - { "gcc_throttle_pcie_ahb_clk", &gcc, 0x40, 2 }, - { "gcc_ufs_card_ahb_clk", &gcc, 0x107, 2 }, - { "gcc_ufs_card_axi_clk", &gcc, 0x106, 2 }, - { "gcc_ufs_card_ice_core_clk", &gcc, 0x10D, 2 }, - { "gcc_ufs_card_phy_aux_clk", &gcc, 0x10E, 2 }, - { "gcc_ufs_card_rx_symbol_0_clk", &gcc, 0x109, 2 }, - { "gcc_ufs_card_rx_symbol_1_clk", &gcc, 0x10F, 2 }, - { "gcc_ufs_card_tx_symbol_0_clk", &gcc, 0x108, 2 }, - { "gcc_ufs_card_unipro_core_clk", &gcc, 0x10C, 2 }, - { "gcc_ufs_phy_ahb_clk", &gcc, 0x113, 2 }, - { "gcc_ufs_phy_axi_clk", &gcc, 0x112, 2 }, - { "gcc_ufs_phy_ice_core_clk", &gcc, 0x119, 2 }, - { "gcc_ufs_phy_phy_aux_clk", &gcc, 0x11A, 2 }, - { "gcc_ufs_phy_rx_symbol_0_clk", &gcc, 0x115, 2 }, - { "gcc_ufs_phy_rx_symbol_1_clk", &gcc, 0x11B, 2 }, - { "gcc_ufs_phy_tx_symbol_0_clk", &gcc, 0x114, 2 }, - { "gcc_ufs_phy_unipro_core_clk", &gcc, 0x118, 2 }, - { "gcc_usb30_prim_master_clk", &gcc, 0x6D, 2 }, - { "gcc_usb30_prim_mock_utmi_clk", &gcc, 0x6F, 2 }, - { "gcc_usb30_prim_sleep_clk", &gcc, 0x6E, 2 }, - { "gcc_usb30_sec_master_clk", &gcc, 0x76, 2 }, - { "gcc_usb30_sec_mock_utmi_clk", &gcc, 0x78, 2 }, - { "gcc_usb30_sec_sleep_clk", &gcc, 0x77, 2 }, - { "gcc_usb3_prim_phy_aux_clk", &gcc, 0x70, 2 }, - { "gcc_usb3_prim_phy_com_aux_clk", &gcc, 0x71, 2 }, - { "gcc_usb3_prim_phy_pipe_clk", &gcc, 0x72, 2 }, - { "gcc_usb3_sec_phy_aux_clk", &gcc, 0x79, 2 }, - { "gcc_usb3_sec_phy_com_aux_clk", &gcc, 0x7A, 2 }, - { "gcc_usb3_sec_phy_pipe_clk", &gcc, 0x7B, 2 }, - { "gcc_video_ahb_clk", &gcc, 0x54, 2 }, - { "gcc_video_axi0_clk", &gcc, 0x57, 2 }, - { "gcc_video_axi1_clk", &gcc, 0x58, 2 }, - { "gcc_video_xo_clk", &gcc, 0x59, 2 }, - { "gpu_cc_debug_mux", &gcc, 0x153, 2 }, - { "measure_only_cnoc_clk", &gcc, 0x18, 2 }, - { "measure_only_ipa_2x_clk", &gcc, 0x140, 2 }, - { "measure_only_memnoc_clk", &gcc, 0xCF, 2 }, - { "measure_only_snoc_clk", &gcc, 0x9, 2 }, - { "pcie_0_pipe_clk", &gcc, 0xFB, 2 }, - { "pcie_1_pipe_clk", &gcc, 0x104, 2 }, - { "ufs_card_rx_symbol_0_clk", &gcc, 0x10B, 2 }, - { "ufs_card_rx_symbol_1_clk", &gcc, 0x110, 2 }, - { "ufs_card_tx_symbol_0_clk", &gcc, 0x10A, 2 }, - { "ufs_phy_rx_symbol_0_clk", &gcc, 0x117, 2 }, - { "ufs_phy_rx_symbol_1_clk", &gcc, 0x11C, 2 }, - { "ufs_phy_tx_symbol_0_clk", &gcc, 0x116, 2 }, - { "usb3_phy_wrapper_gcc_usb30_pipe_clk", &gcc, 0x7C, 2 }, - { "usb3_uni_phy_sec_gcc_usb30_pipe_clk", &gcc, 0x7D, 2 }, - { "mc_cc_debug_mux", &gcc, 0xD3, 2 }, + { "core_bi_pll_test_se", &gcc, 0x5 }, + { "gcc_aggre_noc_pcie_0_axi_clk", &gcc, 0x138 }, + { "gcc_aggre_noc_pcie_1_axi_clk", &gcc, 0x139 }, + { "gcc_aggre_noc_pcie_tbu_clk", &gcc, 0x34 }, + { "gcc_aggre_ufs_card_axi_clk", &gcc, 0x13D }, + { "gcc_aggre_ufs_phy_axi_clk", &gcc, 0x13C }, + { "gcc_aggre_usb3_prim_axi_clk", &gcc, 0x13A }, + { "gcc_aggre_usb3_sec_axi_clk", &gcc, 0x13B }, + { "gcc_boot_rom_ahb_clk", &gcc, 0xA8 }, + { "gcc_camera_ahb_clk", &gcc, 0x47 }, + { "gcc_camera_hf_axi_clk", &gcc, 0x4A }, + { "gcc_camera_sf_axi_clk", &gcc, 0x4B }, + { "gcc_camera_xo_clk", &gcc, 0x4C }, + { "gcc_cfg_noc_usb3_prim_axi_clk", &gcc, 0x1F }, + { "gcc_cfg_noc_usb3_sec_axi_clk", &gcc, 0x20 }, + { "gcc_ddrss_gpu_axi_clk", &gcc, 0xC9 }, + { "gcc_ddrss_pcie_sf_tbu_clk", &gcc, 0xCA }, + { "gcc_disp_ahb_clk", &gcc, 0x4E }, + { "gcc_disp_hf_axi_clk", &gcc, 0x50 }, + { "gcc_disp_sf_axi_clk", &gcc, 0x51 }, + { "gcc_disp_xo_clk", &gcc, 0x52 }, + { "gcc_gp1_clk", &gcc, 0xF1 }, + { "gcc_gp2_clk", &gcc, 0xF2 }, + { "gcc_gp3_clk", &gcc, 0xF3 }, + { "gcc_gpu_cfg_ahb_clk", &gcc, 0x151 }, + { "gcc_gpu_gpll0_clk_src", &gcc, 0x158 }, + { "gcc_gpu_gpll0_div_clk_src", &gcc, 0x159 }, + { "gcc_gpu_memnoc_gfx_clk", &gcc, 0x154 }, + { "gcc_gpu_snoc_dvm_gfx_clk", &gcc, 0x157 }, + { "gcc_pcie0_phy_rchng_clk", &gcc, 0xFA }, + { "gcc_pcie1_phy_rchng_clk", &gcc, 0x103 }, + { "gcc_pcie_0_aux_clk", &gcc, 0xF8 }, + { "gcc_pcie_0_cfg_ahb_clk", &gcc, 0xF7 }, + { "gcc_pcie_0_mstr_axi_clk", &gcc, 0xF6 }, + { "gcc_pcie_0_pipe_clk", &gcc, 0xF9 }, + { "gcc_pcie_0_slv_axi_clk", &gcc, 0xF5 }, + { "gcc_pcie_0_slv_q2a_axi_clk", &gcc, 0xF4 }, + { "gcc_pcie_1_aux_clk", &gcc, 0x101 }, + { "gcc_pcie_1_cfg_ahb_clk", &gcc, 0x100 }, + { "gcc_pcie_1_mstr_axi_clk", &gcc, 0xFF }, + { "gcc_pcie_1_pipe_clk", &gcc, 0x102 }, + { "gcc_pcie_1_slv_axi_clk", &gcc, 0xFE }, + { "gcc_pcie_1_slv_q2a_axi_clk", &gcc, 0xFD }, + { "gcc_pdm2_clk", &gcc, 0x9E }, + { "gcc_pdm_ahb_clk", &gcc, 0x9C }, + { "gcc_pdm_xo4_clk", &gcc, 0x9D }, + { "gcc_qmip_camera_nrt_ahb_clk", &gcc, 0x48 }, + { "gcc_qmip_camera_rt_ahb_clk", &gcc, 0x49 }, + { "gcc_qmip_disp_ahb_clk", &gcc, 0x4F }, + { "gcc_qmip_video_cvp_ahb_clk", &gcc, 0x55 }, + { "gcc_qmip_video_vcodec_ahb_clk", &gcc, 0x56 }, + { "gcc_qupv3_wrap0_core_2x_clk", &gcc, 0x89 }, + { "gcc_qupv3_wrap0_core_clk", &gcc, 0x88 }, + { "gcc_qupv3_wrap0_s0_clk", &gcc, 0x8A }, + { "gcc_qupv3_wrap0_s1_clk", &gcc, 0x8B }, + { "gcc_qupv3_wrap0_s2_clk", &gcc, 0x8C }, + { "gcc_qupv3_wrap0_s3_clk", &gcc, 0x8D }, + { "gcc_qupv3_wrap0_s4_clk", &gcc, 0x8E }, + { "gcc_qupv3_wrap0_s5_clk", &gcc, 0x8F }, + { "gcc_qupv3_wrap0_s6_clk", &gcc, 0x90 }, + { "gcc_qupv3_wrap0_s7_clk", &gcc, 0x91 }, + { "gcc_qupv3_wrap1_core_2x_clk", &gcc, 0x95 }, + { "gcc_qupv3_wrap1_core_clk", &gcc, 0x94 }, + { "gcc_qupv3_wrap1_s0_clk", &gcc, 0x96 }, + { "gcc_qupv3_wrap1_s1_clk", &gcc, 0x97 }, + { "gcc_qupv3_wrap1_s2_clk", &gcc, 0x98 }, + { "gcc_qupv3_wrap1_s3_clk", &gcc, 0x99 }, + { "gcc_qupv3_wrap1_s4_clk", &gcc, 0x9A }, + { "gcc_qupv3_wrap2_core_2x_clk", &gcc, 0x16E }, + { "gcc_qupv3_wrap2_core_clk", &gcc, 0x16D }, + { "gcc_qupv3_wrap2_s0_clk", &gcc, 0x16F }, + { "gcc_qupv3_wrap2_s1_clk", &gcc, 0x170 }, + { "gcc_qupv3_wrap2_s2_clk", &gcc, 0x171 }, + { "gcc_qupv3_wrap2_s3_clk", &gcc, 0x172 }, + { "gcc_qupv3_wrap2_s4_clk", &gcc, 0x173 }, + { "gcc_qupv3_wrap2_s5_clk", &gcc, 0x174 }, + { "gcc_qupv3_wrap_0_m_ahb_clk", &gcc, 0x86 }, + { "gcc_qupv3_wrap_0_s_ahb_clk", &gcc, 0x87 }, + { "gcc_qupv3_wrap_2_m_ahb_clk", &gcc, 0x16B }, + { "gcc_qupv3_wrap_2_s_ahb_clk", &gcc, 0x16C }, + { "gcc_sdcc2_ahb_clk", &gcc, 0x83 }, + { "gcc_sdcc2_apps_clk", &gcc, 0x82 }, + { "gcc_sdcc4_ahb_clk", &gcc, 0x85 }, + { "gcc_sdcc4_apps_clk", &gcc, 0x84 }, + { "gcc_throttle_pcie_ahb_clk", &gcc, 0x40 }, + { "gcc_ufs_card_ahb_clk", &gcc, 0x107 }, + { "gcc_ufs_card_axi_clk", &gcc, 0x106 }, + { "gcc_ufs_card_ice_core_clk", &gcc, 0x10D }, + { "gcc_ufs_card_phy_aux_clk", &gcc, 0x10E }, + { "gcc_ufs_card_rx_symbol_0_clk", &gcc, 0x109 }, + { "gcc_ufs_card_rx_symbol_1_clk", &gcc, 0x10F }, + { "gcc_ufs_card_tx_symbol_0_clk", &gcc, 0x108 }, + { "gcc_ufs_card_unipro_core_clk", &gcc, 0x10C }, + { "gcc_ufs_phy_ahb_clk", &gcc, 0x113 }, + { "gcc_ufs_phy_axi_clk", &gcc, 0x112 }, + { "gcc_ufs_phy_ice_core_clk", &gcc, 0x119 }, + { "gcc_ufs_phy_phy_aux_clk", &gcc, 0x11A }, + { "gcc_ufs_phy_rx_symbol_0_clk", &gcc, 0x115 }, + { "gcc_ufs_phy_rx_symbol_1_clk", &gcc, 0x11B }, + { "gcc_ufs_phy_tx_symbol_0_clk", &gcc, 0x114 }, + { "gcc_ufs_phy_unipro_core_clk", &gcc, 0x118 }, + { "gcc_usb30_prim_master_clk", &gcc, 0x6D }, + { "gcc_usb30_prim_mock_utmi_clk", &gcc, 0x6F }, + { "gcc_usb30_prim_sleep_clk", &gcc, 0x6E }, + { "gcc_usb30_sec_master_clk", &gcc, 0x76 }, + { "gcc_usb30_sec_mock_utmi_clk", &gcc, 0x78 }, + { "gcc_usb30_sec_sleep_clk", &gcc, 0x77 }, + { "gcc_usb3_prim_phy_aux_clk", &gcc, 0x70 }, + { "gcc_usb3_prim_phy_com_aux_clk", &gcc, 0x71 }, + { "gcc_usb3_prim_phy_pipe_clk", &gcc, 0x72 }, + { "gcc_usb3_sec_phy_aux_clk", &gcc, 0x79 }, + { "gcc_usb3_sec_phy_com_aux_clk", &gcc, 0x7A }, + { "gcc_usb3_sec_phy_pipe_clk", &gcc, 0x7B }, + { "gcc_video_ahb_clk", &gcc, 0x54 }, + { "gcc_video_axi0_clk", &gcc, 0x57 }, + { "gcc_video_axi1_clk", &gcc, 0x58 }, + { "gcc_video_xo_clk", &gcc, 0x59 }, + { "gpu_cc_debug_mux", &gcc, 0x153 }, + { "measure_only_cnoc_clk", &gcc, 0x18 }, + { "measure_only_ipa_2x_clk", &gcc, 0x140 }, + { "measure_only_memnoc_clk", &gcc, 0xCF }, + { "measure_only_snoc_clk", &gcc, 0x9 }, + { "pcie_0_pipe_clk", &gcc, 0xFB }, + { "pcie_1_pipe_clk", &gcc, 0x104 }, + { "ufs_card_rx_symbol_0_clk", &gcc, 0x10B }, + { "ufs_card_rx_symbol_1_clk", &gcc, 0x110 }, + { "ufs_card_tx_symbol_0_clk", &gcc, 0x10A }, + { "ufs_phy_rx_symbol_0_clk", &gcc, 0x117 }, + { "ufs_phy_rx_symbol_1_clk", &gcc, 0x11C }, + { "ufs_phy_tx_symbol_0_clk", &gcc, 0x116 }, + { "usb3_phy_wrapper_gcc_usb30_pipe_clk", &gcc, 0x7C }, + { "usb3_uni_phy_sec_gcc_usb30_pipe_clk", &gcc, 0x7D }, + { "mc_cc_debug_mux", &gcc, 0xD3 }, /* gpu_cc_debug_mux is 0x153 */ - { "gpu_cc_ahb_clk", &gcc, 0x153, 2, &gpu_cc, 0x12, 2 }, - { "gpu_cc_cb_clk", &gcc, 0x153, 2, &gpu_cc, 0x26, 2 }, - { "gpu_cc_crc_ahb_clk", &gcc, 0x153, 2, &gpu_cc, 0x13, 2 }, - { "gpu_cc_cx_apb_clk", &gcc, 0x153, 2, &gpu_cc, 0x16, 2 }, - { "gpu_cc_cx_gmu_clk", &gcc, 0x153, 2, &gpu_cc, 0x1A, 2 }, - { "gpu_cc_cx_qdss_at_clk", &gcc, 0x153, 2, &gpu_cc, 0x14, 2 }, - { "gpu_cc_cx_qdss_trig_clk", &gcc, 0x153, 2, &gpu_cc, 0x19, 2 }, - { "gpu_cc_cx_qdss_tsctr_clk", &gcc, 0x153, 2, &gpu_cc, 0x15, 2 }, - { "gpu_cc_cx_snoc_dvm_clk", &gcc, 0x153, 2, &gpu_cc, 0x17, 2 }, - { "gpu_cc_cxo_aon_clk", &gcc, 0x153, 2, &gpu_cc, 0xB, 2 }, - { "gpu_cc_cxo_clk", &gcc, 0x153, 2, &gpu_cc, 0x1B, 2 }, - { "gpu_cc_freq_measure_clk", &gcc, 0x153, 2, &gpu_cc, 0xC, 2 }, - { "gpu_cc_gx_gmu_clk", &gcc, 0x153, 2, &gpu_cc, 0x11, 2 }, - { "gpu_cc_gx_qdss_tsctr_clk", &gcc, 0x153, 2, &gpu_cc, 0xF, 2 }, - { "gpu_cc_gx_vsense_clk", &gcc, 0x153, 2, &gpu_cc, 0xE, 2 }, - { "gpu_cc_hub_aon_clk", &gcc, 0x153, 2, &gpu_cc, 0x27, 2 }, - { "gpu_cc_hub_cx_int_clk", &gcc, 0x153, 2, &gpu_cc, 0x1C, 2 }, - { "gpu_cc_mnd1x_0_gfx3d_clk", &gcc, 0x153, 2, &gpu_cc, 0x21, 2 }, - { "gpu_cc_mnd1x_1_gfx3d_clk", &gcc, 0x153, 2, &gpu_cc, 0x22, 2 }, - { "gpu_cc_sleep_clk", &gcc, 0x153, 2, &gpu_cc, 0x18, 2 }, - { "measure_only_gpu_cc_cx_gfx3d_clk", &gcc, 0x153, 2, &gpu_cc, 0x1D, 2 }, - { "measure_only_gpu_cc_cx_gfx3d_slv_clk", &gcc, 0x153, 2, &gpu_cc, 0x1E, 2 }, - { "measure_only_gpu_cc_gx_gfx3d_clk", &gcc, 0x153, 2, &gpu_cc, 0xD, 2 }, + { "gpu_cc_ahb_clk", &gcc, 0x153, &gpu_cc, 0x12 }, + { "gpu_cc_cb_clk", &gcc, 0x153, &gpu_cc, 0x26 }, + { "gpu_cc_crc_ahb_clk", &gcc, 0x153, &gpu_cc, 0x13 }, + { "gpu_cc_cx_apb_clk", &gcc, 0x153, &gpu_cc, 0x16 }, + { "gpu_cc_cx_gmu_clk", &gcc, 0x153, &gpu_cc, 0x1A }, + { "gpu_cc_cx_qdss_at_clk", &gcc, 0x153, &gpu_cc, 0x14 }, + { "gpu_cc_cx_qdss_trig_clk", &gcc, 0x153, &gpu_cc, 0x19 }, + { "gpu_cc_cx_qdss_tsctr_clk", &gcc, 0x153, &gpu_cc, 0x15 }, + { "gpu_cc_cx_snoc_dvm_clk", &gcc, 0x153, &gpu_cc, 0x17 }, + { "gpu_cc_cxo_aon_clk", &gcc, 0x153, &gpu_cc, 0xB }, + { "gpu_cc_cxo_clk", &gcc, 0x153, &gpu_cc, 0x1B }, + { "gpu_cc_freq_measure_clk", &gcc, 0x153, &gpu_cc, 0xC }, + { "gpu_cc_gx_gmu_clk", &gcc, 0x153, &gpu_cc, 0x11 }, + { "gpu_cc_gx_qdss_tsctr_clk", &gcc, 0x153, &gpu_cc, 0xF }, + { "gpu_cc_gx_vsense_clk", &gcc, 0x153, &gpu_cc, 0xE }, + { "gpu_cc_hub_aon_clk", &gcc, 0x153, &gpu_cc, 0x27 }, + { "gpu_cc_hub_cx_int_clk", &gcc, 0x153, &gpu_cc, 0x1C }, + { "gpu_cc_mnd1x_0_gfx3d_clk", &gcc, 0x153, &gpu_cc, 0x21 }, + { "gpu_cc_mnd1x_1_gfx3d_clk", &gcc, 0x153, &gpu_cc, 0x22 }, + { "gpu_cc_sleep_clk", &gcc, 0x153, &gpu_cc, 0x18 }, + { "measure_only_gpu_cc_cx_gfx3d_clk", &gcc, 0x153, &gpu_cc, 0x1D }, + { "measure_only_gpu_cc_cx_gfx3d_slv_clk", &gcc, 0x153, &gpu_cc, 0x1E }, + { "measure_only_gpu_cc_gx_gfx3d_clk", &gcc, 0x153, &gpu_cc, 0xD }, /* video_cc_debug_mux is 0x5A */ - { "video_cc_mvs0_clk", &gcc, 0x5A, 2, &video_cc, 0x3, 3 }, - { "video_cc_mvs0c_clk", &gcc, 0x5A, 2, &video_cc, 0x1, 3 }, - { "video_cc_mvs1_clk", &gcc, 0x5A, 2, &video_cc, 0x5, 3 }, - { "video_cc_mvs1_div2_clk", &gcc, 0x5A, 2, &video_cc, 0x8, 3 }, - { "video_cc_mvs1c_clk", &gcc, 0x5A, 2, &video_cc, 0x9, 3 }, - { "video_cc_sleep_clk", &gcc, 0x5A, 2, &video_cc, 0xC, 3 }, + { "video_cc_mvs0_clk", &gcc, 0x5A, &video_cc, 0x3 }, + { "video_cc_mvs0c_clk", &gcc, 0x5A, &video_cc, 0x1 }, + { "video_cc_mvs1_clk", &gcc, 0x5A, &video_cc, 0x5 }, + { "video_cc_mvs1_div2_clk", &gcc, 0x5A, &video_cc, 0x8 }, + { "video_cc_mvs1c_clk", &gcc, 0x5A, &video_cc, 0x9 }, + { "video_cc_sleep_clk", &gcc, 0x5A, &video_cc, 0xC }, {} };