mirror of
https://github.com/linux-msm/debugcc.git
synced 2026-02-25 13:12:32 -08:00
Add QCM2290 / scuba
Also applies to QRB2210 / RB1 Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
This commit is contained in:
Konrad Dybcio
@@ -16,6 +16,7 @@ platforms = [
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'msm8996',
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'msm8998',
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'qcs404',
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'qcm2290',
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'sc8280xp',
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'sdm845',
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'sm6115',
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240
qcm2290.c
Normal file
240
qcm2290.c
Normal file
@@ -0,0 +1,240 @@
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// SPDX-License-Identifier: BSD-3-Clause
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/* Copyright (c) 2023, Linaro Limited */
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#include <sys/mman.h>
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#include <err.h>
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#include <fcntl.h>
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#include <stdio.h>
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#include <stdint.h>
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#include <stdlib.h>
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#include <string.h>
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#include <unistd.h>
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#include "debugcc.h"
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static struct gcc_mux gcc = {
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.mux = {
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.phys = 0x1400000,
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.size = 0x1f0000,
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.enable_reg = 0x30004,
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.enable_mask = BIT(0),
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.mux_reg = 0x62000,
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.mux_mask = 0x3ff,
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.div_reg = 0x30000,
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.div_mask = 0xf,
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.div_val = 4,
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},
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.xo_div4_reg = 0x28008,
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.debug_ctl_reg = 0x62038,
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.debug_status_reg = 0x6203c,
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};
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static struct debug_mux disp_cc = {
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.phys = 0x5f00000,
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.size = 0x20000,
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.block_name = "disp",
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.measure = measure_leaf,
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.parent = &gcc.mux,
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.parent_mux_val = 0x41,
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.enable_reg = 0x500c,
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.enable_mask = BIT(0),
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.mux_reg = 0x7000,
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.mux_mask = 0xff,
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.div_reg = 0x5008,
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.div_mask = 0x3,
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.div_val = 4,
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};
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static struct debug_mux gpu_cc = {
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.phys = 0x5990000,
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.size = 0x9000,
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.block_name = "gpu",
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.measure = measure_leaf,
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.parent = &gcc.mux,
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.parent_mux_val = 0xe3,
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.enable_reg = 0x1100,
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.enable_mask = BIT(0),
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.mux_reg = 0x1568,
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.mux_mask = 0xff,
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.div_reg = 0x10fc,
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.div_mask = 0x3,
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.div_val = 2,
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};
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static struct debug_mux mc_cc = {
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.phys = 0x447d000, /* 0x447d220 */
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.size = 0x1000, /* 0x100 */
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.block_name = "mc",
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.measure = measure_mccc,
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};
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static struct debug_mux cpu_cc = {
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.phys = 0xf111000,
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.size = 0x1000,
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.block_name = "cpu",
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.measure = measure_leaf,
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.parent = &gcc.mux,
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.parent_mux_val = 0xab,
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.enable_reg = 0x1c,
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.enable_mask = BIT(0),
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.mux_reg = 0x1c,
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.mux_mask = 0x3ff << 8,
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.mux_shift = 8,
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.div_reg = 0x1c,
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.div_mask = 0xf << 28,
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.div_shift = 28,
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};
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static struct measure_clk qcm2290_clocks[] = {
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{ "pwrcl_clk", &cpu_cc, 0x0 },
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// { "apcs_debug_mux", &gcc.mux, 0xab },
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// { "disp_cc_debug_mux", &gcc.mux, 0x41 },
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{ "gcc_ahb2phy_csi_clk", &gcc.mux, 0x62 },
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{ "gcc_ahb2phy_usb_clk", &gcc.mux, 0x63 },
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{ "gcc_bimc_gpu_axi_clk", &gcc.mux, 0x8d },
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{ "gcc_boot_rom_ahb_clk", &gcc.mux, 0x75 },
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{ "gcc_cam_throttle_nrt_clk", &gcc.mux, 0x4b },
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{ "gcc_cam_throttle_rt_clk", &gcc.mux, 0x4a },
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{ "gcc_camera_ahb_clk", &gcc.mux, 0x36 },
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{ "gcc_camera_xo_clk", &gcc.mux, 0x3e },
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{ "gcc_camss_axi_clk", &gcc.mux, 0x120 },
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{ "gcc_camss_camnoc_atb_clk", &gcc.mux, 0x122 },
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{ "gcc_camss_camnoc_nts_xo_clk", &gcc.mux, 0x123 },
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{ "gcc_camss_cci_0_clk", &gcc.mux, 0x11e },
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{ "gcc_camss_cphy_0_clk", &gcc.mux, 0x115 },
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{ "gcc_camss_cphy_1_clk", &gcc.mux, 0x116 },
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{ "gcc_camss_csi0phytimer_clk", &gcc.mux, 0x10b },
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{ "gcc_camss_csi1phytimer_clk", &gcc.mux, 0x10c },
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{ "gcc_camss_mclk0_clk", &gcc.mux, 0x10d },
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{ "gcc_camss_mclk1_clk", &gcc.mux, 0x10e },
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{ "gcc_camss_mclk2_clk", &gcc.mux, 0x10f },
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{ "gcc_camss_mclk3_clk", &gcc.mux, 0x110 },
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{ "gcc_camss_nrt_axi_clk", &gcc.mux, 0x124 },
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{ "gcc_camss_ope_ahb_clk", &gcc.mux, 0x11d },
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{ "gcc_camss_ope_clk", &gcc.mux, 0x11b },
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{ "gcc_camss_rt_axi_clk", &gcc.mux, 0x126 },
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{ "gcc_camss_tfe_0_clk", &gcc.mux, 0x111 },
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{ "gcc_camss_tfe_0_cphy_rx_clk", &gcc.mux, 0x113 },
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{ "gcc_camss_tfe_0_csid_clk", &gcc.mux, 0x117 },
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{ "gcc_camss_tfe_1_clk", &gcc.mux, 0x112 },
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{ "gcc_camss_tfe_1_cphy_rx_clk", &gcc.mux, 0x114 },
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{ "gcc_camss_tfe_1_csid_clk", &gcc.mux, 0x119 },
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{ "gcc_camss_top_ahb_clk", &gcc.mux, 0x11f },
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{ "gcc_cfg_noc_usb3_prim_axi_clk", &gcc.mux, 0x1c },
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{ "gcc_disp_ahb_clk", &gcc.mux, 0x37 },
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{ "gcc_disp_gpll0_div_clk_src", &gcc.mux, 0x46 },
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{ "gcc_disp_hf_axi_clk", &gcc.mux, 0x3c },
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{ "gcc_disp_throttle_core_clk", &gcc.mux, 0x48 },
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{ "gcc_disp_xo_clk", &gcc.mux, 0x3f },
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{ "gcc_gp1_clk", &gcc.mux, 0xb6 },
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{ "gcc_gp2_clk", &gcc.mux, 0xb7 },
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{ "gcc_gp3_clk", &gcc.mux, 0xb8 },
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{ "gcc_gpu_cfg_ahb_clk", &gcc.mux, 0xe1 },
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{ "gcc_gpu_gpll0_clk_src", &gcc.mux, 0xe7 },
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{ "gcc_gpu_gpll0_div_clk_src", &gcc.mux, 0xe8 },
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{ "gcc_gpu_memnoc_gfx_clk", &gcc.mux, 0xe4 },
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{ "gcc_gpu_snoc_dvm_gfx_clk", &gcc.mux, 0xe6 },
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{ "gcc_gpu_throttle_core_clk", &gcc.mux, 0xeb },
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{ "gcc_pdm2_clk", &gcc.mux, 0x72 },
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{ "gcc_pdm_ahb_clk", &gcc.mux, 0x70 },
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{ "gcc_pdm_xo4_clk", &gcc.mux, 0x71 },
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{ "gcc_pwm0_xo512_clk", &gcc.mux, 0x73 },
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{ "gcc_qmip_camera_nrt_ahb_clk", &gcc.mux, 0x39 },
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{ "gcc_qmip_camera_rt_ahb_clk", &gcc.mux, 0x47 },
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{ "gcc_qmip_disp_ahb_clk", &gcc.mux, 0x3a },
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{ "gcc_qmip_gpu_cfg_ahb_clk", &gcc.mux, 0xe9 },
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{ "gcc_qmip_video_vcodec_ahb_clk", &gcc.mux, 0x38 },
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{ "gcc_qupv3_wrap0_core_2x_clk", &gcc.mux, 0x69 },
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{ "gcc_qupv3_wrap0_core_clk", &gcc.mux, 0x68 },
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{ "gcc_qupv3_wrap0_s0_clk", &gcc.mux, 0x6a },
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{ "gcc_qupv3_wrap0_s1_clk", &gcc.mux, 0x6b },
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{ "gcc_qupv3_wrap0_s2_clk", &gcc.mux, 0x6c },
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{ "gcc_qupv3_wrap0_s3_clk", &gcc.mux, 0x6d },
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{ "gcc_qupv3_wrap0_s4_clk", &gcc.mux, 0x6e },
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{ "gcc_qupv3_wrap0_s5_clk", &gcc.mux, 0x6f },
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{ "gcc_qupv3_wrap_0_m_ahb_clk", &gcc.mux, 0x66 },
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{ "gcc_qupv3_wrap_0_s_ahb_clk", &gcc.mux, 0x67 },
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{ "gcc_sdcc1_ahb_clk", &gcc.mux, 0xef },
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{ "gcc_sdcc1_apps_clk", &gcc.mux, 0xee },
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{ "gcc_sdcc1_ice_core_clk", &gcc.mux, 0xf0 },
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{ "gcc_sdcc2_ahb_clk", &gcc.mux, 0x65 },
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{ "gcc_sdcc2_apps_clk", &gcc.mux, 0x64 },
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{ "gcc_sys_noc_cpuss_ahb_clk", &gcc.mux, 0x9 },
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{ "gcc_sys_noc_usb3_prim_axi_clk", &gcc.mux, 0x18 },
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{ "gcc_usb30_prim_master_clk", &gcc.mux, 0x5b },
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{ "gcc_usb30_prim_mock_utmi_clk", &gcc.mux, 0x5d },
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{ "gcc_usb30_prim_sleep_clk", &gcc.mux, 0x5c },
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{ "gcc_usb3_prim_phy_com_aux_clk", &gcc.mux, 0x5e },
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{ "gcc_usb3_prim_phy_pipe_clk", &gcc.mux, 0x5f },
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{ "gcc_vcodec0_axi_clk", &gcc.mux, 0x12c },
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{ "gcc_venus_ahb_clk", &gcc.mux, 0x12d },
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{ "gcc_venus_ctl_axi_clk", &gcc.mux, 0x12b },
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{ "gcc_video_ahb_clk", &gcc.mux, 0x35 },
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{ "gcc_video_axi0_clk", &gcc.mux, 0x3b },
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{ "gcc_video_throttle_core_clk", &gcc.mux, 0x49 },
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{ "gcc_video_vcodec0_sys_clk", &gcc.mux, 0x129 },
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{ "gcc_video_venus_ctl_clk", &gcc.mux, 0x127 },
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{ "gcc_video_xo_clk", &gcc.mux, 0x3d },
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// { "gpu_cc_debug_mux", &gcc.mux, 0xe3 },
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// { "mc_cc_debug_mux", &gcc.mux, 0x9b },
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{ "measure_only_cnoc_clk", &gcc.mux, 0x19 },
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{ "measure_only_ipa_2x_clk", &gcc.mux, 0xc2 },
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{ "measure_only_snoc_clk", &gcc.mux, 0x7 },
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{ "measure_only_qpic_clk", &gcc.mux, 0x9c },
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{ "measure_only_qpic_ahb_clk", &gcc.mux, 0x9e },
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{ "measure_only_hwkm_km_core_clk", &gcc.mux, 0xa0 },
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{ "measure_only_hwkm_ahb_clk", &gcc.mux, 0xa2 },
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{ "measure_only_pka_core_clk", &gcc.mux, 0xa3 },
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{ "measure_only_pka_ahb_clk", &gcc.mux, 0xa4 },
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{ "measure_only_cpuss_gnoc_clk", &gcc.mux, 0xa6 },
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{ "disp_cc_mdss_ahb_clk", &disp_cc, 0x1a },
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{ "disp_cc_mdss_byte0_clk", &disp_cc, 0x11 },
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{ "disp_cc_mdss_byte0_intf_clk", &disp_cc, 0x12 },
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{ "disp_cc_mdss_esc0_clk", &disp_cc, 0x13 },
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{ "disp_cc_mdss_mdp_clk", &disp_cc, 0xe },
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{ "disp_cc_mdss_mdp_lut_clk", &disp_cc, 0xf },
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{ "disp_cc_mdss_non_gdsc_ahb_clk", &disp_cc, 0x1b },
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{ "disp_cc_mdss_pclk0_clk", &disp_cc, 0xd },
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{ "disp_cc_mdss_vsync_clk", &disp_cc, 0x10 },
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{ "disp_cc_sleep_clk", &disp_cc, 0x24 },
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{ "disp_cc_xo_clk", &disp_cc, 0x23 },
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{ "gpu_cc_ahb_clk", &gpu_cc, 0x10 },
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{ "gpu_cc_crc_ahb_clk", &gpu_cc, 0x11 },
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{ "gpu_cc_cx_gfx3d_clk", &gpu_cc, 0x1a },
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{ "gpu_cc_cx_gmu_clk", &gpu_cc, 0x18 },
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{ "gpu_cc_cx_snoc_dvm_clk", &gpu_cc, 0x15 },
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{ "gpu_cc_cxo_aon_clk", &gpu_cc, 0xa },
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{ "gpu_cc_cxo_clk", &gpu_cc, 0x19 },
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{ "gpu_cc_gx_cxo_clk", &gpu_cc, 0xe },
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{ "gpu_cc_gx_gfx3d_clk", &gpu_cc, 0xb },
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{ "gpu_cc_sleep_clk", &gpu_cc, 0x16 },
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{ "mccc_clk", &mc_cc, 0x220 },
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{}
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};
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struct debugcc_platform qcm2290_debugcc = {
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"qcm2290",
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qcm2290_clocks,
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};
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