mirror of
https://github.com/linux-msm/debugcc.git
synced 2026-02-25 13:12:32 -08:00
Dmitry Baryshkov
GitHub
113
sc8280xp.c
113
sc8280xp.c
@@ -62,6 +62,26 @@ static struct gcc_mux gcc = {
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.debug_status_reg = 0x6203c,
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};
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static struct debug_mux cam_cc = {
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.phys = 0xad00000,
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.size = 0x20000,
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.block_name = "camcc",
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.measure = measure_leaf,
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.parent = &gcc.mux,
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.parent_mux_val = 0x70,
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.enable_reg = 0xd008,
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.enable_mask = BIT(0),
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.mux_reg = 0xd100,
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.mux_mask = 0xff,
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.div_reg = 0xd004,
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.div_mask = 0x0f,
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.div_val = 2,
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};
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static struct debug_mux disp0_cc = {
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.phys = 0xaf00000,
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.size = 0x20000,
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@@ -439,6 +459,99 @@ static struct measure_clk sc8280xp_clocks[] = {
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{ "disp1_cc_sleep_clk", &disp1_cc, 0x46 },
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{ "disp1_cc_xo_clk", &disp1_cc, 0x45 },
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{ "measure_only_mccc_clk", &mc_cc, 0x50 },
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{ "cam_cc_mclk0_clk", &cam_cc, 0x1 },
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{ "cam_cc_mclk1_clk", &cam_cc, 0x2 },
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{ "cam_cc_mclk2_clk", &cam_cc, 0x3 },
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{ "cam_cc_mclk3_clk", &cam_cc, 0x4 },
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{ "cam_cc_csi0phytimer_clk", &cam_cc, 0x5 },
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{ "cam_cc_csiphy0_clk", &cam_cc, 0x6},
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{ "cam_cc_csi1phytimer_clk", &cam_cc, 0x7},
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{ "cam_cc_csiphy1_clk", &cam_cc, 0x8},
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{ "cam_cc_csi2phytimer_clk", &cam_cc, 0x9},
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{ "cam_cc_csiphy2_clk", &cam_cc, 0xa},
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{ "cam_cc_bps_clk", &cam_cc, 0xb},
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{ "cam_cc_bps_axi_clk", &cam_cc, 0xc},
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{ "cam_cc_bps_areg_clk", &cam_cc, 0xd},
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{ "cam_cc_bps_ahb_clk", &cam_cc, 0xe},
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{ "cam_cc_ipe_0_clk", &cam_cc, 0xf},
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{ "cam_cc_ipe_0_axi_clk", &cam_cc, 0x10},
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{ "cam_cc_ipe_0_areg_clk", &cam_cc, 0x11},
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{ "cam_cc_ipe_0_ahb_clk", &cam_cc, 0x12},
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{ "cam_cc_ipe_1_clk", &cam_cc, 0x13},
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{ "cam_cc_ipe_1_axi_clk", &cam_cc, 0x14},
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{ "cam_cc_ipe_1_areg_clk", &cam_cc, 0x15},
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{ "cam_cc_ipe_1_ahb_clk", &cam_cc, 0x16},
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{ "cam_cc_ife_0_clk", &cam_cc, 0x17},
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{ "cam_cc_ife_0_dsp_clk", &cam_cc, 0x18},
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{ "cam_cc_ife_0_csid_clk", &cam_cc, 0x19},
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{ "cam_cc_ife_0_cphy_rx_clk", &cam_cc, 0x1a},
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{ "cam_cc_ife_0_axi_clk", &cam_cc, 0x1b},
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{ "cam_cc_spdm_ife_1_clk", &cam_cc, 0x1c},
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{ "cam_cc_ife_1_clk", &cam_cc, 0x1d},
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{ "cam_cc_ife_1_dsp_clk", &cam_cc, 0x1e},
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{ "cam_cc_ife_1_csid_clk", &cam_cc, 0x1f},
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{ "cam_cc_ife_1_cphy_rx_clk", &cam_cc, 0x20},
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{ "cam_cc_ife_1_axi_clk", &cam_cc, 0x21},
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{ "cam_cc_ife_lite_0_clk", &cam_cc, 0x22},
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{ "cam_cc_ife_lite_0_csid_clk", &cam_cc, 0x23},
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{ "cam_cc_ife_lite_0_cphy_rx_clk", &cam_cc, 0x24},
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{ "cam_cc_jpeg_clk", &cam_cc, 0x25},
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{ "cam_cc_icp_clk", &cam_cc, 0x26},
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{ "cam_cc_camnoc_axi_clk", &cam_cc, 0x27},
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{ "cam_cc_spdm_ife_1_csid_clk", &cam_cc, 0x28},
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{ "cam_cc_pll_lock_monitor_clk", &cam_cc, 0x29},
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{ "cam_cc_cci_0_clk", &cam_cc, 0x2a},
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{ "cam_cc_lrme_clk", &cam_cc, 0x2b},
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{ "cam_cc_cpas_ahb_clk", &cam_cc, 0x2c},
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{ "cam_cc_spdm_bps_clk", &cam_cc, 0x2d},
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{ "cam_cc_core_ahb_clk", &cam_cc, 0x2e},
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{ "cam_cc_spdm_ipe_0_clk", &cam_cc, 0x2f},
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{ "cam_cc_spdm_ipe_1_clk", &cam_cc, 0x30},
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{ "cam_cc_spdm_ife_0_clk", &cam_cc, 0x31},
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{ "cam_cc_spdm_ife_0_csid_clk", &cam_cc, 0x32},
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{ "cam_cc_camnoc_dcd_xo_clk", &cam_cc, 0x33},
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{ "cam_cc_spdm_jpeg_clk", &cam_cc, 0x34},
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{ "cam_cc_csi3phytimer_clk", &cam_cc, 0x35},
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{ "cam_cc_csiphy3_clk", &cam_cc, 0x36},
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{ "cam_cc_icp_ahb_clk", &cam_cc, 0x37},
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{ "cam_cc_ife_lite_1_clk", &cam_cc, 0x38},
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{ "cam_cc_ife_lite_1_csid_clk", &cam_cc, 0x39},
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{ "cam_cc_ife_lite_1_cphy_rx_clk", &cam_cc, 0x3a},
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{ "cam_cc_cci_1_clk", &cam_cc, 0x3b},
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{ "cam_cc_gdsc_clk", &cam_cc, 0x3c},
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{ "cam_cc_qdss_debug_clk", &cam_cc, 0x3d},
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{ "cam_cc_qdss_debug_xo_clk", &cam_cc, 0x3e},
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{ "cam_cc_sleep_clk", &cam_cc, 0x3f},
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{ "csiphy0_cam_cc_debug_clk", &cam_cc, 0x40},
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{ "csiphy1_cam_cc_debug_clk", &cam_cc, 0x41},
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{ "csiphy2_cam_cc_debug_clk", &cam_cc, 0x42},
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{ "csiphy3_cam_cc_debug_clk", &cam_cc, 0x43},
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{ "cam_cc_ife_2_clk", &cam_cc, 0x44},
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{ "cam_cc_spdm_ife_2_clk", &cam_cc, 0x45},
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{ "cam_cc_ife_2_dsp_clk", &cam_cc, 0x46},
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{ "cam_cc_ife_2_csid_clk", &cam_cc, 0x47},
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{ "cam_cc_spdm_ife_2_csid_clk", &cam_cc, 0x48},
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{ "cam_cc_ife_2_cphy_rx_clk", &cam_cc, 0x49},
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{ "cam_cc_ife_2_axi_clk", &cam_cc, 0x4a},
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{ "cam_cc_ife_3_clk", &cam_cc, 0x4b},
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{ "cam_cc_spdm_ife_3_clk", &cam_cc, 0x4c},
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{ "cam_cc_ife_3_dsp_clk", &cam_cc, 0x4d},
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{ "cam_cc_ife_3_csid_clk", &cam_cc, 0x4e},
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{ "cam_cc_spdm_ife_3_csid_clk", &cam_cc, 0x4f},
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{ "cam_cc_ife_3_cphy_rx_clk", &cam_cc, 0x50},
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{ "cam_cc_ife_3_axi_clk", &cam_cc, 0x51},
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{ "cam_cc_ife_lite_2_clk", &cam_cc, 0x55},
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{ "cam_cc_ife_lite_2_csid_clk", &cam_cc, 0x56},
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{ "cam_cc_ife_lite_2_cphy_rx_clk", &cam_cc, 0x57},
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{ "cam_cc_ife_lite_3_clk", &cam_cc, 0x58},
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{ "cam_cc_ife_lite_3_csid_clk", &cam_cc, 0x59},
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{ "cam_cc_ife_lite_3_cphy_rx_clk", &cam_cc, 0x5a},
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{ "cam_cc_cci_2_clk", &cam_cc, 0x5b},
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{ "cam_cc_cci_3_clk", &cam_cc, 0x5c},
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{ "cam_cc_mclk4_clk", &cam_cc, 0x5d},
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{ "cam_cc_mclk5_clk", &cam_cc, 0x5e},
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{ "cam_cc_mclk6_clk", &cam_cc, 0x5f},
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{ "cam_cc_mclk7_clk", &cam_cc, 0x60},
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{}
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};
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