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[A64] Mask vector SHR immediates

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Keep USHR constant shifts within lane width to avoid Oaknut ImmRange asserts.
This commit is contained in:
Will Martin
2026-01-21 12:11:02 +09:00
parent ab942708ff
commit a12dddcf27
1 changed files with 3 additions and 3 deletions
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src/xenia/cpu/backend/a64/a64_seq_vector.cc
+3 -3
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@@ -663,7 +663,7 @@ struct VECTOR_SHR_V128
}
if (all_same) {
// Every count is the same, so we can use USHR
e.USHR(i.dest.reg().B16(), i.src1.reg().B16(), shamt.u8[0]);
e.USHR(i.dest.reg().B16(), i.src1.reg().B16(), shamt.u8[0] & 0x7);
return;
}
e.ADD(e.GetNativeParam(1), SP, e.StashConstantV(1, i.src2.constant()));
@@ -687,7 +687,7 @@ struct VECTOR_SHR_V128
}
if (all_same) {
// Every count is the same, so we can use USHR
e.USHR(i.dest.reg().H8(), i.src1.reg().H8(), shamt.u16[0]);
e.USHR(i.dest.reg().H8(), i.src1.reg().H8(), shamt.u16[0] & 0xF);
return;
}
e.ADD(e.GetNativeParam(1), SP, e.StashConstantV(1, i.src2.constant()));
@@ -711,7 +711,7 @@ struct VECTOR_SHR_V128
}
if (all_same) {
// Every count is the same, so we can use USHR
e.USHR(i.dest.reg().S4(), i.src1.reg().S4(), shamt.u32[0]);
e.USHR(i.dest.reg().S4(), i.src1.reg().S4(), shamt.u32[0] & 0x1F);
return;
}
e.ADD(e.GetNativeParam(1), SP, e.StashConstantV(1, i.src2.constant()));