izzy/xemu
0
0
Fork 0
mirror of https://github.com/izzy2lost/xemu.git synced 2026-07-06 00:20:22 -07:00
Code Issues Packages Projects Releases Wiki Activity

Merge tag 'pull-target-arm-20250801' of https://gitlab.com/pm215/qemu into staging

Browse Source 
target-arm queue:
 * Add missing 64-bit PMCCNTR in AArch32 mode
 * Reinstate bogus AArch32 DBGDTRTX register for migration compat
 * fix big-endian handling of AArch64 FPU registers in gdbstub
 * fix handling of setting SVE registers from gdbstub
 * hw/intc/arm_gicv3_kvm: fix writing of enable/active/pending state to KVM
 * hw/display/framebuffer: Add cast to force 64x64 multiply
 * tests/tcg: Fix run for tests with specific plugin

# -----BEGIN PGP SIGNATURE-----
#
# iQJMBAABCAA3FiEE4aXFk81BneKOgxXPPCUl7RQ2DN4FAmiM4mgZHHBldGVyLm1h
# eWRlbGxAbGluYXJvLm9yZwAKCRA8JSXtFDYM3lH/D/iniJpHRVDVAvHcYe7vSgLl
# HHfdEro/lOJJbaktQwOwkSuyl5HFy3YoIg3/5K2kX40DRkeA/M1HWkaWpwpCUReV
# 6XS8fCDmxw5M0oncJsTD1cYxCAAHm/CSt2uvdwgHo6nU+vnEa85ml3Q57phLEkvl
# 2R6xjXDD2FY3Xi6l2Jvqhnx/y60D5YnZVo/G9jcwRI2kIvpwTxukge5rGRTeagzL
# fKwsgr8jThvWyzTJtd88n36uD8xiH8/IfHh+e0kGYfzPRjEGfN3rKh4OlyfRyv7D
# AVI8qgVz0ex7DEjJTCS2nNYmNhO8hTE+cybcsH6AU2e3V7/vqg3Lh0/1cWlmvGnR
# 8L0/RBy0exPI1kRABfjXPV4VtNSuByxp+F+s4LvUrxgnnbv29ldOnQNHn3BZJtZn
# OuuixZNa3/tJFa+2U20fPW+q2H9uhPhvLn5fhtCx1ucYONLMrWl3Z8Q3/qwbW+5e
# FR459UaVHUvqKDGL6cjnaQ3VclrsXngCbeBmLm7fDfniRf/4uIc3q6RzdwY3waj3
# t7D/+GmLwZzajEaCU1NcI+Uz+yO/wJhEXUtWAzm6xeowYfOEeZc1pRgGWSqy4qvi
# L9vKmZtRW5LvwLwpMLdcoB3BOIszSDy7AylX4onSWl3Vp3GYiOhYqv9OKlQoUGtu
# xjFCVDCB/0FPl9b+xoYK
# =lN06
# -----END PGP SIGNATURE-----
# gpg: Signature made Fri 01 Aug 2025 11:51:04 EDT
# gpg:                using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg:                issuer "peter.maydell@linaro.org"
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [full]
# gpg:                 aka "Peter Maydell <pmaydell@gmail.com>" [full]
# gpg:                 aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [full]
# gpg:                 aka "Peter Maydell <peter@archaic.org.uk>" [unknown]
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83  15CF 3C25 25ED 1436 0CDE

* tag 'pull-target-arm-20250801' of https://gitlab.com/pm215/qemu:
  tests/tcg: Fix run for tests with specific plugin
  target/arm: Fix handling of setting SVE registers from gdb
  target/arm: Fix big-endian handling of NEON gdb remote debugging
  target/arm: Reinstate bogus AArch32 DBGDTRTX register for migration compat
  hw/display/framebuffer: Add cast to force 64x64 multiply
  hw/intc/arm_gicv3_kvm: Write all 1's to clear enable/active
  hw/intc/arm_gicv3_kvm: Remove writes to ICPENDR registers
  target/arm: add support for 64-bit PMCCNTR in AArch32 mode

Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
This commit is contained in:
Stefan Hajnoczi
2025-08-04 08:56:59 -04:00
parent e5859141b9 676ab6a211
commit a666a84b32
9 changed files with 106 additions and 25 deletions
Download Patch File Download Diff File Expand all files Collapse all files
hw/display/framebuffer.c
+3 -3
View File
@@ -95,9 +95,9 @@ void framebuffer_update_display(
}
first = -1;
addr += i * src_width;
src += i * src_width;
dest += i * dest_row_pitch;
addr += (uint64_t)i * src_width;
src += (uint64_t)i * src_width;
dest += (uint64_t)i * dest_row_pitch;
snap = memory_region_snapshot_and_clear_dirty(mem, addr, src_width * rows,
DIRTY_MEMORY_VGA);
hw/intc/arm_gicv3_kvm.c
+2 -4
View File
@@ -295,7 +295,7 @@ static void kvm_dist_putbmp(GICv3State *s, uint32_t offset,
* the 1 bits.
*/
if (clroffset != 0) {
reg = 0;
reg = ~0;
kvm_gicd_access(s, clroffset, &reg, true);
clroffset += 4;
}
@@ -387,8 +387,6 @@ static void kvm_arm_gicv3_put(GICv3State *s)
reg = c->level;
kvm_gic_line_level_access(s, 0, ncpu, &reg, true);
reg = ~0;
kvm_gicr_access(s, GICR_ICPENDR0, ncpu, &reg, true);
reg = c->gicr_ipendr0;
kvm_gicr_access(s, GICR_ISPENDR0, ncpu, &reg, true);
@@ -445,7 +443,7 @@ static void kvm_arm_gicv3_put(GICv3State *s)
kvm_gic_put_line_level_bmp(s, s->level);
/* s->pending bitmap -> GICD_ISPENDRn */
kvm_dist_putbmp(s, GICD_ISPENDR, GICD_ICPENDR, s->pending);
kvm_dist_putbmp(s, GICD_ISPENDR, 0, s->pending);
/* s->active bitmap -> GICD_ISACTIVERn */
kvm_dist_putbmp(s, GICD_ISACTIVER, GICD_ICACTIVER, s->active);
target/arm/cpregs-pmu.c
+24 -5
View File
@@ -1067,11 +1067,6 @@ static const ARMCPRegInfo v7_pm_reginfo[] = {
.fgt = FGT_PMSELR_EL0,
.fieldoffset = offsetof(CPUARMState, cp15.c9_pmselr),
.writefn = pmselr_write, .raw_writefn = raw_write, },
{ .name = "PMCCNTR", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 0,
.access = PL0_RW, .resetvalue = 0, .type = ARM_CP_ALIAS | ARM_CP_IO,
.fgt = FGT_PMCCNTR_EL0,
.readfn = pmccntr_read, .writefn = pmccntr_write32,
.accessfn = pmreg_access_ccntr },
{ .name = "PMCCNTR_EL0", .state = ARM_CP_STATE_AA64,
.opc0 = 3, .opc1 = 3, .crn = 9, .crm = 13, .opc2 = 0,
.access = PL0_RW, .accessfn = pmreg_access_ccntr,
@@ -1211,6 +1206,23 @@ void define_pm_cpregs(ARMCPU *cpu)
define_one_arm_cp_reg(cpu, &pmcr);
define_one_arm_cp_reg(cpu, &pmcr64);
define_arm_cp_regs(cpu, v7_pm_reginfo);
/*
* 32-bit AArch32 PMCCNTR. We don't expose this to GDB if the
* new-in-v8 PMUv3 64-bit AArch32 PMCCNTR register is implemented
* (as that will provide the GDB user's view of "PMCCNTR").
*/
ARMCPRegInfo pmccntr = {
.name = "PMCCNTR",
.cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 0,
.access = PL0_RW, .accessfn = pmreg_access_ccntr,
.resetvalue = 0, .type = ARM_CP_ALIAS | ARM_CP_IO,
.fgt = FGT_PMCCNTR_EL0,
.readfn = pmccntr_read, .writefn = pmccntr_write32,
};
if (arm_feature(env, ARM_FEATURE_V8)) {
pmccntr.type |= ARM_CP_NO_GDB;
}
define_one_arm_cp_reg(cpu, &pmccntr);
for (unsigned i = 0, pmcrn = pmu_num_counters(env); i < pmcrn; i++) {
g_autofree char *pmevcntr_name = g_strdup_printf("PMEVCNTR%d", i);
@@ -1276,6 +1288,13 @@ void define_pm_cpregs(ARMCPU *cpu)
.access = PL0_R, .accessfn = pmreg_access, .type = ARM_CP_CONST,
.fgt = FGT_PMCEIDN_EL0,
.resetvalue = cpu->pmceid1 },
/* AArch32 64-bit PMCCNTR view: added in PMUv3 with Armv8 */
{ .name = "PMCCNTR", .state = ARM_CP_STATE_AA32,
.cp = 15, .crm = 9, .opc1 = 0,
.access = PL0_RW, .accessfn = pmreg_access_ccntr, .resetvalue = 0,
.type = ARM_CP_ALIAS | ARM_CP_IO | ARM_CP_64BIT,
.fgt = FGT_PMCCNTR_EL0, .readfn = pmccntr_read,
.writefn = pmccntr_write, },
};
define_arm_cp_regs(cpu, v8_pm_reginfo);
}
target/arm/debug_helper.c
+29
View File
@@ -940,6 +940,13 @@ static void dbgclaimclr_write(CPUARMState *env, const ARMCPRegInfo *ri,
env->cp15.dbgclaim &= ~(value & 0xFF);
}
static CPAccessResult access_bogus(CPUARMState *env, const ARMCPRegInfo *ri,
bool isread)
{
/* Always UNDEF, as if this cpreg didn't exist */
return CP_ACCESS_UNDEFINED;
}
static const ARMCPRegInfo debug_cp_reginfo[] = {
/*
* DBGDRAR, DBGDSAR: always RAZ since we don't implement memory mapped
@@ -1002,6 +1009,28 @@ static const ARMCPRegInfo debug_cp_reginfo[] = {
.opc0 = 2, .opc1 = 3, .crn = 0, .crm = 4, .opc2 = 0,
.access = PL0_RW, .accessfn = access_tdcc,
.type = ARM_CP_CONST, .resetvalue = 0 },
/*
* This is not a real AArch32 register. We used to incorrectly expose
* this due to a QEMU bug; to avoid breaking migration compatibility we
* need to continue to provide it so that we don't fail the inbound
* migration when it tells us about a sysreg that we don't have.
* We set an always-fails .accessfn, which means that the guest doesn't
* actually see this register (it will always UNDEF, identically to if
* there were no cpreg definition for it other than that we won't print
* a LOG_UNIMP message about it), and we set the ARM_CP_NO_GDB flag so the
* gdbstub won't see it either.
* (We can't just set .access = 0, because add_cpreg_to_hashtable()
* helpfully ignores cpregs which aren't accessible to the highest
* implemented EL.)
*
* TODO: implement a system for being able to describe "this register
* can be ignored if it appears in the inbound stream"; then we can
* remove this temporary hack.
*/
{ .name = "BOGUS_DBGDTR_EL0", .state = ARM_CP_STATE_AA32,
.cp = 14, .opc1 = 3, .crn = 0, .crm = 5, .opc2 = 0,
.access = PL0_RW, .accessfn = access_bogus,
.type = ARM_CP_CONST | ARM_CP_NO_GDB, .resetvalue = 0 },
/*
* OSECCR_EL1 provides a mechanism for an operating system
* to access the contents of EDECCR. EDECCR is not implemented though,
target/arm/gdbstub64.c
+28 -7
View File
@@ -115,8 +115,22 @@ int aarch64_gdb_set_fpu_reg(CPUState *cs, uint8_t *buf, int reg)
/* 128 bit FP register */
{
uint64_t *q = aa64_vfp_qreg(env, reg);
q[0] = ldq_le_p(buf);
q[1] = ldq_le_p(buf + 8);
/*
* On the wire these are target-endian 128 bit values.
* In the CPU state these are host-order uint64_t values
* with the least-significant one first. This means they're
* the other way around for target_big_endian() (which is
* only true for us for aarch64_be-linux-user).
*/
if (target_big_endian()) {
q[1] = ldq_p(buf);
q[0] = ldq_p(buf + 8);
} else{
q[0] = ldq_p(buf);
q[1] = ldq_p(buf + 8);
}
return 16;
}
case 32:
@@ -192,10 +206,17 @@ int aarch64_gdb_set_sve_reg(CPUState *cs, uint8_t *buf, int reg)
case 0 ... 31:
{
int vq, len = 0;
uint64_t *p = (uint64_t *) buf;
for (vq = 0; vq < cpu->sve_max_vq; vq++) {
env->vfp.zregs[reg].d[vq * 2 + 1] = *p++;
env->vfp.zregs[reg].d[vq * 2] = *p++;
if (target_big_endian()) {
env->vfp.zregs[reg].d[vq * 2 + 1] = ldq_p(buf);
buf += 8;
env->vfp.zregs[reg].d[vq * 2] = ldq_p(buf);
} else{
env->vfp.zregs[reg].d[vq * 2] = ldq_p(buf);
buf += 8;
env->vfp.zregs[reg].d[vq * 2 + 1] = ldq_p(buf);
}
buf += 8;
len += 16;
}
return len;
@@ -210,9 +231,9 @@ int aarch64_gdb_set_sve_reg(CPUState *cs, uint8_t *buf, int reg)
{
int preg = reg - 34;
int vq, len = 0;
uint64_t *p = (uint64_t *) buf;
for (vq = 0; vq < cpu->sve_max_vq; vq = vq + 4) {
env->vfp.pregs[preg].p[vq / 4] = *p++;
env->vfp.pregs[preg].p[vq / 4] = ldq_p(buf);
buf += 8;
len += 8;
}
return len;
tests/tcg/Makefile.target
+17 -3
View File
@@ -170,6 +170,10 @@ endif
PLUGINS=$(filter-out $(DISABLE_PLUGINS), \
$(patsubst %.c, lib%.so, $(notdir $(wildcard $(PLUGIN_SRC)/*.c))))
strip-plugin = $(wordlist 1, 1, $(subst -with-, ,$1))
extract-plugin = $(wordlist 2, 2, $(subst -with-, ,$1))
extract-test = $(subst run-plugin-,,$(wordlist 1, 1, $(subst -with-, ,$1)))
# We need to ensure expand the run-plugin-TEST-with-PLUGIN
# pre-requistes manually here as we can't use stems to handle it. We
# only expand MULTIARCH_TESTS which are common on most of our targets
@@ -179,6 +183,13 @@ PLUGINS=$(filter-out $(DISABLE_PLUGINS), \
ifneq ($(MULTIARCH_TESTS),)
# Extract extra tests from the extra test+plugin combination.
EXTRA_TESTS_WITH_PLUGIN=$(foreach test, \
$(EXTRA_RUNS_WITH_PLUGIN),$(call extract-test,$(test)))
# Exclude tests that were specified to run with specific plugins from the tests
# which can run with any plugin combination, so we don't run it twice.
MULTIARCH_TESTS:=$(filter-out $(EXTRA_TESTS_WITH_PLUGIN), $(MULTIARCH_TESTS))
NUM_PLUGINS := $(words $(PLUGINS))
NUM_TESTS := $(words $(MULTIARCH_TESTS))
@@ -186,19 +197,22 @@ define mod_plus_one
$(shell $(PYTHON) -c "print( ($(1) % $(2)) + 1 )")
endef
# Rules for running tests with any plugin combination, i.e., no specific plugin.
$(foreach _idx, $(shell seq 1 $(NUM_TESTS)), \
$(eval _test := $(word $(_idx), $(MULTIARCH_TESTS))) \
$(eval _plugin := $(word $(call mod_plus_one, $(_idx), $(NUM_PLUGINS)), $(PLUGINS))) \
$(eval run-plugin-$(_test)-with-$(_plugin): $(_test) $(_plugin)) \
$(eval RUN_TESTS+=run-plugin-$(_test)-with-$(_plugin)))
# Rules for running extra tests with specific plugins.
$(foreach f,$(EXTRA_RUNS_WITH_PLUGIN), \
$(eval $(f): $(call extract-test,$(f)) $(call extract-plugin,$(f))))
endif # MULTIARCH_TESTS
endif # CONFIG_PLUGIN
strip-plugin = $(wordlist 1, 1, $(subst -with-, ,$1))
extract-plugin = $(wordlist 2, 2, $(subst -with-, ,$1))
RUN_TESTS+=$(EXTRA_RUNS)
RUN_TESTS+=$(EXTRA_RUNS_WITH_PLUGIN)
# Some plugins need additional arguments above the default to fully
# exercise things. We can define them on a per-test basis here.
tests/tcg/multiarch/Makefile.target
+1 -1
View File
@@ -201,7 +201,7 @@ run-plugin-test-plugin-mem-access-with-libmem.so: \
$(SRC_PATH)/tests/tcg/multiarch/check-plugin-output.sh \
$(QEMU) $<
EXTRA_RUNS += run-plugin-test-plugin-mem-access-with-libmem.so
EXTRA_RUNS_WITH_PLUGIN += run-plugin-test-plugin-mem-access-with-libmem.so
endif
# Update TESTS
tests/tcg/multiarch/system/Makefile.softmmu-target
+1 -1
View File
@@ -77,5 +77,5 @@ run-plugin-memory-with-libmem.so: memory libmem.so
run-plugin-memory-with-libmem.so: PLUGIN_ARGS=$(COMMA)region-summary=true
run-plugin-memory-with-libmem.so: CHECK_PLUGIN_OUTPUT_COMMAND=$(MULTIARCH_SYSTEM_SRC)/validate-memory-counts.py $@.out
EXTRA_RUNS += run-plugin-memory-with-libmem.so
EXTRA_RUNS_WITH_PLUGIN += run-plugin-memory-with-libmem.so
endif
tests/tcg/x86_64/Makefile.softmmu-target
+1 -1
View File
@@ -40,5 +40,5 @@ run-plugin-patch-target-with-libpatch.so: \
run-plugin-patch-target-with-libpatch.so: \
CHECK_PLUGIN_OUTPUT_COMMAND=$(X64_SYSTEM_SRC)/validate-patch.py $@.out
run-plugin-patch-target-with-libpatch.so: patch-target libpatch.so
EXTRA_RUNS+=run-plugin-patch-target-with-libpatch.so
EXTRA_RUNS_WITH_PLUGIN+=run-plugin-patch-target-with-libpatch.so
endif