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Merge tag 'pull-ppc-for-20250928-20250929' of https://gitlab.com/harshpb/qemu into staging

Browse Source 
ppc queue for 20250928

* Support for PowerNV11 and PPE42 CPU/Machines.
* Deprecation of Power8E and Power8NVL
* Decodetree patches for some floating-point instructions
* Minor bug fixes, improvements in ppc/spapr/xive/xics.

# -----BEGIN PGP SIGNATURE-----
#
# iQIzBAABCAAdFiEEa4EM1tK+EPOIPSFCRUTplPnWj7sFAmjZgYQACgkQRUTplPnW
# j7uNJQ/8Cbr3xqyCyyqL+MM+Ze1PbXe4xSgdg13A1sNU3IHTffB77DCQVOxjudUS
# uo+XHVFssc4SKDZYjEzXFnYpzRpbZzfcuhG4kgn9QQ3VyKP+2xe6kWLleDbB6ds1
# e9ZAW6Ryk4R3ZFLnZzGfEdltliaoIn6zy4R25oJfJUgIRt0Xz++GBxll+Tdr8Exy
# qstvvyyjeTiIS3kA1zk6fbhDRJKKBsA0L1G1Pk6AuTMKa1RRTCniA36idnGVFAuY
# ef8WCEQYQS0do9Ytai06Tp1QNRVMG2y+AsKbSQRMi92lFfn+qhvA29OJd5TNvXtp
# LNiIfXHo3jLjGBUP13iVN8b8udWdis9BayvA/OwDaKWgononEHb9nqJgzVJR4n7t
# DxxUxcSCiEXOpObtklrKhi1nDt16nXPZ/bnnreMSWzxHBZK1My7qnI3S0hA7c11z
# YgssB5wJbRaETaEVzQfWfAcSaPpXBzBEXOAJcbd+Ni6w9SxXz2OrhckTOvfrXpmI
# XQ1KFUCkmTtXF1qB+oEihlrvG2qjdGuleRZdyiktaM2psBFgN/2gHl3S+JjL9kiY
# 9FdBffr/2K604l7EQkAYWixe2WMMsjHVHpuxJ7opG7MMSXJZq9cXKIK+tbkSNoRO
# Ia6Qr6eWJWjFF3y4OZCbYAOVU77ez6lo7kRj0e99fOjxfI+UuWU=
# =Fjdq
# -----END PGP SIGNATURE-----
# gpg: Signature made Sun 28 Sep 2025 11:42:12 AM PDT
# gpg:                using RSA key 6B810CD6D2BE10F3883D21424544E994F9D68FBB
# gpg: Good signature from "Harsh Prateek Bora <harsh.prateek.bora@gmail.com>" [undefined]
# gpg:                 aka "Harsh Prateek Bora <harshpb@linux.ibm.com>" [undefined]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg:          There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 6B81 0CD6 D2BE 10F3 883D  2142 4544 E994 F9D6 8FBB

* tag 'pull-ppc-for-20250928-20250929' of https://gitlab.com/harshpb/qemu: (27 commits)
  target/ppc: use MAKE_64BIT_MASK for mcrfs exception clear mask
  target/ppc: Deprecate Power8E and Power8NVL
  target/ppc: Introduce macro for deprecating PowerPC CPUs
  target/ppc: Move remaining floating-point move instructions to decodetree.
  target/ppc: Move floating-point move instructions to decodetree.
  target/ppc: Move floating-point compare instructions to decodetree.
  target/ppc: Move floating-point rounding and conversion instructions to decodetree.
  ppc/xive2: Fix integer overflow warning in xive2_redistribute()
  ppc/spapr: init lrdr-capapcity phys with ram size if maxmem not provided
  hw/intc/xics: Add missing call to register vmstate_icp_server
  tests/functional: Add test for IBM PPE42 instructions
  hw/ppc: Add a test machine for the IBM PPE42 CPU
  hw/ppc: Support for an IBM PPE42 CPU decrementer
  target/ppc: Add IBM PPE42 special instructions
  target/ppc: Support for IBM PPE42 MMU
  target/ppc: Add IBM PPE42 exception model
  target/ppc: IBM PPE42 exception flags and regs
  target/ppc: Add IBM PPE42 family of processors
  target/ppc: IBM PPE42 general regs and flags
  tests/powernv: Add PowerNV test for Power11
  ...

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson
2025-09-29 07:25:28 -07:00
parent 4975b64efb 6c51df580d
commit 9b16edec6e
36 changed files with 2411 additions and 372 deletions
Download Patch File Download Diff File Expand all files Collapse all files
MAINTAINERS
+7
View File
@@ -1530,6 +1530,13 @@ F: include/hw/pci-host/grackle.h
F: pc-bios/qemu_vga.ndrv
F: tests/functional/ppc/test_mac.py
PPE42
M: Glenn Miles <milesg@linux.ibm.com>
L: qemu-ppc@nongnu.org
S: Odd Fixes
F: hw/ppc/ppe42_machine.c
F: tests/functional/ppc/test_ppe42.py
PReP
M: Hervé Poussineau <hpoussin@reactos.org>
L: qemu-ppc@nongnu.org
docs/about/deprecated.rst
+9
View File
@@ -253,6 +253,15 @@ embedded 405 for power management (OCC) and other internal tasks, it
is theoretically possible to use QEMU to model them. Let's keep the
CPU implementation for a while before removing all support.
Power8E and Power8NVL CPUs and corresponding Pnv chips (since 10.1)
'''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''
The Power8E and Power8NVL variants of Power8 are not really useful anymore
in qemu, and are old and unmaintained now.
The CPUs as well as corresponding Power8NVL and Power8E PnvChips will also
be considered deprecated.
System emulator machines
------------------------
docs/system/ppc/powernv.rst
+5 -4
View File
@@ -1,5 +1,5 @@
PowerNV family boards (``powernv8``, ``powernv9``, ``powernv10``)
==================================================================
PowerNV family boards (``powernv8``, ``powernv9``, ``powernv10``, ``powernv11``)
================================================================================
PowerNV (as Non-Virtualized) is the "bare metal" platform using the
OPAL firmware. It runs Linux on IBM and OpenPOWER systems and it can
@@ -15,11 +15,12 @@ beyond the scope of what QEMU addresses today.
Supported devices
-----------------
* Multi processor support for POWER8, POWER8NVL and POWER9.
* Multi processor support for POWER8, POWER8NVL, POWER9, Power10 and Power11.
* XSCOM, serial communication sideband bus to configure chiplets.
* Simple LPC Controller.
* Processor Service Interface (PSI) Controller.
* Interrupt Controller, XICS (POWER8) and XIVE (POWER9) and XIVE2 (Power10).
* Interrupt Controller, XICS (POWER8) and XIVE (POWER9) and XIVE2 (Power10 &
Power11).
* POWER8 PHB3 PCIe Host bridge and POWER9 PHB4 PCIe Host bridge.
* Simple OCC is an on-chip micro-controller used for power management tasks.
* iBT device to handle BMC communication, with the internal BMC simulator
hw/intc/pnv_xive2.c
+2 -2
View File
@@ -110,8 +110,8 @@ static PnvXive2 *pnv_xive2_get_remote(uint32_t vsd_type, hwaddr fwd_addr)
int i;
for (i = 0; i < pnv->num_chips; i++) {
Pnv10Chip *chip10 = PNV10_CHIP(pnv->chips[i]);
PnvXive2 *xive = &chip10->xive;
PnvChipClass *k = PNV_CHIP_GET_CLASS(pnv->chips[i]);
PnvXive2 *xive = PNV_XIVE2(k->intc_get(pnv->chips[i]));
/*
* Is this the XIVE matching the forwarded VSD address is for this
hw/intc/xics.c
+2
View File
@@ -335,6 +335,8 @@ static void icp_realize(DeviceState *dev, Error **errp)
return;
}
}
vmstate_register(NULL, icp->cs->cpu_index, &vmstate_icp_server, icp);
}
static void icp_unrealize(DeviceState *dev)
hw/intc/xive2.c
+31 -14
View File
@@ -95,6 +95,35 @@ static void xive2_nvgc_set_backlog(Xive2Nvgc *nvgc, uint8_t priority,
}
}
static uint32_t xive2_nvgc_get_idx(uint32_t nvp_idx, uint8_t group)
{
uint32_t nvgc_idx;
if (group > 0) {
nvgc_idx = (nvp_idx & (0xffffffffULL << group)) |
((1 << (group - 1)) - 1);
} else {
nvgc_idx = nvp_idx;
}
return nvgc_idx;
}
static uint8_t xive2_nvgc_get_blk(uint8_t nvp_blk, uint8_t crowd)
{
uint8_t nvgc_blk;
if (crowd > 0) {
crowd = (crowd == 3) ? 4 : crowd;
nvgc_blk = (nvp_blk & (0xffffffffULL << crowd)) |
((1 << (crowd - 1)) - 1);
} else {
nvgc_blk = nvp_blk;
}
return nvgc_blk;
}
uint64_t xive2_presenter_nvgc_backlog_op(XivePresenter *xptr,
bool crowd,
uint8_t blk, uint32_t idx,
@@ -638,20 +667,8 @@ static void xive2_redistribute(Xive2Router *xrtr, XiveTCTX *tctx, uint8_t ring)
trace_xive_redistribute(tctx->cs->cpu_index, ring, nvp_blk, nvp_idx);
/* convert crowd/group to blk/idx */
if (group > 0) {
nvgc_idx = (nvp_idx & (0xffffffff << group)) |
((1 << (group - 1)) - 1);
} else {
nvgc_idx = nvp_idx;
}
if (crowd > 0) {
crowd = (crowd == 3) ? 4 : crowd;
nvgc_blk = (nvp_blk & (0xffffffff << crowd)) |
((1 << (crowd - 1)) - 1);
} else {
nvgc_blk = nvp_blk;
}
nvgc_idx = xive2_nvgc_get_idx(nvp_idx, group);
nvgc_blk = xive2_nvgc_get_blk(nvp_blk, crowd);
/* Use blk/idx to retrieve the NVGC */
if (xive2_router_get_nvgc(xrtr, crowd, nvgc_blk, nvgc_idx, &nvgc)) {
hw/ppc/Kconfig
+5
View File
@@ -44,6 +44,11 @@ config POWERNV
select SSI_M25P80
select PNV_SPI
config PPC405
bool
default y
depends on PPC
config PPC440
bool
default y
hw/ppc/meson.build
+2
View File
@@ -57,6 +57,8 @@ ppc_ss.add(when: 'CONFIG_POWERNV', if_true: files(
'pnv_n1_chiplet.c',
))
# PowerPC 4xx boards
ppc_ss.add(when: 'CONFIG_PPC405', if_true: files(
'ppe42_machine.c'))
ppc_ss.add(when: 'CONFIG_PPC440', if_true: files(
'ppc440_bamboo.c',
'ppc440_uc.c'))
hw/ppc/pnv.c
+560
View File
File diff suppressed because it is too large Load Diff
hw/ppc/pnv_chiptod.c
+59
View File
@@ -210,6 +210,22 @@ static void chiptod_power10_broadcast_ttype(PnvChipTOD *sender,
}
}
static void chiptod_power11_broadcast_ttype(PnvChipTOD *sender,
uint32_t trigger)
{
PnvMachineState *pnv = PNV_MACHINE(qdev_get_machine());
int i;
for (i = 0; i < pnv->num_chips; i++) {
Pnv11Chip *chip11 = PNV11_CHIP(pnv->chips[i]);
PnvChipTOD *chiptod = &chip11->chiptod;
if (chiptod != sender) {
chiptod_receive_ttype(chiptod, trigger);
}
}
}
static PnvCore *pnv_chip_get_core_by_xscom_base(PnvChip *chip,
uint32_t xscom_base)
{
@@ -283,6 +299,12 @@ static PnvCore *chiptod_power10_tx_ttype_target(PnvChipTOD *chiptod,
}
}
static PnvCore *chiptod_power11_tx_ttype_target(PnvChipTOD *chiptod,
uint64_t val)
{
return chiptod_power10_tx_ttype_target(chiptod, val);
}
static void pnv_chiptod_xscom_write(void *opaque, hwaddr addr,
uint64_t val, unsigned size)
{
@@ -520,6 +542,42 @@ static const TypeInfo pnv_chiptod_power10_type_info = {
}
};
static int pnv_chiptod_power11_dt_xscom(PnvXScomInterface *dev, void *fdt,
int xscom_offset)
{
const char compat[] = "ibm,power-chiptod\0ibm,power11-chiptod";
return pnv_chiptod_dt_xscom(dev, fdt, xscom_offset, compat, sizeof(compat));
}
static void pnv_chiptod_power11_class_init(ObjectClass *klass, const void *data)
{
PnvChipTODClass *pctc = PNV_CHIPTOD_CLASS(klass);
DeviceClass *dc = DEVICE_CLASS(klass);
PnvXScomInterfaceClass *xdc = PNV_XSCOM_INTERFACE_CLASS(klass);
dc->desc = "PowerNV ChipTOD Controller (Power11)";
device_class_set_props(dc, pnv_chiptod_properties);
xdc->dt_xscom = pnv_chiptod_power11_dt_xscom;
pctc->broadcast_ttype = chiptod_power11_broadcast_ttype;
pctc->tx_ttype_target = chiptod_power11_tx_ttype_target;
pctc->xscom_size = PNV_XSCOM_CHIPTOD_SIZE;
}
static const TypeInfo pnv_chiptod_power11_type_info = {
.name = TYPE_PNV11_CHIPTOD,
.parent = TYPE_PNV_CHIPTOD,
.instance_size = sizeof(PnvChipTOD),
.class_init = pnv_chiptod_power11_class_init,
.interfaces = (const InterfaceInfo[]) {
{ TYPE_PNV_XSCOM_INTERFACE },
{ }
}
};
static void pnv_chiptod_reset(void *dev)
{
PnvChipTOD *chiptod = PNV_CHIPTOD(dev);
@@ -579,6 +637,7 @@ static void pnv_chiptod_register_types(void)
type_register_static(&pnv_chiptod_type_info);
type_register_static(&pnv_chiptod_power9_type_info);
type_register_static(&pnv_chiptod_power10_type_info);
type_register_static(&pnv_chiptod_power11_type_info);
}
type_init(pnv_chiptod_register_types);
hw/ppc/pnv_core.c
+17
View File
@@ -473,6 +473,11 @@ static void pnv_core_power10_class_init(ObjectClass *oc, const void *data)
pcc->xscom_size = PNV10_XSCOM_EC_SIZE;
}
static void pnv_core_power11_class_init(ObjectClass *oc, const void *data)
{
pnv_core_power10_class_init(oc, data);
}
static void pnv_core_class_init(ObjectClass *oc, const void *data)
{
DeviceClass *dc = DEVICE_CLASS(oc);
@@ -504,6 +509,7 @@ static const TypeInfo pnv_core_infos[] = {
DEFINE_PNV_CORE_TYPE(power8, "power8nvl_v1.0"),
DEFINE_PNV_CORE_TYPE(power9, "power9_v2.2"),
DEFINE_PNV_CORE_TYPE(power10, "power10_v2.0"),
DEFINE_PNV_CORE_TYPE(power11, "power11_v2.0"),
};
DEFINE_TYPES(pnv_core_infos)
@@ -725,6 +731,12 @@ static void pnv_quad_power10_class_init(ObjectClass *oc, const void *data)
pqc->xscom_qme_size = PNV10_XSCOM_QME_SIZE;
}
static void pnv_quad_power11_class_init(ObjectClass *oc, const void *data)
{
/* Power11 quad is similar to Power10 quad */
pnv_quad_power10_class_init(oc, data);
}
static void pnv_quad_class_init(ObjectClass *oc, const void *data)
{
DeviceClass *dc = DEVICE_CLASS(oc);
@@ -752,6 +764,11 @@ static const TypeInfo pnv_quad_infos[] = {
.name = PNV_QUAD_TYPE_NAME("power10"),
.class_init = pnv_quad_power10_class_init,
},
{
.parent = TYPE_PNV_QUAD,
.name = PNV_QUAD_TYPE_NAME("power11"),
.class_init = pnv_quad_power11_class_init,
},
};
DEFINE_TYPES(pnv_quad_infos);
hw/ppc/ppc_booke.c
+6 -1
View File
@@ -352,7 +352,12 @@ void ppc_booke_timers_init(PowerPCCPU *cpu, uint32_t freq, uint32_t flags)
booke_timer = g_new0(booke_timer_t, 1);
cpu->env.tb_env = tb_env;
tb_env->flags = flags | PPC_TIMER_BOOKE | PPC_DECR_ZERO_TRIGGERED;
if (flags & PPC_TIMER_PPE) {
/* PPE's use a modified version of the booke behavior */
tb_env->flags = flags | PPC_DECR_UNDERFLOW_TRIGGERED;
} else {
tb_env->flags = flags | PPC_TIMER_BOOKE | PPC_DECR_ZERO_TRIGGERED;
}
tb_env->tb_freq = freq;
tb_env->decr_freq = freq;
hw/ppc/ppe42_machine.c
+101
View File
@@ -0,0 +1,101 @@
/*
* Test Machine for the IBM PPE42 processor
*
* Copyright (c) 2025, IBM Corporation.
*
* SPDX-License-Identifier: GPL-2.0-or-later
*/
#include "qemu/osdep.h"
#include "qemu/units.h"
#include "qemu/error-report.h"
#include "system/address-spaces.h"
#include "hw/boards.h"
#include "hw/ppc/ppc.h"
#include "system/system.h"
#include "system/reset.h"
#include "system/kvm.h"
#include "qapi/error.h"
#define TYPE_PPE42_MACHINE MACHINE_TYPE_NAME("ppe42_machine")
typedef MachineClass Ppe42MachineClass;
typedef struct Ppe42MachineState Ppe42MachineState;
DECLARE_OBJ_CHECKERS(Ppe42MachineState, Ppe42MachineClass,
PPE42_MACHINE, TYPE_PPE42_MACHINE)
struct Ppe42MachineState {
MachineState parent_obj;
PowerPCCPU cpu;
};
static void main_cpu_reset(void *opaque)
{
PowerPCCPU *cpu = opaque;
cpu_reset(CPU(cpu));
}
static void ppe42_machine_init(MachineState *machine)
{
Ppe42MachineState *pms = PPE42_MACHINE(machine);
PowerPCCPU *cpu = &pms->cpu;
if (kvm_enabled()) {
error_report("machine %s does not support the KVM accelerator",
MACHINE_GET_CLASS(machine)->name);
exit(EXIT_FAILURE);
}
if (machine->ram_size > 512 * KiB) {
error_report("RAM size more than 512 KiB is not supported");
exit(1);
}
/* init CPU */
object_initialize_child(OBJECT(pms), "cpu", cpu, machine->cpu_type);
if (!qdev_realize(DEVICE(cpu), NULL, &error_fatal)) {
return;
}
qemu_register_reset(main_cpu_reset, cpu);
/* This sets the decrementer timebase */
ppc_booke_timers_init(cpu, 37500000, PPC_TIMER_PPE);
/* RAM */
memory_region_add_subregion(get_system_memory(), 0xfff80000, machine->ram);
}
static void ppe42_machine_class_init(ObjectClass *oc, const void *data)
{
MachineClass *mc = MACHINE_CLASS(oc);
static const char * const valid_cpu_types[] = {
POWERPC_CPU_TYPE_NAME("PPE42"),
POWERPC_CPU_TYPE_NAME("PPE42X"),
POWERPC_CPU_TYPE_NAME("PPE42XM"),
NULL,
};
mc->desc = "PPE42 Test Machine";
mc->init = ppe42_machine_init;
mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("PPE42XM");
mc->valid_cpu_types = valid_cpu_types;
mc->default_ram_id = "ram";
mc->default_ram_size = 512 * KiB;
}
static const TypeInfo ppe42_machine_info = {
.name = TYPE_PPE42_MACHINE,
.parent = TYPE_MACHINE,
.instance_size = sizeof(Ppe42MachineState),
.class_init = ppe42_machine_class_init,
.class_size = sizeof(Ppe42MachineClass),
};
static void ppe42_machine_register_types(void)
{
type_register_static(&ppe42_machine_info);
}
type_init(ppe42_machine_register_types);
hw/ppc/spapr.c
+7 -4
View File
@@ -907,6 +907,7 @@ static void spapr_dt_rtas(SpaprMachineState *spapr, void *fdt)
int rtas;
GString *hypertas = g_string_sized_new(256);
GString *qemu_hypertas = g_string_sized_new(256);
uint64_t max_device_addr = 0;
uint32_t lrdr_capacity[] = {
0,
0,
@@ -917,13 +918,15 @@ static void spapr_dt_rtas(SpaprMachineState *spapr, void *fdt)
/* Do we have device memory? */
if (MACHINE(spapr)->device_memory) {
uint64_t max_device_addr = MACHINE(spapr)->device_memory->base +
max_device_addr = MACHINE(spapr)->device_memory->base +
memory_region_size(&MACHINE(spapr)->device_memory->mr);
lrdr_capacity[0] = cpu_to_be32(max_device_addr >> 32);
lrdr_capacity[1] = cpu_to_be32(max_device_addr & 0xffffffff);
} else if (ms->ram_size == ms->maxram_size) {
max_device_addr = ms->ram_size;
}
lrdr_capacity[0] = cpu_to_be32(max_device_addr >> 32);
lrdr_capacity[1] = cpu_to_be32(max_device_addr & 0xffffffff);
_FDT(rtas = fdt_add_subnode(fdt, 0, "rtas"));
/* hypertas */
include/hw/ppc/pnv.h
+38
View File
@@ -33,6 +33,7 @@ typedef struct PnvChip PnvChip;
typedef struct Pnv8Chip Pnv8Chip;
typedef struct Pnv9Chip Pnv9Chip;
typedef struct Pnv10Chip Pnv10Chip;
typedef struct Pnv10Chip Pnv11Chip;
#define PNV_CHIP_TYPE_SUFFIX "-" TYPE_PNV_CHIP
#define PNV_CHIP_TYPE_NAME(cpu_model) cpu_model PNV_CHIP_TYPE_SUFFIX
@@ -57,6 +58,10 @@ DECLARE_INSTANCE_CHECKER(PnvChip, PNV_CHIP_POWER9,
DECLARE_INSTANCE_CHECKER(PnvChip, PNV_CHIP_POWER10,
TYPE_PNV_CHIP_POWER10)
#define TYPE_PNV_CHIP_POWER11 PNV_CHIP_TYPE_NAME("power11_v2.0")
DECLARE_INSTANCE_CHECKER(PnvChip, PNV_CHIP_POWER11,
TYPE_PNV_CHIP_POWER11)
PnvCore *pnv_chip_find_core(PnvChip *chip, uint32_t core_id);
PowerPCCPU *pnv_chip_find_cpu(PnvChip *chip, uint32_t pir);
@@ -252,4 +257,37 @@ void pnv_bmc_set_pnor(IPMIBmc *bmc, PnvPnor *pnor);
#define PNV10_HOMER_BASE(chip) \
(0x300ffd800000ll + ((uint64_t)(chip)->chip_id) * PNV_HOMER_SIZE)
/* Power11 */
#define PNV11_XSCOM_SIZE PNV10_XSCOM_SIZE
#define PNV11_XSCOM_BASE(chip) PNV10_XSCOM_BASE(chip)
#define PNV11_LPCM_SIZE PNV10_LPCM_SIZE
#define PNV11_LPCM_BASE(chip) PNV10_LPCM_BASE(chip)
#define PNV11_PSIHB_ESB_SIZE PNV10_PSIHB_ESB_SIZE
#define PNV11_PSIHB_ESB_BASE(chip) PNV10_PSIHB_ESB_BASE(chip)
#define PNV11_PSIHB_SIZE PNV10_PSIHB_SIZE
#define PNV11_PSIHB_BASE(chip) PNV10_PSIHB_BASE(chip)
#define PNV11_XIVE2_IC_SIZE PNV10_XIVE2_IC_SIZE
#define PNV11_XIVE2_IC_BASE(chip) PNV10_XIVE2_IC_BASE(chip)
#define PNV11_XIVE2_TM_SIZE PNV10_XIVE2_TM_SIZE
#define PNV11_XIVE2_TM_BASE(chip) PNV10_XIVE2_TM_BASE(chip)
#define PNV11_XIVE2_NVC_SIZE PNV10_XIVE2_NVC_SIZE
#define PNV11_XIVE2_NVC_BASE(chip) PNV10_XIVE2_NVC_BASE(chip)
#define PNV11_XIVE2_NVPG_SIZE PNV10_XIVE2_NVPG_SIZE
#define PNV11_XIVE2_NVPG_BASE(chip) PNV10_XIVE2_NVPG_BASE(chip)
#define PNV11_XIVE2_ESB_SIZE PNV10_XIVE2_ESB_SIZE
#define PNV11_XIVE2_ESB_BASE(chip) PNV10_XIVE2_ESB_BASE(chip)
#define PNV11_XIVE2_END_SIZE PNV10_XIVE2_END_SIZE
#define PNV11_XIVE2_END_BASE(chip) PNV10_XIVE2_END_BASE(chip)
#define PNV11_OCC_SENSOR_BASE(chip) PNV10_OCC_SENSOR_BASE(chip)
#endif /* PPC_PNV_H */
include/hw/ppc/pnv_chip.h
+8
View File
@@ -141,6 +141,13 @@ struct Pnv10Chip {
#define PNV10_PIR2CHIP(pir) (((pir) >> 8) & 0x7f)
#define PNV10_PIR2THREAD(pir) (((pir) & 0x7f))
#define TYPE_PNV11_CHIP "pnv11-chip"
DECLARE_INSTANCE_CHECKER(Pnv11Chip, PNV11_CHIP,
TYPE_PNV11_CHIP)
/* Power11 core is same as Power10 */
typedef struct Pnv10Chip Pnv11Chip;
struct PnvChipClass {
/*< private >*/
SysBusDeviceClass parent_class;
@@ -163,6 +170,7 @@ struct PnvChipClass {
void (*intc_reset)(PnvChip *chip, PowerPCCPU *cpu);
void (*intc_destroy)(PnvChip *chip, PowerPCCPU *cpu);
void (*intc_print_info)(PnvChip *chip, PowerPCCPU *cpu, GString *buf);
void* (*intc_get)(PnvChip *chip);
ISABus *(*isa_create)(PnvChip *chip, Error **errp);
void (*dt_populate)(PnvChip *chip, void *fdt);
void (*pic_print_info)(PnvChip *chip, GString *buf);
include/hw/ppc/pnv_chiptod.h
+2
View File
@@ -17,6 +17,8 @@ OBJECT_DECLARE_TYPE(PnvChipTOD, PnvChipTODClass, PNV_CHIPTOD)
DECLARE_INSTANCE_CHECKER(PnvChipTOD, PNV9_CHIPTOD, TYPE_PNV9_CHIPTOD)
#define TYPE_PNV10_CHIPTOD TYPE_PNV_CHIPTOD "-POWER10"
DECLARE_INSTANCE_CHECKER(PnvChipTOD, PNV10_CHIPTOD, TYPE_PNV10_CHIPTOD)
#define TYPE_PNV11_CHIPTOD TYPE_PNV_CHIPTOD "-POWER11"
DECLARE_INSTANCE_CHECKER(PnvChipTOD, PNV11_CHIPTOD, TYPE_PNV11_CHIPTOD)
enum tod_state {
tod_error = 0,
include/hw/ppc/pnv_xscom.h
+49
View File
@@ -207,6 +207,55 @@ struct PnvXScomInterfaceClass {
#define PNV10_XSCOM_PIB_SPIC_BASE 0xc0000
#define PNV10_XSCOM_PIB_SPIC_SIZE 0x20
/*
* Power11 core is same as Power10
*/
#define PNV11_XSCOM_EC_BASE(core) PNV10_XSCOM_EC_BASE(core)
#define PNV11_XSCOM_ADU_BASE PNV10_XSCOM_ADU_BASE
#define PNV11_XSCOM_ADU_SIZE PNV10_XSCOM_ADU_SIZE
#define PNV11_XSCOM_QME_BASE(core) PNV10_XSCOM_QME_BASE(core)
#define PNV11_XSCOM_EQ_BASE(core) PNV10_XSCOM_EQ_BASE(core)
#define PNV11_XSCOM_PSIHB_BASE PNV10_XSCOM_PSIHB_BASE
#define PNV11_XSCOM_PSIHB_SIZE PNV10_XSCOM_PSIHB_SIZE
#define PNV11_XSCOM_I2CM_BASE PNV10_XSCOM_I2CM_BASE
#define PNV11_XSCOM_I2CM_SIZE PNV10_XSCOM_I2CM_SIZE
#define PNV11_XSCOM_CHIPTOD_BASE PNV10_XSCOM_CHIPTOD_BASE
#define PNV11_XSCOM_CHIPTOD_SIZE PNV10_XSCOM_CHIPTOD_SIZE
#define PNV11_XSCOM_OCC_BASE PNV10_XSCOM_OCC_BASE
#define PNV11_XSCOM_OCC_SIZE PNV10_XSCOM_OCC_SIZE
#define PNV11_XSCOM_SBE_CTRL_BASE PNV10_XSCOM_SBE_CTRL_BASE
#define PNV11_XSCOM_SBE_CTRL_SIZE PNV10_XSCOM_SBE_CTRL_SIZE
#define PNV11_XSCOM_SBE_MBOX_BASE PNV10_XSCOM_SBE_MBOX_BASE
#define PNV11_XSCOM_SBE_MBOX_SIZE PNV10_XSCOM_SBE_MBOX_SIZE
#define PNV11_XSCOM_PBA_BASE PNV10_XSCOM_PBA_BASE
#define PNV11_XSCOM_PBA_SIZE PNV10_XSCOM_PBA_SIZE
#define PNV11_XSCOM_XIVE2_BASE PNV10_XSCOM_XIVE2_BASE
#define PNV11_XSCOM_XIVE2_SIZE PNV10_XSCOM_XIVE2_SIZE
#define PNV11_XSCOM_N1_CHIPLET_CTRL_REGS_BASE \
PNV10_XSCOM_N1_CHIPLET_CTRL_REGS_BASE
#define PNV11_XSCOM_CHIPLET_CTRL_REGS_SIZE PNV10_XSCOM_CHIPLET_CTRL_REGS_SIZE
#define PNV11_XSCOM_N1_PB_SCOM_EQ_BASE PNV10_XSCOM_N1_PB_SCOM_EQ_BASE
#define PNV11_XSCOM_N1_PB_SCOM_EQ_SIZE PNV10_XSCOM_N1_PB_SCOM_EQ_SIZE
#define PNV11_XSCOM_N1_PB_SCOM_ES_BASE PNV10_XSCOM_N1_PB_SCOM_ES_BASE
#define PNV11_XSCOM_N1_PB_SCOM_ES_SIZE PNV10_XSCOM_N1_PB_SCOM_ES_SIZE
#define PNV11_XSCOM_PIB_SPIC_BASE PNV10_XSCOM_PIB_SPIC_BASE
#define PNV11_XSCOM_PIB_SPIC_SIZE PNV10_XSCOM_PIB_SPIC_SIZE
void pnv_xscom_init(PnvChip *chip, uint64_t size, hwaddr addr);
int pnv_dt_xscom(PnvChip *chip, void *fdt, int root_offset,
uint64_t xscom_base, uint64_t xscom_size,
include/hw/ppc/ppc.h
+1
View File
@@ -52,6 +52,7 @@ struct ppc_tb_t {
#define PPC_DECR_UNDERFLOW_LEVEL (1 << 4) /* Decr interrupt active when
* the most significant bit is 1.
*/
#define PPC_TIMER_PPE (1 << 5) /* Enable PPE support */
uint64_t cpu_ppc_get_tb(ppc_tb_t *tb_env, uint64_t vmclk, int64_t tb_offset);
void cpu_ppc_tb_init(CPUPPCState *env, uint32_t freq);
target/ppc/cpu-models.c
+22 -5
View File
@@ -32,17 +32,20 @@
/* PowerPC CPU definitions */
#define POWERPC_DEF_PREFIX(pvr, svr, type) \
glue(glue(glue(glue(pvr, _), svr), _), type)
#define POWERPC_DEF_SVR(_name, _desc, _pvr, _svr, _type) \
#define POWERPC_DEF_SVR_DEPR(_name, _desc, _pvr, _svr, _type, _deprecation_note) \
static void \
glue(POWERPC_DEF_PREFIX(_pvr, _svr, _type), _cpu_class_init) \
(ObjectClass *oc, const void *data) \
{ \
DeviceClass *dc = DEVICE_CLASS(oc); \
CPUClass *cc = CPU_CLASS(oc); \
PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); \
\
pcc->pvr = _pvr; \
pcc->svr = _svr; \
dc->desc = _desc; \
\
cc->deprecation_note = _deprecation_note; \
} \
\
static const TypeInfo \
@@ -63,6 +66,13 @@
type_init( \
glue(POWERPC_DEF_PREFIX(_pvr, _svr, _type), _cpu_register_types))
#define POWERPC_DEF_SVR(_name, _desc, _pvr, _svr, _type) \
POWERPC_DEF_SVR_DEPR(_name, _desc, _pvr, _svr, _type, NULL)
#define POWERPC_DEPRECATED_CPU(_name, _pvr, _type, _desc, _deprecation_note)\
POWERPC_DEF_SVR_DEPR(_name, _desc, _pvr, POWERPC_SVR_NONE, _type, \
_deprecation_note)
#define POWERPC_DEF(_name, _pvr, _type, _desc) \
POWERPC_DEF_SVR(_name, _desc, _pvr, POWERPC_SVR_NONE, _type)
@@ -116,6 +126,13 @@
NULL)
POWERPC_DEF("x2vp20", CPU_POWERPC_X2VP20, 405,
NULL)
/* PPE42 Embedded Controllers */
POWERPC_DEF("PPE42", CPU_POWERPC_PPE42, ppe42,
"Generic PPE 42")
POWERPC_DEF("PPE42X", CPU_POWERPC_PPE42X, ppe42x,
"Generic PPE 42X")
POWERPC_DEF("PPE42XM", CPU_POWERPC_PPE42XM, ppe42xm,
"Generic PPE 42XM")
/* PowerPC 440 family */
#if defined(TODO_USER_ONLY)
POWERPC_DEF("440", CPU_POWERPC_440, 440GP,
@@ -722,12 +739,12 @@
"POWER7 v2.3")
POWERPC_DEF("power7p_v2.1", CPU_POWERPC_POWER7P_v21, POWER7,
"POWER7+ v2.1")
POWERPC_DEF("power8e_v2.1", CPU_POWERPC_POWER8E_v21, POWER8,
"POWER8E v2.1")
POWERPC_DEPRECATED_CPU("power8e_v2.1", CPU_POWERPC_POWER8E_v21, POWER8,
"POWER8E v2.1", "CPU is unmaintained.")
POWERPC_DEF("power8_v2.0", CPU_POWERPC_POWER8_v20, POWER8,
"POWER8 v2.0")
POWERPC_DEF("power8nvl_v1.0", CPU_POWERPC_POWER8NVL_v10, POWER8,
"POWER8NVL v1.0")
POWERPC_DEPRECATED_CPU("power8nvl_v1.0", CPU_POWERPC_POWER8NVL_v10, POWER8,
"POWER8NVL v1.0", "CPU is unmaintained.")
POWERPC_DEF("power9_v2.0", CPU_POWERPC_POWER9_DD20, POWER9,
"POWER9 v2.0")
POWERPC_DEF("power9_v2.2", CPU_POWERPC_POWER9_DD22, POWER9,

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