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Merge tag 'pull-loongarch-20250928' of https://github.com/bibo-mao/qemu into staging

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loongarch queue

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# 0Z9VAQDuqEzBEj0I3L7AtJgwRxSau+sw9FqUdAjQguM9mA29ggD7BOBFwHpjx68t
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# gpg: Signature made Sun 28 Sep 2025 01:11:39 AM PDT
# gpg:                using EDDSA key 0D8642A3A2659F80B0B3D1A41F7B0C1251ACE7D1
# gpg: Good signature from "bibo mao <maobibo@loongson.cn>" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
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# Primary key fingerprint: 7044 3A00 19C0 E97A 31C7  13C4 8E86 8FB7 A176 9D4C
#      Subkey fingerprint: 0D86 42A3 A265 9F80 B0B3  D1A4 1F7B 0C12 51AC E7D1

* tag 'pull-loongarch-20250928' of https://github.com/bibo-mao/qemu:
  target/loongarch: Only flush one TLB entry in helper_invtlb_page_asid()
  target/loongarch: Only flush one TLB entry in helper_invtlb_page_asid_or_g()
  target/loongarch: Invalid tlb entry in invalidate_tlb()
  target/loongarch: Use loongarch_tlb_search_cb in helper_invtlb_page_asid
  target/loongarch: Use loongarch_tlb_search_cb in helper_invtlb_page_asid_or_g
  target/loongarch: Change return value type with loongarch_tlb_search_cb()
  target/loongarch: Add common API loongarch_tlb_search_cb()
  target/loongarch: Add tlb search callback in loongarch_tlb_search()
  target/loongarch: Fix page size set issue with CSR_STLBPS
  target/loongarch: Update TLB index selection method
  target/loongarch: Reduce TLB flush with helper_tlbwr
  target/loongarch: Add parameter tlb pointer with fill_tlb_entry
  target/loongarch: Use mmu idx bitmap method when flush TLB

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson
2025-09-28 09:01:35 -07:00
parent 7b59aa146a 8d26856fab
commit 4975b64efb
3 changed files with 131 additions and 80 deletions
Download Patch File Download Diff File Expand all files Collapse all files
target/loongarch/cpu-csr.h
+1
View File
@@ -108,6 +108,7 @@ FIELD(CSR_PWCH, DIR4_WIDTH, 18, 6)
#define LOONGARCH_CSR_STLBPS 0x1e /* Stlb page size */
FIELD(CSR_STLBPS, PS, 0, 5)
FIELD(CSR_STLBPS, RESERVE, 5, 27)
#define LOONGARCH_CSR_RVACFG 0x1f /* Reduced virtual address config */
FIELD(CSR_RVACFG, RBITS, 0, 4)
target/loongarch/tcg/csr_helper.c
+3 -2
View File
@@ -26,13 +26,14 @@ target_ulong helper_csrwr_stlbps(CPULoongArchState *env, target_ulong val)
* The real hardware only supports the min tlb_ps is 12
* tlb_ps=0 may cause undefined-behavior.
*/
uint8_t tlb_ps = FIELD_EX64(env->CSR_STLBPS, CSR_STLBPS, PS);
uint8_t tlb_ps = FIELD_EX64(val, CSR_STLBPS, PS);
if (!check_ps(env, tlb_ps)) {
qemu_log_mask(LOG_GUEST_ERROR,
"Attempted set ps %d\n", tlb_ps);
} else {
/* Only update PS field, reserved bit keeps zero */
env->CSR_STLBPS = FIELD_DP64(old_v, CSR_STLBPS, PS, tlb_ps);
val = FIELD_DP64(val, CSR_STLBPS, RESERVE, 0);
env->CSR_STLBPS = val;
}
return old_v;
target/loongarch/tcg/tlb_helper.c
+127 -78
View File
@@ -21,6 +21,18 @@
#include "cpu-csr.h"
#include "tcg/tcg_loongarch.h"
typedef bool (*tlb_match)(bool global, int asid, int tlb_asid);
static bool tlb_match_any(bool global, int asid, int tlb_asid)
{
return global || tlb_asid == asid;
}
static bool tlb_match_asid(bool global, int asid, int tlb_asid)
{
return !global && tlb_asid == asid;
}
bool check_ps(CPULoongArchState *env, uint8_t tlb_ps)
{
if (tlb_ps >= 64) {
@@ -101,8 +113,7 @@ static void invalidate_tlb_entry(CPULoongArchState *env, int index)
target_ulong addr, mask, pagesize;
uint8_t tlb_ps;
LoongArchTLB *tlb = &env->tlb[index];
int mmu_idx = cpu_mmu_index(env_cpu(env), false);
int idxmap = BIT(MMU_KERNEL_IDX) | BIT(MMU_USER_IDX);
uint8_t tlb_v0 = FIELD_EX64(tlb->tlb_entry0, TLBENTRY, V);
uint8_t tlb_v1 = FIELD_EX64(tlb->tlb_entry1, TLBENTRY, V);
uint64_t tlb_vppn = FIELD_EX64(tlb->tlb_misc, TLB_MISC, VPPN);
@@ -112,6 +123,7 @@ static void invalidate_tlb_entry(CPULoongArchState *env, int index)
return;
}
tlb->tlb_misc = FIELD_DP64(tlb->tlb_misc, TLB_MISC, E, 0);
tlb_ps = FIELD_EX64(tlb->tlb_misc, TLB_MISC, PS);
pagesize = MAKE_64BIT_MASK(tlb_ps, 1);
mask = MAKE_64BIT_MASK(0, tlb_ps + 1);
@@ -120,12 +132,12 @@ static void invalidate_tlb_entry(CPULoongArchState *env, int index)
if (tlb_v0) {
tlb_flush_range_by_mmuidx(env_cpu(env), addr, pagesize,
mmu_idx, TARGET_LONG_BITS);
idxmap, TARGET_LONG_BITS);
}
if (tlb_v1) {
tlb_flush_range_by_mmuidx(env_cpu(env), addr + pagesize, pagesize,
mmu_idx, TARGET_LONG_BITS);
idxmap, TARGET_LONG_BITS);
}
}
@@ -144,9 +156,8 @@ static void invalidate_tlb(CPULoongArchState *env, int index)
invalidate_tlb_entry(env, index);
}
static void fill_tlb_entry(CPULoongArchState *env, int index)
static void fill_tlb_entry(CPULoongArchState *env, LoongArchTLB *tlb)
{
LoongArchTLB *tlb = &env->tlb[index];
uint64_t lo0, lo1, csr_vppn;
uint16_t csr_asid;
uint8_t csr_ps;
@@ -198,17 +209,18 @@ static uint32_t get_random_tlb(uint32_t low, uint32_t high)
* field in tlb entry contains bit[47:13], so need adjust.
* virt_vpn = vaddr[47:13]
*/
static bool loongarch_tlb_search(CPULoongArchState *env, vaddr vaddr,
int *index)
static LoongArchTLB *loongarch_tlb_search_cb(CPULoongArchState *env,
vaddr vaddr, int csr_asid,
tlb_match func)
{
LoongArchTLB *tlb;
uint16_t csr_asid, tlb_asid, stlb_idx;
uint8_t tlb_e, tlb_ps, tlb_g, stlb_ps;
uint16_t tlb_asid, stlb_idx;
uint8_t tlb_e, tlb_ps, stlb_ps;
bool tlb_g;
int i, compare_shift;
uint64_t vpn, tlb_vppn;
csr_asid = FIELD_EX64(env->CSR_ASID, CSR_ASID, ASID);
stlb_ps = FIELD_EX64(env->CSR_STLBPS, CSR_STLBPS, PS);
stlb_ps = FIELD_EX64(env->CSR_STLBPS, CSR_STLBPS, PS);
vpn = (vaddr & TARGET_VIRT_MASK) >> (stlb_ps + 1);
stlb_idx = vpn & 0xff; /* VA[25:15] <==> TLBIDX.index for 16KiB Page */
compare_shift = stlb_ps + 1 - R_TLB_MISC_VPPN_SHIFT;
@@ -220,12 +232,11 @@ static bool loongarch_tlb_search(CPULoongArchState *env, vaddr vaddr,
if (tlb_e) {
tlb_vppn = FIELD_EX64(tlb->tlb_misc, TLB_MISC, VPPN);
tlb_asid = FIELD_EX64(tlb->tlb_misc, TLB_MISC, ASID);
tlb_g = FIELD_EX64(tlb->tlb_entry0, TLBENTRY, G);
tlb_g = !!FIELD_EX64(tlb->tlb_entry0, TLBENTRY, G);
if ((tlb_g == 1 || tlb_asid == csr_asid) &&
if (func(tlb_g, csr_asid, tlb_asid) &&
(vpn == (tlb_vppn >> compare_shift))) {
*index = i * 256 + stlb_idx;
return true;
return tlb;
}
}
}
@@ -241,13 +252,30 @@ static bool loongarch_tlb_search(CPULoongArchState *env, vaddr vaddr,
tlb_g = FIELD_EX64(tlb->tlb_entry0, TLBENTRY, G);
compare_shift = tlb_ps + 1 - R_TLB_MISC_VPPN_SHIFT;
vpn = (vaddr & TARGET_VIRT_MASK) >> (tlb_ps + 1);
if ((tlb_g == 1 || tlb_asid == csr_asid) &&
if (func(tlb_g, csr_asid, tlb_asid) &&
(vpn == (tlb_vppn >> compare_shift))) {
*index = i;
return true;
return tlb;
}
}
}
return NULL;
}
static bool loongarch_tlb_search(CPULoongArchState *env, vaddr vaddr,
int *index)
{
int csr_asid;
tlb_match func;
LoongArchTLB *tlb;
func = tlb_match_any;
csr_asid = FIELD_EX64(env->CSR_ASID, CSR_ASID, ASID);
tlb = loongarch_tlb_search_cb(env, vaddr, csr_asid, func);
if (tlb) {
*index = tlb - env->tlb;
return true;
}
return false;
}
@@ -304,23 +332,44 @@ void helper_tlbrd(CPULoongArchState *env)
void helper_tlbwr(CPULoongArchState *env)
{
int index = FIELD_EX64(env->CSR_TLBIDX, CSR_TLBIDX, INDEX);
LoongArchTLB *old, new = {};
bool skip_inv = false;
uint8_t tlb_v0, tlb_v1;
invalidate_tlb(env, index);
old = env->tlb + index;
if (FIELD_EX64(env->CSR_TLBIDX, CSR_TLBIDX, NE)) {
env->tlb[index].tlb_misc = FIELD_DP64(env->tlb[index].tlb_misc,
TLB_MISC, E, 0);
invalidate_tlb(env, index);
return;
}
fill_tlb_entry(env, index);
fill_tlb_entry(env, &new);
/* Check whether ASID/VPPN is the same */
if (old->tlb_misc == new.tlb_misc) {
/* Check whether both even/odd pages is the same or invalid */
tlb_v0 = FIELD_EX64(old->tlb_entry0, TLBENTRY, V);
tlb_v1 = FIELD_EX64(old->tlb_entry1, TLBENTRY, V);
if ((!tlb_v0 || new.tlb_entry0 == old->tlb_entry0) &&
(!tlb_v1 || new.tlb_entry1 == old->tlb_entry1)) {
skip_inv = true;
}
}
/* flush tlb before updating the entry */
if (!skip_inv) {
invalidate_tlb(env, index);
}
*old = new;
}
void helper_tlbfill(CPULoongArchState *env)
{
uint64_t address, entryhi;
int index, set, stlb_idx;
int index, set, i, stlb_idx;
uint16_t pagesize, stlb_ps;
uint16_t asid, tlb_asid;
LoongArchTLB *tlb;
uint8_t tlb_e;
if (FIELD_EX64(env->CSR_TLBRERA, CSR_TLBRERA, ISTLBR)) {
entryhi = env->CSR_TLBREHI;
@@ -334,24 +383,56 @@ void helper_tlbfill(CPULoongArchState *env)
/* Validity of stlb_ps is checked in helper_csrwr_stlbps() */
stlb_ps = FIELD_EX64(env->CSR_STLBPS, CSR_STLBPS, PS);
asid = FIELD_EX64(env->CSR_ASID, CSR_ASID, ASID);
if (pagesize == stlb_ps) {
/* Only write into STLB bits [47:13] */
address = entryhi & ~MAKE_64BIT_MASK(0, R_CSR_TLBEHI_64_VPPN_SHIFT);
/* Choose one set ramdomly */
set = get_random_tlb(0, 7);
/* Index in one set */
set = -1;
stlb_idx = (address >> (stlb_ps + 1)) & 0xff; /* [0,255] */
for (i = 0; i < 8; ++i) {
tlb = &env->tlb[i * 256 + stlb_idx];
tlb_e = FIELD_EX64(tlb->tlb_misc, TLB_MISC, E);
if (!tlb_e) {
set = i;
break;
}
tlb_asid = FIELD_EX64(tlb->tlb_misc, TLB_MISC, ASID);
if (asid != tlb_asid) {
set = i;
}
}
/* Choose one set randomly */
if (set < 0) {
set = get_random_tlb(0, 7);
}
index = set * 256 + stlb_idx;
} else {
/* Only write into MTLB */
index = get_random_tlb(LOONGARCH_STLB, LOONGARCH_TLB_MAX - 1);
index = -1;
for (i = LOONGARCH_STLB; i < LOONGARCH_TLB_MAX; i++) {
tlb = &env->tlb[i];
tlb_e = FIELD_EX64(tlb->tlb_misc, TLB_MISC, E);
if (!tlb_e) {
index = i;
break;
}
tlb_asid = FIELD_EX64(tlb->tlb_misc, TLB_MISC, ASID);
if (asid != tlb_asid) {
index = i;
}
}
if (index < 0) {
index = get_random_tlb(LOONGARCH_STLB, LOONGARCH_TLB_MAX - 1);
}
}
invalidate_tlb(env, index);
fill_tlb_entry(env, index);
fill_tlb_entry(env, env->tlb + index);
}
void helper_tlbclr(CPULoongArchState *env)
@@ -453,61 +534,29 @@ void helper_invtlb_all_asid(CPULoongArchState *env, target_ulong info)
void helper_invtlb_page_asid(CPULoongArchState *env, target_ulong info,
target_ulong addr)
{
uint16_t asid = info & 0x3ff;
int asid = info & 0x3ff;
LoongArchTLB *tlb;
tlb_match func;
for (int i = 0; i < LOONGARCH_TLB_MAX; i++) {
LoongArchTLB *tlb = &env->tlb[i];
uint8_t tlb_g = FIELD_EX64(tlb->tlb_entry0, TLBENTRY, G);
uint16_t tlb_asid = FIELD_EX64(tlb->tlb_misc, TLB_MISC, ASID);
uint64_t vpn, tlb_vppn;
uint8_t tlb_ps, compare_shift;
uint8_t tlb_e = FIELD_EX64(tlb->tlb_misc, TLB_MISC, E);
if (!tlb_e) {
continue;
}
tlb_ps = FIELD_EX64(tlb->tlb_misc, TLB_MISC, PS);
tlb_vppn = FIELD_EX64(tlb->tlb_misc, TLB_MISC, VPPN);
vpn = (addr & TARGET_VIRT_MASK) >> (tlb_ps + 1);
compare_shift = tlb_ps + 1 - R_TLB_MISC_VPPN_SHIFT;
if (!tlb_g && (tlb_asid == asid) &&
(vpn == (tlb_vppn >> compare_shift))) {
tlb->tlb_misc = FIELD_DP64(tlb->tlb_misc, TLB_MISC, E, 0);
}
func = tlb_match_asid;
tlb = loongarch_tlb_search_cb(env, addr, asid, func);
if (tlb) {
invalidate_tlb(env, tlb - env->tlb);
}
tlb_flush(env_cpu(env));
}
void helper_invtlb_page_asid_or_g(CPULoongArchState *env,
target_ulong info, target_ulong addr)
{
uint16_t asid = info & 0x3ff;
int asid = info & 0x3ff;
LoongArchTLB *tlb;
tlb_match func;
for (int i = 0; i < LOONGARCH_TLB_MAX; i++) {
LoongArchTLB *tlb = &env->tlb[i];
uint8_t tlb_g = FIELD_EX64(tlb->tlb_entry0, TLBENTRY, G);
uint16_t tlb_asid = FIELD_EX64(tlb->tlb_misc, TLB_MISC, ASID);
uint64_t vpn, tlb_vppn;
uint8_t tlb_ps, compare_shift;
uint8_t tlb_e = FIELD_EX64(tlb->tlb_misc, TLB_MISC, E);
if (!tlb_e) {
continue;
}
tlb_ps = FIELD_EX64(tlb->tlb_misc, TLB_MISC, PS);
tlb_vppn = FIELD_EX64(tlb->tlb_misc, TLB_MISC, VPPN);
vpn = (addr & TARGET_VIRT_MASK) >> (tlb_ps + 1);
compare_shift = tlb_ps + 1 - R_TLB_MISC_VPPN_SHIFT;
if ((tlb_g || (tlb_asid == asid)) &&
(vpn == (tlb_vppn >> compare_shift))) {
tlb->tlb_misc = FIELD_DP64(tlb->tlb_misc, TLB_MISC, E, 0);
}
func = tlb_match_any;
tlb = loongarch_tlb_search_cb(env, addr, asid, func);
if (tlb) {
invalidate_tlb(env, tlb - env->tlb);
}
tlb_flush(env_cpu(env));
}
bool loongarch_cpu_tlb_fill(CPUState *cs, vaddr address, int size,